JPS5945930U - Semiconductor element mounting structure - Google Patents

Semiconductor element mounting structure

Info

Publication number
JPS5945930U
JPS5945930U JP1982142032U JP14203282U JPS5945930U JP S5945930 U JPS5945930 U JP S5945930U JP 1982142032 U JP1982142032 U JP 1982142032U JP 14203282 U JP14203282 U JP 14203282U JP S5945930 U JPS5945930 U JP S5945930U
Authority
JP
Japan
Prior art keywords
semiconductor element
main surface
mounting structure
element mounting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982142032U
Other languages
Japanese (ja)
Other versions
JPH0119395Y2 (en
Inventor
鳥羽　進
博 渡部
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP1982142032U priority Critical patent/JPS5945930U/en
Publication of JPS5945930U publication Critical patent/JPS5945930U/en
Application granted granted Critical
Publication of JPH0119395Y2 publication Critical patent/JPH0119395Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来構造を示すものでありａは平面図、ｂは同
図ａのｘ−ｘ’断面図、第２図は本考案の実施例を示す
ものであり、ａは平面図、ｂは同図ａのＹ−Ｙ’断面図
である。 １・・・半導体素子、３・・・金属細線、４・・・基板
、５・・・配線導体、６・・・導電性スルーホール、７
・・・導電端子、９・・・電極。Fig. 1 shows a conventional structure, where a is a plan view, b is a sectional view taken along line xx' in a of the same figure, and Fig. 2 shows an embodiment of the present invention, where a is a plan view and b is a sectional view taken along line Y-Y' in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 3... Metal thin wire, 4... Substrate, 5... Wiring conductor, 6... Conductive through hole, 7
... Conductive terminal, 9... Electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板の一主表面上に半導体素子を搭載し、該素子の電極
と基板の導体パターンとを金属細線により接続するもの
において、該導体パターンを前記−主表面上の素子周辺
に形成される配線導体と、前記素子と配線導体との間に
位置し前記−主面から他の主表面に貫通する導電性スル
ーホールを有する導電端子とから構成することを特徴と
する半導体素子の実装構造。In a device in which a semiconductor element is mounted on one main surface of a substrate, and an electrode of the element is connected to a conductor pattern of the substrate by a thin metal wire, the conductor pattern is connected to a wiring conductor formed around the element on the main surface. and a conductive terminal having a conductive through hole located between the element and the wiring conductor and penetrating from the main surface to the other main surface.
JP1982142032U 1982-09-20 1982-09-20 Semiconductor element mounting structure Granted JPS5945930U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982142032U JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982142032U JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Publications (2)

Publication Number Publication Date
JPS5945930U true JPS5945930U (en) 1984-03-27
JPH0119395Y2 JPH0119395Y2 (en) 1989-06-05

Family

ID=30317487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982142032U Granted JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Country Status (1)

Country Link
JP (1) JPS5945930U (en)

Also Published As

Publication number Publication date
JPH0119395Y2 (en) 1989-06-05

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