JPH0119395Y2 - - Google Patents

Info

Publication number
JPH0119395Y2
JPH0119395Y2 JP1982142032U JP14203282U JPH0119395Y2 JP H0119395 Y2 JPH0119395 Y2 JP H0119395Y2 JP 1982142032 U JP1982142032 U JP 1982142032U JP 14203282 U JP14203282 U JP 14203282U JP H0119395 Y2 JPH0119395 Y2 JP H0119395Y2
Authority
JP
Japan
Prior art keywords
substrate
conductive
main surface
electrodes
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982142032U
Other languages
Japanese (ja)
Other versions
JPS5945930U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982142032U priority Critical patent/JPS5945930U/en
Publication of JPS5945930U publication Critical patent/JPS5945930U/en
Application granted granted Critical
Publication of JPH0119395Y2 publication Critical patent/JPH0119395Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

Description

【考案の詳細な説明】 本考案は特に混成集積回路に用いられる半導体
素子の実装構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a mounting structure for semiconductor elements used in hybrid integrated circuits.

最近、混成集積回路に使用される半導体素子
は、その集積化に伴い素子の接続用電極は増加の
傾向にある。一方、この電極は外部との接続の関
係で素子の縁に沿つて配置されるのが一般的であ
り、このため電極数が増大すると共にこの電極の
数により素子の寸法が決まつてくる場合がある。
したがつて、電極寸法を極力小さくする方が有利
である。
Recently, as semiconductor elements used in hybrid integrated circuits become more integrated, the number of connection electrodes for the elements tends to increase. On the other hand, these electrodes are generally arranged along the edge of the device for connection with the outside, and as a result, as the number of electrodes increases, the dimensions of the device are determined by the number of electrodes. There is.
Therefore, it is advantageous to make the electrode dimensions as small as possible.

しかしながら素子の電極を小さくし電極数を増
した場合、基板側配線導体(導体パターン)に次
の様な問題がある。すなわち第1図の一部平面図
a及び第1図aをX−X′にて切断した断面図b
に示す様に、半導体素子1の電極2を金属細線3
を介して接続される基板4上の配線導体5は半導
体素子1周辺に形成されるため、配線導体5を素
子の電極2と同様寸法に小さくする必要がある
が、印刷方法による電極寸法(同図においてAと
Bの和に相当する)には量産ベースで考えたとき
現況では200〜300μmという限界がある。
However, when the electrodes of the element are made smaller and the number of electrodes is increased, the following problems arise with the wiring conductor (conductor pattern) on the substrate side. That is, a partial plan view a of FIG. 1 and a sectional view b taken along X-X′ of FIG. 1 a.
As shown in FIG.
Since the wiring conductor 5 on the substrate 4 to be connected via is formed around the semiconductor element 1, it is necessary to reduce the wiring conductor 5 to the same size as the electrode 2 of the element. (corresponding to the sum of A and B in the figure) currently has a limit of 200 to 300 μm when considered on a mass production basis.

また配線導体の数を増すには電極位置を素子周
辺より遠ざけて周辺寸法を増す方法も考えられる
が、素子周辺よりあまり遠ざけることは電極と配
線導体との接続が金属細線であることより限界が
あり、信頼性上好ましくない。
Additionally, in order to increase the number of wiring conductors, it is possible to increase the peripheral dimensions by moving the electrodes further away from the periphery of the element, but there is a limit to placing the electrodes too far away from the periphery of the element because the connections between the electrodes and the wiring conductors are thin metal wires. Yes, unfavorable in terms of reliability.

本考案は上記の欠点を除去し、極力、素子周辺
に近い基板上へ多くの導体パターンを設け、素子
の小形化に対応した素子基板間の接続を実現する
ことを目的とする。
The present invention aims to eliminate the above-mentioned drawbacks, provide as many conductor patterns on the substrate as close to the periphery of the element as possible, and realize connections between element substrates that correspond to the miniaturization of the element.

この目的は本考案によれば、基板の一主表面上
に半導体素子を塔載し、該素子の電極と基板の導
体パターンとを金属細線により接続するものにお
いて、該導体パターンを前記一主面上の素子周辺
に形成される配線導体と、前記素子と配線導体と
の間に位置し前記一主表面上から他の主表面に貫
通する導電性スルーホールを有する導電端子とか
ら構成することにより達成される。
According to the present invention, this purpose is to mount a semiconductor element on one main surface of a substrate, and connect the electrode of the element to a conductor pattern of the substrate by a thin metal wire, in which the conductor pattern is connected to the one main surface of the substrate. By comprising a wiring conductor formed around the upper element, and a conductive terminal having a conductive through hole located between the element and the wiring conductor and penetrating from the one main surface to the other main surface. achieved.

第2図は本考案の実施例を示し、同図aは平面
図、同図bは図aをY−Y′にて切断した断面図
であり、第1図と同様のものには同符号を付して
いる。すなわち第1図の従来例と異なる点は、配
線導体5と半導体素子1との間に導電性スルーホ
ール6を有する導電端子7を設けたことであり、
この導電端子7と配線導体5とで基板の導体パタ
ーンを構成している。導電端子7は配線導体5よ
り素子1側にあれば、その位置及び数は特に限定
されるものではないが、少なくとも導電端子7の
金属細線接続部は細線同士の接触を防ぐため、配
線導体5の絶縁領域8の延長上にあることが好ま
しい。
Fig. 2 shows an embodiment of the present invention, Fig. 2a is a plan view, Fig. 2b is a sectional view taken along Y-Y' in Fig. is attached. That is, the difference from the conventional example shown in FIG. 1 is that a conductive terminal 7 having a conductive through hole 6 is provided between the wiring conductor 5 and the semiconductor element 1.
The conductive terminal 7 and the wiring conductor 5 constitute a conductive pattern on the board. As long as the conductive terminals 7 are closer to the element 1 than the wiring conductor 5, their position and number are not particularly limited. It is preferable that the insulation region 8 be located on an extension of the insulating region 8 .

このように構成することにより、素子1の電極
9よりスルーホール6を有する導電端子7へ金属
細線3にて接続し、次の接続を導電端子7を飛び
越えて配線導体5へ接続する。これを交互に行う
ことにより基板4上の素子1周辺に従来の約2倍
の電極接続が可能となる。導電端子7は、第2図
bに示す様に導電性スルーホール6を介して基板
7裏面へ引出され、裏面に構成された回路に接続
されるか又は適当な位置まで導かれ導電性スルー
ホール又は基板周辺にて再び基板4の表面へ接続
することも可能である。
With this configuration, the electrode 9 of the element 1 is connected to the conductive terminal 7 having the through hole 6 using the thin metal wire 3, and the next connection is made by jumping over the conductive terminal 7 and connecting to the wiring conductor 5. By performing this alternately, it is possible to connect about twice as many electrodes around the element 1 on the substrate 4 as in the conventional method. As shown in FIG. 2b, the conductive terminal 7 is drawn out to the back surface of the substrate 7 through the conductive through hole 6 and connected to a circuit configured on the back surface, or is guided to an appropriate position and connected to the conductive through hole. Alternatively, it is also possible to connect to the surface of the substrate 4 again around the substrate.

このように本考案によれば、基板上の素子周辺
に多数の電極を設けることができるため、素子の
電極数を素子の小形化を図りつつ増すことがで
き、また基板裏面への回路の構成が容易となるこ
とも相俟つて、全体として装置の小形化・集積化
が可能となる。
As described above, according to the present invention, a large number of electrodes can be provided around the element on the substrate, so the number of electrodes on the element can be increased while making the element smaller, and the circuit can be configured on the back side of the substrate. Coupled with this, it becomes possible to downsize and integrate the device as a whole.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来構造を示すものでありaは平面
図、bは同図aのX−X′断面図、第2図は本考
案の実施例を示すものであり、aは平面図、bは
同図aのY−Y′断面図である。 1……半導体素子、3……金属細線、4……基
板、5……配線導体、6……導電性スルーホー
ル、7……導電端子、9……電極。
Fig. 1 shows a conventional structure, where a is a plan view, b is a sectional view taken along line is a sectional view taken along line Y-Y' in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 3... Metal thin wire, 4... Substrate, 5... Wiring conductor, 6... Conductive through hole, 7... Conductive terminal, 9... Electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板の一主表面上に半導体素子を塔載し、該素
子の電極と基板の導体パターンとを金属細線によ
り接続するものにおいて、該導体パターンを前記
一主表面上の素子周辺に形成される配線導体と、
前記素子と配線導体との間に位置し前記一主面か
ら他の主表面に貫通する導電性スルーホールを有
する導電端子とから構成することを特徴とする半
導体素子の実装構造。
In a device in which a semiconductor element is mounted on one main surface of a substrate, and an electrode of the element is connected to a conductive pattern of the substrate by a thin metal wire, the conductive pattern is connected to a wiring formed around the element on the one main surface. a conductor;
A mounting structure for a semiconductor element, comprising a conductive terminal having a conductive through hole located between the element and the wiring conductor and penetrating from the one main surface to the other main surface.
JP1982142032U 1982-09-20 1982-09-20 Semiconductor element mounting structure Granted JPS5945930U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982142032U JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982142032U JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Publications (2)

Publication Number Publication Date
JPS5945930U JPS5945930U (en) 1984-03-27
JPH0119395Y2 true JPH0119395Y2 (en) 1989-06-05

Family

ID=30317487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982142032U Granted JPS5945930U (en) 1982-09-20 1982-09-20 Semiconductor element mounting structure

Country Status (1)

Country Link
JP (1) JPS5945930U (en)

Also Published As

Publication number Publication date
JPS5945930U (en) 1984-03-27

Similar Documents

Publication Publication Date Title
JPH0358550B2 (en)
JP3138539B2 (en) Semiconductor device and COB substrate
JPH0119395Y2 (en)
JPS6362339A (en) Semiconductor device
JPS5980957A (en) Semiconductor device
JPH0458189B2 (en)
JPH0349420Y2 (en)
JPH019160Y2 (en)
JP2743524B2 (en) Hybrid integrated circuit device
JPH0126108Y2 (en)
JPH0722577A (en) Hybrid integrated circuit device
JP2815003B2 (en) Hybrid integrated circuit device
JPH0427131A (en) Electronic component mounting board
JPH0714657U (en) Semiconductor device
JPS59166435U (en) porcelain capacitor block
JPS62166640U (en)
JPH02102594A (en) Hybrid integrated circuit substrate
JPH03261079A (en) Hybrid integrated circuit
JPS61144049A (en) Substrate for hybrid integrated circuit
JPH08222688A (en) Hybrid integrated circuit device
JPS6165443A (en) Built-in method for ic chip
JPS59929A (en) Assembled body of electric circuit
JPS6122380U (en) hybrid integrated circuit board
JPS59182935U (en) Semiconductor integrated circuit device
JPS60129157U (en) Substrate for hybrid integrated circuits