JPH03261079A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH03261079A JPH03261079A JP2058571A JP5857190A JPH03261079A JP H03261079 A JPH03261079 A JP H03261079A JP 2058571 A JP2058571 A JP 2058571A JP 5857190 A JP5857190 A JP 5857190A JP H03261079 A JPH03261079 A JP H03261079A
- Authority
- JP
- Japan
- Prior art keywords
- board
- integrated circuit
- hybrid integrated
- circuit
- external terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000010354 integration Effects 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路に関し、特にプリント配線基板に
複数の半導体チップなどを搭載した混成集積回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit in which a plurality of semiconductor chips and the like are mounted on a printed wiring board.
従来：この種の混成集積回路は、第４図の斜視図および
同図のＡ−Ａ断面を示す第５図のように、外部回路との
接続のための外部端子８は、プリント配線基板１の周辺
にのみ取付けられ、コーティング樹脂６で保護されたベ
アチップ状態の半導体素子２の電極は、ワイヤ５．導体
パターン４を通じて外部端子８に導かれていた。Conventional: In this type of hybrid integrated circuit, as shown in the perspective view of FIG. 4 and in FIG. The electrodes of the semiconductor element 2 in a bare chip state, which is attached only around the periphery of the wire 5 and protected by the coating resin 6, are connected to the wire 5. It was led to an external terminal 8 through the conductor pattern 4.
上述した従来の混成集積回路は、それを構成するプリン
ト配線基板の周辺にのみ外部端子を取り付けているので
、多数のピン（外部端子）を必要とする混成集積回路の
場合、外部端子を取り付ける辺の長さは、搭載する部品
の占有面積に拘わらず、（−辺に取り付ける端子数）×
（端子間ピッチ）の長さが必要であった。また、搭載し
た半導体素子から、端子が取り付けられる基板周辺迄の
導体配線パターンが必要であった。この様に、従来の混
成集積回路は、搭載する部品の占有面積が小さくても、
多ピンを要する場合、基板を大型にしなげればならない
という欠点を有する。In the conventional hybrid integrated circuit described above, external terminals are attached only to the periphery of the printed wiring board that makes up the circuit, so in the case of a hybrid integrated circuit that requires a large number of pins (external terminals), the external terminals are attached to the edges. Regardless of the area occupied by the mounted components, the length of
(pitch between terminals) was required. Further, a conductive wiring pattern was required from the mounted semiconductor element to the periphery of the substrate to which the terminals were attached. In this way, conventional hybrid integrated circuits, even if the mounted components occupy a small area,
If a large number of pins are required, the disadvantage is that the board must be made large.
本発明の混成集積回路は、半導体素子を搭載するプリン
ト配線基板の周辺ばかりでなく、内側の部品搭載部分に
も外部回路と接続するための外部端子を設けている。The hybrid integrated circuit of the present invention is provided with external terminals for connection to external circuits not only in the periphery of the printed wiring board on which the semiconductor element is mounted, but also in the internal component mounting area.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図は、本発明の一実施例を示す斜視図、第２図は、
第１図のＡＡ線での断面図である。第１図と第２図にお
いて、コーティング樹脂６によってコーティングされ、
ワイヤ５によって、導体パターン４と接続されたベアチ
ップの半導体素子２が搭載されたプリント配線基板１の
周辺に、基板１の下面から下方に突き出た外部端子７の
多数が内外２重列に取付けられている他に、基板中央の
コーティング樹脂６の下にも取付けられている。FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing an embodiment of the present invention.
2 is a sectional view taken along line AA in FIG. 1. FIG. 1 and 2, coated with coating resin 6,
A large number of external terminals 7 protruding downward from the bottom surface of the board 1 are attached in double rows inside and outside around the printed wiring board 1 on which a bare chip semiconductor element 2 connected to a conductor pattern 4 is mounted by wires 5. In addition to this, it is also attached under the coating resin 6 at the center of the board.
これにより１２０本の外部端子が必要な混成集積回路の
場合、端子間ピッチが２．５４ｍｍ、コーティング樹脂
面積が４００ｍｍ”であれば、従来約６４００ｍｍ２０
基板が必要であったものを、約２５０．０ｍｍ２で実現
できるようになる。As a result, in the case of a hybrid integrated circuit that requires 120 external terminals, if the pitch between the terminals is 2.54 mm and the coating resin area is 400 mm, the conventional method would be approximately 6400 mm20.
What used to require a board can now be realized with a size of approximately 250.0 mm2.
第３図は本発明の第２の実施例を示す斜視図である。こ
の実施例では、コーティング樹脂６で覆われた半導体素
子の他に、表面実装部品３も搭載され、基板周辺の外部
端子の他に各部品の間にも外部端子７を取り付けた構造
となっている。この実施例では、搭載部品から外部端子
迄の導体配線パターンが短く、低インピーダンスで実現
できるので、小型、高性能の混成集積回路を実現できる
利点がある。FIG. 3 is a perspective view showing a second embodiment of the invention. In this embodiment, in addition to the semiconductor element covered with the coating resin 6, surface mount components 3 are also mounted, and in addition to external terminals around the board, external terminals 7 are also attached between each component. There is. In this embodiment, the conductor wiring pattern from the mounted components to the external terminals is short and can be realized with low impedance, so there is an advantage that a compact, high-performance hybrid integrated circuit can be realized.
以上説明したように本発明は、複数のベアチップ状態の
半導体素子を搭載する混成集積回路のベースとなるプリ
ント配線基板に、周辺のみならず、内側の搭載部品の近
辺にも、外部端子を取り付ける事により、混成集積回路
のザイズを小型化できる効果がある。As explained above, the present invention is capable of attaching external terminals not only to the periphery but also near internal mounted components to a printed wiring board that serves as the base of a hybrid integrated circuit on which a plurality of semiconductor elements in the form of bare chips are mounted. This has the effect of reducing the size of the hybrid integrated circuit.
第１図は本発明の第１実施例の斜視図、第２図は第１図
のＡ−Ａ断面図、第３図は本発明の第２実施例の斜視図
、第斗図は従来の混成集積回路の斜視図、第５図は第４
図のＡ−Ａ断面図である。
ｌ・・・・・・プリント配線基板、２・・・・・・半導
体素子、３・・・・・・表面実装部品、４・・・・・・
導体（配線）パターン、５・・・・・・ワイヤ、６・・
・・・・コーティング樹脂、７．８・・・・・・外部端
子。Fig. 1 is a perspective view of the first embodiment of the present invention, Fig. 2 is a sectional view taken along the line A-A in Fig. 1, Fig. 3 is a perspective view of the second embodiment of the invention, and Fig. 2 is a perspective view of the conventional A perspective view of a hybrid integrated circuit, FIG.
It is an AA sectional view of the figure. 1...Printed wiring board, 2...Semiconductor element, 3...Surface mount component, 4...
Conductor (wiring) pattern, 5...Wire, 6...
...Coating resin, 7.8...External terminal.
Claims (1)
部品をプリント配線基板に搭載し、ワイヤボンディング
によって、基板とベアチップの電気的接続がなされてい
る混成集積回路において、前記プリント配線基板の周辺
に沿って外部接続用の端子が少くとも一列に設けられて
いる他に、この端子列の内側の半導体素子などの搭載部
品の搭載部の近傍にも外部端子が設けられていることを
特徴とする混成集積回路。In a hybrid integrated circuit in which a mounted component including at least a plurality of semiconductor elements in a bare chip state is mounted on a printed wiring board, and the board and bare chip are electrically connected by wire bonding, along the periphery of the printed wiring board. A hybrid integration characterized in that terminals for external connections are provided in at least one row, and external terminals are also provided in the vicinity of the mounting portion of mounted components such as semiconductor elements inside this terminal row. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2058571A JPH03261079A (en) | 1990-03-08 | 1990-03-08 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2058571A JPH03261079A (en) | 1990-03-08 | 1990-03-08 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03261079A true JPH03261079A (en) | 1991-11-20 |
Family
ID=13088127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2058571A Pending JPH03261079A (en) | 1990-03-08 | 1990-03-08 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03261079A (en) |
-
1990
- 1990-03-08 JP JP2058571A patent/JPH03261079A/en active Pending
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