JPS59109150U - IC chip package - Google Patents

IC chip package

Info

Publication number
JPS59109150U
JPS59109150U JP246683U JP246683U JPS59109150U JP S59109150 U JPS59109150 U JP S59109150U JP 246683 U JP246683 U JP 246683U JP 246683 U JP246683 U JP 246683U JP S59109150 U JPS59109150 U JP S59109150U
Authority
JP
Japan
Prior art keywords
chip package
package
chip
signal conductor
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP246683U
Other languages
Japanese (ja)
Other versions
JPH0126109Y2 (en
Inventor
高野　勇
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP246683U priority Critical patent/JPS59109150U/en
Publication of JPS59109150U publication Critical patent/JPS59109150U/en
Application granted granted Critical
Publication of JPH0126109Y2 publication Critical patent/JPH0126109Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＩＣチップ用パッケージの平面を示した
図、第２図は第１図に示した従来のＩＣチップ用パッケ
ージの断面を示した図である。第３図は、本考案のＩＣ
チップ用パッケージの構成を説明するために示した図、
第４図は第３図のＸ−ｘ′間の断面を示したものである
。第５図は、本考案の効果を説明するために示した図で
ある。 □第６図は本考案のＩＣチップ用パッケージに外部回路
との接続用リードを備えた態様の平面図であり、第７図
は第６図のＹ−Ｙ’間の断面わ示した図である。 なお図中の記号は、それぞれ次のものを示している。１
１０１．２１０１・・・リード、１１０２゜２１０２．
３１０２，４１０２．５１０２川パツケ一ジ本体、１１
０３，２１０６，３１０３゜４１０３．５１０３・・・
信号゛導体パターン、１１０４．２１０４・・・ＩＣＣ
チップ搭載用クランド部２１０５．３１０５．４１０５
・・・放熱用スタッド、２１０６．４１０６・・・ＩＣ
チップ、２１０７．４１０’？・・・ボンディングワイ
ヤ、２１０８．４１０８・・・パッケージキャップ、３
１０１．４１０１．５１０１・・・接地導体パターン。 第１図 第５図２FIG. 1 is a plan view of a conventional IC chip package, and FIG. 2 is a cross-sectional view of the conventional IC chip package shown in FIG. Figure 3 shows the IC of the present invention.
A diagram shown to explain the configuration of a chip package,
FIG. 4 shows a cross section taken along line X-x' in FIG. 3. FIG. 5 is a diagram shown to explain the effects of the present invention. □ Fig. 6 is a plan view of an embodiment of the IC chip package of the present invention equipped with leads for connection to an external circuit, and Fig. 7 is a cross-sectional view taken along Y-Y' in Fig. 6. be. The symbols in the figure indicate the following, respectively. 1
101.2101...Reed, 1102°2102.
3102,4102.5102 River package unit body, 11
03,2106,3103゜4103.5103...
Signal conductor pattern, 1104.2104...ICC
Crank part for chip mounting 2105.3105.4105
...Heat radiation stud, 2106.4106...IC
Chip, 2107.410'? ...Bonding wire, 2108.4108...Package cap, 3
101.4101.5101...Ground conductor pattern. Figure 1 Figure 5 Figure 2

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フラットパックタイプのＩＣチップ用パッケージにおい
て、゛前記ＩＣチップ用パッケージ内の各信号導体パタ
ーンと同一平面上で各信号導体ではさまれる部分と、前
記ＩＣチップ用パッケージを形成する誘電体基板の裏面
とにそれぞれ連続した接地導体パターンを設け、さらに
これら接地導体パターンと電気的に導通された放熱用ス
タッドをパッケージ裏側に設けると共に、前記ＩＣチッ
プ用パッケージを回路基板に搭載する時の電気的接続部
として、前記各信号導体パターンと前記放熱用スタンド
とを用いることを特徴とするＩＣチップ用パッケージ。In a flat pack type IC chip package, ``a portion sandwiched between each signal conductor on the same plane as each signal conductor pattern in the IC chip package, and a back surface of a dielectric substrate forming the IC chip package; A continuous ground conductor pattern is provided on each of the IC chip packages, and a heat radiation stud electrically connected to these ground conductor patterns is provided on the back side of the package, and serves as an electrical connection part when mounting the IC chip package on a circuit board. , an IC chip package characterized in that each of the signal conductor patterns and the heat dissipation stand are used.
JP246683U 1983-01-12 1983-01-12 IC chip package Granted JPS59109150U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP246683U JPS59109150U (en) 1983-01-12 1983-01-12 IC chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP246683U JPS59109150U (en) 1983-01-12 1983-01-12 IC chip package

Publications (2)

Publication Number Publication Date
JPS59109150U true JPS59109150U (en) 1984-07-23
JPH0126109Y2 JPH0126109Y2 (en) 1989-08-04

Family

ID=30134129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP246683U Granted JPS59109150U (en) 1983-01-12 1983-01-12 IC chip package

Country Status (1)

Country Link
JP (1) JPS59109150U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213364A (en) * 1987-02-27 1988-09-06 Ibiden Co Ltd Semiconductor mounting board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4980569A (en) * 1972-12-12 1974-08-03
JPS57154861A (en) * 1981-03-20 1982-09-24 Hitachi Ltd Package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4980569A (en) * 1972-12-12 1974-08-03
JPS57154861A (en) * 1981-03-20 1982-09-24 Hitachi Ltd Package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213364A (en) * 1987-02-27 1988-09-06 Ibiden Co Ltd Semiconductor mounting board

Also Published As

Publication number Publication date
JPH0126109Y2 (en) 1989-08-04

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