JPS63187341U - - Google Patents
Info
- Publication number
- JPS63187341U JPS63187341U JP7736287U JP7736287U JPS63187341U JP S63187341 U JPS63187341 U JP S63187341U JP 7736287 U JP7736287 U JP 7736287U JP 7736287 U JP7736287 U JP 7736287U JP S63187341 U JPS63187341 U JP S63187341U
- Authority
- JP
- Japan
- Prior art keywords
- package
- power supply
- chip
- signal wiring
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は従来のＩＣパツケージの上面図、断面
図及び側面図、第２図は従来のパツケージの組み
立て例を示す斜視図、第３図は従来のＩＣパツケ
ージのアイソレーシヨン特性図、第４図は従来の
ＩＣパツケージのＩＣチツプ搭載時の電源供給部
分の断面図とその等価回路、第５図は電源供給ラ
イン部分でのインダクタンスの影響を示す特性図
、第６図は本考案のＩＣパツケージの上面図、断
面図及び側面図、第７図は本考案のＩＣパツケー
ジの組み立て例を示す斜視図、第８図は本考案の
ＩＣパツケージと従来のＩＣパツケージのアイソ
レーシヨン特性の比較を示した特性図、第９図は
本考案のＩＣパツケージの上面図、断面図及び側
面図である。
１……入出力信号端子、２……電源供給用端子
、２′……電源供給用端子部分での寄生インダク
タンス、３……ＩＣチツプ搭載部、４……ＩＣチ
ツプ、５，５′……大容量コンデンサ、６……金
属のふた、７……ボンデイングワイヤ、７′……
ボンデイングワイヤのインダクタンス、１０……
大容量コンデンサ搭載の凹部、１１……ＩＣ接地
用金属ポスト。
Fig. 1 is a top view, sectional view, and side view of a conventional IC package, Fig. 2 is a perspective view showing an example of assembly of the conventional package, Fig. 3 is an isolation characteristic diagram of the conventional IC package, and Fig. 4 is a diagram showing the isolation characteristics of the conventional IC package. The figure shows a cross-sectional view of the power supply part of a conventional IC package when an IC chip is mounted and its equivalent circuit, Figure 5 is a characteristic diagram showing the influence of inductance in the power supply line part, and Figure 6 shows the IC package of the present invention. 7 is a perspective view showing an example of the assembly of the IC package of the present invention, and FIG. 8 is a comparison of isolation characteristics between the IC package of the present invention and a conventional IC package. FIG. 9 shows a top view, a sectional view, and a side view of the IC package of the present invention. 1... Input/output signal terminal, 2... Power supply terminal, 2'... Parasitic inductance at the power supply terminal portion, 3... IC chip mounting part, 4... IC chip, 5, 5'... Large capacity capacitor, 6...metal lid, 7...bonding wire, 7'...
Bonding wire inductance, 10...
Concave part with large capacity capacitor mounted, 11...metal post for IC grounding.
Claims (1)
搭載するための凹部を有するパツケージ本体と金
属材料の蓋を具備するＩＣパツケージにおいて、
該凹部をはさんで単数あるいは複数の容量素子を
搭載し、該単数あるいは複数の容量素子の少なく
とも１つの信号配線パタンを搭載させる埋込み誘
電体ラインが配置され、該ＩＣチツプの各信号配
線端子と該各信号配線パタンはボンデイングワイ
ヤで接続され、該ＩＣチツプの各電源供給用端子
と該単数あるいは複数の容量素子とはボンデイン
グワイヤで接続され、各容量素子と該パツケージ
本体の周辺に配置された単数あるいは複数の埋込
み誘電体上に搭載された各電源供給用端子とはボ
ンデイングワイヤで接続されたことを特徴とする
ＩＣパツケージ。 (2) 前記単数または複数の容量素子は単一の高
誘電率基板上に搭載された複数に分割された金属
パタンにより構成され、該各金属パタンは前記電
源供給用端子とボンデイングワイヤで接続された
ことを特徴とする実用新案登録請求の範囲第１項
に記載のＩＣパツケージ。[Claims for Utility Model Registration] (1) An IC package comprising a package body made mostly of metal material and having a recess for mounting an IC chip, and a lid made of metal material,
A buried dielectric line is disposed across the recess, on which one or more capacitors are mounted, and on which at least one signal wiring pattern of the one or more capacitors is mounted, and is connected to each signal wiring terminal of the IC chip. Each of the signal wiring patterns is connected with a bonding wire, each power supply terminal of the IC chip and the one or more capacitive elements are connected with a bonding wire, and each of the power supply terminals of the IC chip is connected with the one or more capacitive elements, and each of the signal wiring patterns is arranged around each capacitive element and the package body. An IC package characterized in that power supply terminals mounted on one or more embedded dielectrics are connected by bonding wires. (2) The single or plurality of capacitive elements are constituted by a metal pattern divided into a plurality of parts mounted on a single high dielectric constant substrate, and each metal pattern is connected to the power supply terminal by a bonding wire. The IC package according to claim 1 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987077362U JPH0720920Y2 (en) | 1987-05-25 | 1987-05-25 | IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987077362U JPH0720920Y2 (en) | 1987-05-25 | 1987-05-25 | IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63187341U true JPS63187341U (en) | 1988-11-30 |
| JPH0720920Y2 JPH0720920Y2 (en) | 1995-05-15 |
Family
ID=30925295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987077362U Expired - Lifetime JPH0720920Y2 (en) | 1987-05-25 | 1987-05-25 | IC package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0720920Y2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007081125A (en) * | 2005-09-14 | 2007-03-29 | Toshiba Corp | High frequency package |
| JP2017045957A (en) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | High frequency semiconductor device |
| CN111199965A (en) * | 2018-11-16 | 2020-05-26 | 模拟设备国际无限公司 | Regulator circuit packaging techniques |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134060A (en) * | 1984-12-04 | 1986-06-21 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
-
1987
- 1987-05-25 JP JP1987077362U patent/JPH0720920Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134060A (en) * | 1984-12-04 | 1986-06-21 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007081125A (en) * | 2005-09-14 | 2007-03-29 | Toshiba Corp | High frequency package |
| JP4575261B2 (en) * | 2005-09-14 | 2010-11-04 | 株式会社東芝 | High frequency package |
| JP2017045957A (en) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | High frequency semiconductor device |
| CN111199965A (en) * | 2018-11-16 | 2020-05-26 | 模拟设备国际无限公司 | Regulator circuit packaging techniques |
| CN111199965B (en) * | 2018-11-16 | 2023-11-03 | 亚德诺半导体国际无限责任公司 | Regulator circuit packaging techniques |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0720920Y2 (en) | 1995-05-15 |
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