GB2172429A - Electronic circuit assembly - Google Patents
Electronic circuit assembly Download PDFInfo
- Publication number
- GB2172429A GB2172429A GB08605664A GB8605664A GB2172429A GB 2172429 A GB2172429 A GB 2172429A GB 08605664 A GB08605664 A GB 08605664A GB 8605664 A GB8605664 A GB 8605664A GB 2172429 A GB2172429 A GB 2172429A
- Authority
- GB
- United Kingdom
- Prior art keywords
- substrate
- electronic circuit
- circuit assembly
- dice
- contact pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Emergency Protection Circuit Devices (AREA)
- Burglar Alarm Systems (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
An electronic circuit assembly comprises one or more integrated circuit dice 30 with contact pads 34, which are connected to corresponding pads 24 on a silicon substrate 20. The substrate 20 itself has active semiconductor devices 50 integrated within it and electrically connected with the contact pads 24. The substrate 20 has a larger surface than the dice 30 and external electrical connection of the assembly is made via conductive elements 23 on that part of the substrate projecting beyond the dice. The pattern of integration in the integrated circuit dice may be a mirror image of the pattern of integration in the substrate. Alternatively, the devices 50 in the substrate 20 may be connected to form a voter circuit that selects between different ones of the dice 30. The substrate may be used to interconnect two dice mounted on opposite sides of the substrate, face-to-face, with their aligned contact pads interconnected by plated-through holes in the substrate. <IMAGE>
Description
SPECIFICATION
Electronic circuit assemblies
This invention relates to electronic circuit assemblies.
The invention is more particularly concerned with circuit assemblies including an integrated semiconductor circuit or die mounted on a substrate by which electrical connection to the die is made.
Conventionally, the substrate may be a multi-layer circuit board having conducting tracks extending over its surface, or within it, which are connected to contact pads on the die or to pins on the package in which the die is mounted. The substrate provides electrical connection with external circuits and may support more than one die, also providing electrical connection between the dice.
Where a large circuit assembly is needed, this requires a correspondingly large number of dice which in turn requires a large number of connections between die and substrate and an increase in the length of the conductive tracks. This increases the risk of failure or malfunction of the assembly and can reduce its operating speed.
It is an object of the present invention to provide an improved electronic circuit assembly.
According to one aspect of the present invention there is provided an electronic circuit assembly comprising at least one integrated circuit die having a plurality of active semiconductor devices and a plurality of contact pads on a surface thereof electric- ally connected with the semiconductor devices, and a substrate member having a plurality of contact pads on a surface thereof, the die and substrate being mounted one above the other with the contact pads on the substrate in contact with the contact pads on the die, the substrate including a plurality of active semiconductor devices integrated within the substrate so that electrical connection of the devices in the die is established with the devices in the substrate.
By mounting the integrated circuit die directly on a substrate having active semiconductor devices within it, in effect, another integrated circuit die, the path length between devices can be reduced. Also, the number of interconnections required can be reduced. An arrangement according to the present
invention can enable a more compact circuit assem buy to be provided.
The substrate may have a greater surface area than the die. The substrate may have conductive elements on that part of its surface which projects beyond the die, external electrical connection being made to those elements. The assembly may include a plurality of dice mounted on the substrate. The semiconductor devices in the integrated circuit die and the semiconductor devices in the substrate may
be connected in respective circuits that are arranged to perform substantially the same functions. The
pattern of integration in the integrated circuit die
may be substantially a mirror image of the pattern of
integrations in the substrate.
The plurality of active semiconductor devices
integrated within the substrate may be connected to form a voter circuit, the voter circuit being connected to select between different ones of the dice. The substrate may be of silicon.
According to another aspect of the present invention there is provided a packaged electronic circuit assembly including an electronic circuit assembly, a package within which the assembly is contained, a plurality of electrically- conductive leads extending through the wall of the package, the leads being electrically connected internally of the package with the contact pads on the substrate. The leads may be connected internally of the package by separate electrically-conductive wires extending between the leads and the contact pads. Alternatively, a part of the substrate may overlie the internal end of the leads, with the contact pads on the substrate in direct electrical connection with the leads.
According to a further aspect of the present invention there is provided an electronic circuit assembly including first and second integrated circuit dice each of which has contact pads on a respective surface, the pattern of integration of one die being substantially a mirror image of the pattern of integration of the other die, and the two dice being mounted one above the other in a face-to-face relationship with the respective contact pads on the two dice aligned with each other.
The assembly may include a substrate between the two dice, electrical interconnection of contact pads on the dice being achieved by electricallyconductive paths through the thickness of the substrate. The electrically-conductive paths may be holes through the thickness of the substrate plated with an electrically-conductive material.
Various packaged assemblies comprising a substrate and dice, according to the present invention, will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a sectional side elevation of an assembly pack;
Figure 2 shows a part of Figure 1 to a larger scale;
Figure 3 shows schematically a part of a circuit arrangement of the substrate;
Figure 4 illustrates schematically the electrical circuit provided by the assembly;
Figure 5shows an alternative assembly according to the second aspect of the present invention; and
Figure 6 is a side elevation of an alternative assembly pack.
With reference to Figures 1 to 3, the electronic circuit assembly 10 is contained within an outer sealed package 11 from which project stiff connecting leads 12 that are used to establish electrical connection to the assembly.
The assembly 10 comprises a rectangular silicon substrate 20 and six integrated circuit dice 30A, 30B, 30C, 30X, 30Y and 30Z connected with the substrate, the surface area of the substrate being greater than that of any one of the dice. The bottom surface 21 of the substrate 20 is secured to the floor of the package 11 such as by means of a heat-conducting adhesive or a gold/silicon eutectic bond. The upper surface 22 bears a pattern of aluminium tracks 23 on which are formed gold contact pads 24 located to underlie corresponding contact pads 34 formed on the underside 35 of the dice 30. Fine wires 31 interconnect the tracks 23 on the surface 22 of the substrate 20 with the connecting leads 12.Electrical connection between the contact pads 24 on the substrate and the pads 34 on the dice is made by bonds 25 using solder ball methods, a conducting epoxy or silver-loaded glass.
The tracks 23 serve both to interconnect different pads 24 on the substrate, so as to establish interconnection between different dice 30, and also to interconnect contact pads on the substrate surface 22 with active semiconductor devices 50 (shown only schematically in the drawings) formed within the body of the substrate 20. In this respect, the substrate 20 itself is, in effect an integrated circuit die containing active semiconductor devices formed by conventional deposition, doping and etching techniques. The devices 50 within the substrate 20 can take many different forms according to the application to which the circuit assembly 10 is to be put.
In the present embodiment, the dice 30 form two sets of identical dice 30A to 30C and 30Xto 30Z, and the devices 50 form three selection logic units 50A, SOB and 50C, each including a voter circuit 51 and an
OR gate 52, as shown in Figures 3 and 4. The voter circuits 51 each have three inputs which are coupled to receive output signals from each of three of the dice 30A, 30B and 30C. The voter circuits 51 each have a single output that is supplied to one input of each of the three OR gates 52. The output of the OR gates 52 is connected to a respective one of the remaining dice 30X, 30Y and 30Z.In operation, the voter circuits 51 reject any one of the inputs that differs from the other two input signals by more than a a predetermined threshold, and supply an output signal based on those two input signals which are approximately equal to one another. In this way, if one of the dice 30A to 30C should malfunction, it will be isolated and signals based on the correctly functioning dice will be supplied to following components.
The invention is not restricted to the provision of voter circuits in the substrate. Any conventional integrated circuit can be formed by the interconnection of active semiconductor devices formed within the substrate. Where the substrate is of substantially the same size as the integrated circuit die mounted on the substrate, this enables the scale of integration to be double that which can be provided by the die alone. To achieve the same scale of integration by conventional means would require the use of two dice, mounted side-by-side on a substrate and interconnected with each other by means of joints made between each die and conductive tracks on the substrate.Such conventional arrangements lead to an increase in the path length between devices in different circuit dice and also increase the number of interconnections required with a consequent increase in capacitance and the risk of malfunction caused by a poor joint.
In a possible alternative embodiment the substrate may have substantially the same circuit within it as the chip mounted on the circuit. In this way, the chip and substrate together can form a duplex assembly with a degree of redundancy so that, on failure of one circuit, the other circuit can carry out the same functions. Because the bonding pads on the opposite faces of the substrate and die must align with each other, it would not, in general, be possible for the pattern of the pads to be identical on the die and substrate. This, however, need not increase significantly the cost of manufacture since the same masks used to form the die could also be used to form the substrate, after having been inverted.Thus, a mirror image circuit pattern will be formed in the substrate which will align with the pattern in the die, when the die and substrate are placed face-to4ace. Preferably, the substrate will-be slightly larger than the die and have contact pads that project beyond the edge of the die so as to enable interconnection of the assembly with external circuits. This will only require minor modifications to be made to one or two of the masks used for manufacture of the substrate.
By making pairs of integrated circuit dice with one of the pair being a mirror image of the other can have advantages in conventional assemblies. For example, as shown in Figure 5, where an assembly has a conventional substrate 200 that serves solely to provide electrical interconnection between two dice 201 and 202 the two dice could be mounted on opposite sides of the substrate, directly above one another in a face-to-face relationship. In such an arrangement, because corresponding contact pads on the two dice are aligned with one another interconnection is facilitated, and interconnect path length is reduced, by using plated-through holes 203 or other conductive paths through the thickness of the substrate.
The present invention enables two or more integrated circuit dice to be used together when they are not specifically designed to be compatible, since the substrate can incorporate active semiconductor devices so arranged as to make the output of one die compatible with the input of the other die or dice.
This enables standard integrated circuits and custom-designed dice to be freely mixed, and modifications to be made without necessarily incurring high retooling costs.
The assembly may be mounted in the package in different ways. For example, as shown in Figure 6, substrate 20' may be inverted, and its dimensions relative to the package 11' selected such that, it overlaps the leads 12' at the edge of package, and the conductive tracks on the substrate surface make direct contact with the leads.
Claims (18)
1. An electronic circuit assembly comprising at least one integrated circuit die having a plurality of active semiconductor devices and a plurality of contact pads on a surface thereof electrically connected with the semiconductor devices, and a substrate member having a plurality of contact pads on a surface thereof, the die and substrate being mounted one above the other with the contact pads on the substrate in contact with the contact pads on the die, wherein the substrate includes a plurality of active semiconductor devices integrated within the substrate and electrically connected with the contact pads on the substrate so that electrical connection of the devices in the die is established with the devices in the substrate.
2. An electronic circuit assembly according to
Claim 1, wherein the substrate has a greater surface area than the die.
3. An electronic circuit assembly according to
Claim 2, wherein the substrate has conductive elements on that part of its surface which projects beyond the die, and wherein external electrical connection is made to those elements.
4. An electronic circuit assembly according to any one of the preceding claims, wherein the assembly includes a plurality of dice mounted on the substrate.
5. An electronic circuit assembly according to any one of the preceding claims, wherein the semiconductor devices in the integrated circuit die and the semiconductor devices in the substrate are connected in respective circuits that are arranged to perform substantially the same functions.
6. An electronic circuit assembly according to
Claim 5, wherein the pattern of integration in the integrated circuit die is substantially a mirror image of the pattern of integration in the substrate.
7. An electronic circuit assembly according to
Claim 4, wherein the plurality of active semiconductor devices integrated within the substrate are connected to form a voter circuit, and wherein the voter circuit is connected to select between different ones of the dice.
8. An electronic circuit assembly according to any one of the preceding claims, wherein the substrate is of silicon.
9. A packaged electronic circuit assembly including an electronic circuit assembly according to any one of the preceding claims, a package within which the assembly is contained, a plurality of electricallyconductive leads extending through the wall of the package, the leads being electrically connected internally of the package with the contact pads on the substrate.
10. A packaged electronic circuit assembly according to Claim 9, wherein the leads are connected internally of the packaged by separate electrically-conductive wires extending between the leads and the contact pads.
11. A packaged electronic circuit assembly according to Claim 9, wherein a part of the substrate overlies the internal end of the lead, with the contact pads on the substrate in direct electrical connection with the leads.
12. An electronic circuit assembly substantially as hereinbefore described with reference to Figures 1 1 to 4 of the accompanying drawings.
13. An electronic circuit assembly substantially as hereinbefore described with reference to Figures 1 to 4 as modified by Figure 6 of the accompanying drawings.
14. An electronic circuit assembly including first and second integrated circuit dice each of which has contact pads on a respective surface, wherein the pattern of integration of one die is substantially a mirror image of the pattern of integration of the other die, and wherein the two dice are mounted one above the other in a face-to-face relationship with the respective contact pads on the two dice aligned with each other.
15. An electronic circuit assembly according to
Claim 14, wherein the assembly includes a substrate between the two dice, and wherein electrical interconnection of contact pads on the dice is achieved by electrically-conductive paths through the thickness of the substrate.
16. An electronic circuit assembly according to
Claim 15, wherein the electrically-conductive path are holes through the thickness of the substrate plated with an electrically-conductive material.
17. An electronic circuit assembly substantially as hereinbefore described with reference to Figure 5 of the accompanying drawings.
18. Any novel feature or combination of features as hereinbefore described.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB858506714A GB8506714D0 (en) | 1985-03-15 | 1985-03-15 | Electronic circuit assemblies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8605664D0 GB8605664D0 (en) | 1986-04-16 |
| GB2172429A true GB2172429A (en) | 1986-09-17 |
Family
ID=10576034
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB858506714A Pending GB8506714D0 (en) | 1985-03-15 | 1985-03-15 | Electronic circuit assemblies |
| GB08605664A Withdrawn GB2172429A (en) | 1985-03-15 | 1986-03-07 | Electronic circuit assembly |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB858506714A Pending GB8506714D0 (en) | 1985-03-15 | 1985-03-15 | Electronic circuit assemblies |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS61214549A (en) |
| DE (1) | DE3607093A1 (en) |
| FR (1) | FR2579022A1 (en) |
| GB (2) | GB8506714D0 (en) |
| IT (1) | IT1188581B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0375869A2 (en) * | 1988-12-27 | 1990-07-04 | Hewlett-Packard Company | Monolithic semiconductor chip interconnection technique and arragement |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335529A (en) * | 1992-05-28 | 1993-12-17 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| DE4225138A1 (en) * | 1992-07-30 | 1994-02-03 | Daimler Benz Ag | Multichip module and method for its production |
| WO1996001497A1 (en) * | 1994-07-05 | 1996-01-18 | Siemens Aktiengesellschaft | Method of manufacturing three-dimensional circuits |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3748548A (en) * | 1964-08-18 | 1973-07-24 | Texas Instruments Inc | Three-dimensional integrated circuits and method of making same |
| GB1425283A (en) * | 1973-06-04 | 1976-02-18 | Ibm | Multifunction wafers |
| EP0032068A1 (en) * | 1979-12-07 | 1981-07-15 | Le Silicium Semiconducteur Ssc | Three terminal diode and mounting of a main semiconductor component and the diode in a single housing |
| GB2117564A (en) * | 1982-03-26 | 1983-10-12 | Int Computers Ltd | Mounting one integrated circuit upon another |
-
1985
- 1985-03-15 GB GB858506714A patent/GB8506714D0/en active Pending
-
1986
- 1986-03-05 DE DE19863607093 patent/DE3607093A1/en not_active Withdrawn
- 1986-03-07 GB GB08605664A patent/GB2172429A/en not_active Withdrawn
- 1986-03-07 IT IT19667/86A patent/IT1188581B/en active
- 1986-03-11 FR FR8603549A patent/FR2579022A1/en not_active Withdrawn
- 1986-03-15 JP JP61056113A patent/JPS61214549A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3748548A (en) * | 1964-08-18 | 1973-07-24 | Texas Instruments Inc | Three-dimensional integrated circuits and method of making same |
| GB1425283A (en) * | 1973-06-04 | 1976-02-18 | Ibm | Multifunction wafers |
| EP0032068A1 (en) * | 1979-12-07 | 1981-07-15 | Le Silicium Semiconducteur Ssc | Three terminal diode and mounting of a main semiconductor component and the diode in a single housing |
| GB2117564A (en) * | 1982-03-26 | 1983-10-12 | Int Computers Ltd | Mounting one integrated circuit upon another |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0375869A2 (en) * | 1988-12-27 | 1990-07-04 | Hewlett-Packard Company | Monolithic semiconductor chip interconnection technique and arragement |
| EP0375869A3 (en) * | 1988-12-27 | 1991-04-17 | Hewlett-Packard Company | Monolithic semiconductor chip interconnection technique and arragement |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8506714D0 (en) | 1985-04-17 |
| GB8605664D0 (en) | 1986-04-16 |
| JPS61214549A (en) | 1986-09-24 |
| IT8619667A0 (en) | 1986-03-07 |
| FR2579022A1 (en) | 1986-09-19 |
| IT1188581B (en) | 1988-01-20 |
| DE3607093A1 (en) | 1986-09-18 |
| IT8619667A1 (en) | 1987-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |