AU6317100A - Semiconductor package unit - Google Patents

Semiconductor package unit

Info

Publication number
AU6317100A
AU6317100A AU63171/00A AU6317100A AU6317100A AU 6317100 A AU6317100 A AU 6317100A AU 63171/00 A AU63171/00 A AU 63171/00A AU 6317100 A AU6317100 A AU 6317100A AU 6317100 A AU6317100 A AU 6317100A
Authority
AU
Australia
Prior art keywords
semiconductor package
package unit
unit
semiconductor
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU63171/00A
Inventor
Shinji Ohsawa
Hiroaki Okamoto
Kinji Saijo
Kazuo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Kohan Co Ltd
Original Assignee
Toyo Kohan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co Ltd filed Critical Toyo Kohan Co Ltd
Publication of AU6317100A publication Critical patent/AU6317100A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)
AU63171/00A 1999-08-02 2000-08-02 Semiconductor package unit Abandoned AU6317100A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11/218929 1999-08-02
JP21892999 1999-08-02
PCT/JP2000/005181 WO2001009950A1 (en) 1999-08-02 2000-08-02 Semiconductor package unit

Publications (1)

Publication Number Publication Date
AU6317100A true AU6317100A (en) 2001-02-19

Family

ID=16727543

Family Applications (1)

Application Number Title Priority Date Filing Date
AU63171/00A Abandoned AU6317100A (en) 1999-08-02 2000-08-02 Semiconductor package unit

Country Status (4)

Country Link
JP (1) JP5105625B2 (en)
AU (1) AU6317100A (en)
TW (1) TW522530B (en)
WO (1) WO2001009950A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5067107B2 (en) * 2007-10-12 2012-11-07 富士通株式会社 Circuit board and semiconductor device
US20220223531A1 (en) * 2019-05-31 2022-07-14 Ultramemory Inc. Semiconductor module and manufacturing method therefor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03188660A (en) * 1989-12-19 1991-08-16 Toppan Printing Co Ltd Lead frame material for semiconductor device and manufacture of lead frame for semiconductor device
JPH05190764A (en) * 1992-01-17 1993-07-30 Hitachi Ltd Semiconductor device
JPH08241945A (en) * 1995-03-03 1996-09-17 Sony Corp Lead frame, semiconductor device and manufacture of semiconductor device
JP3988227B2 (en) * 1997-12-01 2007-10-10 日立化成工業株式会社 Manufacturing method of semiconductor chip mounting substrate and semiconductor device
JP3497774B2 (en) * 1999-08-13 2004-02-16 株式会社ノース Wiring board and its manufacturing method
JP3798597B2 (en) * 1999-11-30 2006-07-19 富士通株式会社 Semiconductor device

Also Published As

Publication number Publication date
WO2001009950A1 (en) 2001-02-08
JP5105625B2 (en) 2012-12-26
JP2010004064A (en) 2010-01-07
TW522530B (en) 2003-03-01

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase