AU7748800A - Semiconductor packaging - Google Patents

Semiconductor packaging

Info

Publication number
AU7748800A
AU7748800A AU77488/00A AU7748800A AU7748800A AU 7748800 A AU7748800 A AU 7748800A AU 77488/00 A AU77488/00 A AU 77488/00A AU 7748800 A AU7748800 A AU 7748800A AU 7748800 A AU7748800 A AU 7748800A
Authority
AU
Australia
Prior art keywords
semiconductor packaging
packaging
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU77488/00A
Inventor
Behnam Tabrizi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Skyworks Solutions Inc
Original Assignee
Alpha Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha Industries Inc filed Critical Alpha Industries Inc
Publication of AU7748800A publication Critical patent/AU7748800A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
AU77488/00A 1999-09-30 2000-10-02 Semiconductor packaging Abandoned AU7748800A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15673999P 1999-09-30 1999-09-30
US60156739 1999-09-30
PCT/US2000/027206 WO2001024259A2 (en) 1999-09-30 2000-10-02 Semiconductor packaging

Publications (1)

Publication Number Publication Date
AU7748800A true AU7748800A (en) 2001-04-30

Family

ID=22560878

Family Applications (1)

Application Number Title Priority Date Filing Date
AU77488/00A Abandoned AU7748800A (en) 1999-09-30 2000-10-02 Semiconductor packaging

Country Status (3)

Country Link
EP (1) EP1243025A2 (en)
AU (1) AU7748800A (en)
WO (1) WO2001024259A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10047213A1 (en) * 2000-09-23 2002-04-11 Philips Corp Intellectual Pty Electric or electronic component e.g. for microelectronics, has electrically-conducting connection element between contact surface of component and section of contact path
US6686642B2 (en) * 2001-06-11 2004-02-03 Hewlett-Packard Development Company, L.P. Multi-level integrated circuit for wide-gap substrate bonding
PT3659437T (en) 2004-01-23 2022-06-20 Eden Research Plc Methods of killing nematodes comprising the application of an encapsulated terpene component
DE102005007423B3 (en) 2005-02-18 2006-06-14 Atmel Germany Gmbh Integration of electronic component (8) into substrate by formation of dielectric insulating layers on substrate front side useful in structural element modelling in semiconductor flip-chip technology with photoresistive layer in cavity
DE102010042567B3 (en) 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method for manufacturing a chip package and chip package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
JPS5944849A (en) * 1982-09-08 1984-03-13 Hitachi Ltd Semiconductor device and manufacture thereof
JPS61214444A (en) * 1985-03-18 1986-09-24 Fujitsu Ltd Semiconductor device
JPH0834264B2 (en) * 1987-04-21 1996-03-29 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
KR910006706B1 (en) * 1988-12-12 1991-08-31 삼성전자 주식회사 Manufacturing method of light emitted diode array head
US5198963A (en) * 1991-11-21 1993-03-30 Motorola, Inc. Multiple integrated circuit module which simplifies handling and testing
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
DE19720300B4 (en) * 1996-06-03 2006-05-04 CiS Institut für Mikrosensorik gGmbH Hybrid electronic component and method for its production

Also Published As

Publication number Publication date
WO2001024259A3 (en) 2001-11-29
WO2001024259A2 (en) 2001-04-05
EP1243025A2 (en) 2002-09-25

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Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase