JP2665293B2 - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JP2665293B2
JP2665293B2 JP4068405A JP6840592A JP2665293B2 JP 2665293 B2 JP2665293 B2 JP 2665293B2 JP 4068405 A JP4068405 A JP 4068405A JP 6840592 A JP6840592 A JP 6840592A JP 2665293 B2 JP2665293 B2 JP 2665293B2
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
solder
component mounting
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4068405A
Other languages
Japanese (ja)
Other versions
JPH05275836A (en
Inventor
出 吉澤
昇 山口
浩昌 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4068405A priority Critical patent/JP2665293B2/en
Publication of JPH05275836A publication Critical patent/JPH05275836A/en
Application granted granted Critical
Publication of JP2665293B2 publication Critical patent/JP2665293B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、電子材料分野等で使
用される配線回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board used in the field of electronic materials and the like.

【0002】[0002]

【従来の技術】従来、はんだリフロー工程に供する配線
回路基板には、部品実装に必要な部分のみにはんだコー
ティングするため、図5に示すように、基板1表面に形
成された金属層2のうち、部品実装部3となる箇所以外
の箇所(配線回路部)を、はんだレジスト4で被覆する
ことが行われていた。
2. Description of the Related Art Conventionally, in a printed circuit board subjected to a solder reflow process, only a portion necessary for component mounting is coated with a solder, as shown in FIG. In addition, a portion (wiring circuit portion) other than the portion serving as the component mounting portion 3 is covered with the solder resist 4.

【0003】[0003]

【発明が解決しようとする課題】しかし、近年、高密度
実装が要求され部品実装部の面積が微小化するにしたが
い、リフロー工程中に溶融はんだと金属部分とが接触し
ているにもかかわらず、所定の箇所にはんだが付かない
という問題が発生し、その改善が望まれていた。この発
明の課題は、上述のような問題を解決するためになされ
たものであり、たとえ高密度実装化によって金属部分の
面積が微小化しても、リフロー工程時に所定のはんだが
コーティングができる配線回路基板を提供することにあ
る。
However, in recent years, as high-density mounting has been demanded and the area of the component mounting portion has become smaller, the molten solder has come into contact with the metal portion during the reflow process. In addition, a problem that solder does not adhere to a predetermined portion has occurred, and improvement thereof has been desired. An object of the present invention is to solve the above-described problems, and a wiring circuit capable of coating a predetermined solder during a reflow process even if the area of a metal portion is reduced by high-density mounting. It is to provide a substrate.

【0004】[0004]

【課題を解決するための手段】発明者らの検討したとこ
ろによれば、前述のように、リフロー工程中に溶融はん
だが金属層に接触しているにもかかわらず、所定の箇所
にはんだが付かないという問題が発生するのは、高密度
化に伴い部品実装部の金属層表面の面積とそれを取り囲
むレジスト層の高さとの比率が小さくなり、それにつれ
て、単に、レジスト層によって、金属層部分へのはんだ
の回り込みが阻害されるという理由だけでなく、はんだ
と金属層部分との濡れ性と、レジスト層がはんだをはじ
く力と、はんだの表面張力等とのバランスが崩れるため
である。このような問題は、部品実装部となる金属層の
表面とレジスト層の表面との段差が解消されるか小さく
なれば改善されるが、前記金属層の表面がレジスト層の
表面よりも高い位置に配置されていれば、確実に解決さ
れる。
According to the study by the inventors, as described above, although the molten solder is in contact with the metal layer during the reflow process, the solder is formed at a predetermined location. The problem of non-sticking occurs because the ratio of the area of the metal layer surface of the component mounting part to the height of the resist layer surrounding it decreases with the increase in density. This is because the balance between the wettability of the solder and the metal layer portion, the force with which the resist layer repels the solder, the surface tension of the solder, and the like is lost, in addition to the reason that the wraparound of the solder to the portion is hindered. Such a problem is ameliorated if the step between the surface of the metal layer serving as the component mounting portion and the surface of the resist layer is eliminated or reduced , but the surface of the metal layer is formed of the resist layer.
If it is arranged at a position higher than the surface, it is surely solved.

【0005】そこで、この発明にかかる配線回路基板
は、部品実装部となる金属層以外の部分がはんだレジス
トによって被覆された配線回路基板であって、前記はん
だレジスト層の表面が、前記部品実装部となる金属層の
表面よりも低い位置に配置されていることを特徴とす
る。この発明にかかる配線回路基板は、前記部品実装部
となる金属層の表面がそれ以外のはんだレジストによっ
て被覆された部分の金属層の表面よりも高くなっている
ことができる。
Therefore, a printed circuit board according to the present invention is a printed circuit board in which a portion other than a metal layer serving as a component mounting portion is covered with a solder resist, and the surface of the solder resist layer is formed on the component mounting portion. characterized that you have been placed at a position lower than the surface of the metal layer becomes. The printed circuit board according to the present invention, the surface of the pre-SL component mounting portion and comprising a metal layer by the other solder resist
Ru can be higher than the surface of the metal layer of the coated portion Te.

【0006】以下に、この発明にかかる配線回路基板に
ついて、具体的に説明する。図1は、この発明にかかる
配線回路基板の一例を示したものである。図から分かる
ように、この配線回路基板では、図5に示した従来のも
のとは異なり、基板1の表面に形成された金属層2は、
部品実装部3となる箇所の表面がそれ以外の箇所(配線
回路部)の表面よりも高くなっており、そのため、はん
だレジスト4の表面が部品実装部3となる金属層の表面
よりも下に位置している。
Hereinafter, the printed circuit board according to the present invention will be specifically described. FIG. 1 shows an example of a printed circuit board according to the present invention. As can be seen from the drawing, in this wired circuit board, unlike the conventional one shown in FIG. 5, the metal layer 2 formed on the surface of the substrate 1 is
The surface of the part to be the component mounting part 3 is higher than the surface of the other part (wiring circuit part). Therefore, the surface of the solder resist 4 is lower than the surface of the metal layer to be the component mounting part 3. positioned.

【0007】この発明にかかる配線回路基板では、部品
実装部3となる箇所の表面がそれ以外の箇所(配線回路
部)の表面よりも高くなっておりさえすれば、図1のよ
うなものである必要は必ずしもない。このような配線回
路基板は、例えば、次に示すような2つの方法で作製す
ることができる。
In the printed circuit board according to the present invention, as long as the surface of the part to be the component mounting part 3 is higher than the surface of the other part (wiring circuit part), the circuit shown in FIG. there need not necessarily stomach. Such a printed circuit board can be manufactured, for example, by the following two methods.

【0008】先ず、第1の方法について、図2に示すフ
ロー工程に従って説明する。全面に所定の厚みの金属層
が形成された基板を用意し、ポジ型のレジストを施す。
ここで、ポジ型のレジストは、後のめっき工程に対して
支障をきたさないものであれば特に指定はなく、ドライ
フィルムタイプのものであっても、EDタイプのもので
あっても、あるいは液状タイプのものであっても、差し
支えなく、状況に応じて使い分けることができる。
First, the first method will be described with reference to the flow steps shown in FIG. A substrate on which a metal layer having a predetermined thickness is formed over the entire surface is prepared, and a positive resist is applied.
Here, the positive resist is not particularly specified as long as it does not hinder the subsequent plating step, and may be a dry film type, an ED type, or a liquid. Even if it is a type, it can be used properly according to the situation.

【0009】そして、フォトリソグラフ法によって、後
のリフロー工程時にはんだコーティングを要する部分
(部品実装部となる金属層の部分)のみを露光現像す
る。次に、レジストが除去されて露出した金属層部分
(部品実装部)にめっきを行い、所定の厚みとなるよう
に金属層の厚付けを実施する。すなわち、本ポジ型レジ
ストはめっきレジストとして使用するわけである。
Then, by photolithography, only a portion requiring solder coating (a portion of a metal layer to be a component mounting portion) in a later reflow step is exposed and developed. Next, plating is performed on the metal layer portion (component mounting portion) exposed by removing the resist, and the metal layer is thickened to have a predetermined thickness. That is, the positive resist is used as a plating resist.

【0010】なお、このめっき工程では、前工程で形成
したポジ型レジストを、次工程でさらに露光現像するた
め、紫外線を当てないように例えばイエロールーム等で
作業する必要がある。本めっき工程では、めっきする金
属について特に指定はなく、さらに、電解めっき、無電
解めっきのいずれの方法によってもさしつかえない。次
に、露出した金属層表面、または、基板表面全面にポジ
型レジストを形成する。このレジスト形成は、例えば、
液状レジストを塗布することなどで対応できる。
In this plating step, the positive resist formed in the previous step is further exposed and developed in the next step, so that it is necessary to work in a yellow room or the like so as not to be irradiated with ultraviolet rays. In the present plating step, there is no particular designation for the metal to be plated, and furthermore, any one of electrolytic plating and electroless plating may be used. Next, a positive resist is formed on the exposed metal layer surface or the entire substrate surface. This resist formation, for example,
This can be dealt with by applying a liquid resist.

【0011】次に、このポジ型レジストの回路となる部
分以外の箇所の露光現像を行い、露出した金属層のエッ
チング処理を行い、さらに残ったポジ型レジストの剥離
を行う。最後に、上記工程によって形成された部品実装
部となる金属層以外の部分を、その表面が前記金属層の
表面よりも低い位置になるように、はんだレジストで被
覆すると、図1に示すような配線回路基板が得られる。
Next, exposure and development are performed on portions other than the circuit portion of the positive resist, the exposed metal layer is etched, and the remaining positive resist is removed. Finally, the portion other than the metal layer serving as a component mounting portion formed by the above process, so that the such a position lower than the surface of the surface of the metal layer, when coated with solder resist, as shown in FIG. 1 A simple printed circuit board can be obtained.

【0012】次に、図3に示すフロー工程図に従って、
第2の方法について説明する。先ず、フルアディティブ
法によって所定のパターニングおよびメタライズを終え
た図4に示すような配線回路基板を準備する。図におい
て、1は基板、2は金属層、4はレジストである。つぎ
に、その部品実装部3となる箇所以外の箇所の金属層2
をレジスト4で覆い、図5のような配線回路基板を得
る。そして、この配線回路基板の部品実装部3に、無電
解めっき法等によって、金属層の積み上げ形成(厚付
け)をすることにより、その部分の金属層表面がはんだ
レジスト層表面以上の高さとなるようにすると、図1に
示すような配線回路基板が得られる。
Next, according to the flow process diagram shown in FIG.
The second method will be described. First, a printed circuit board as shown in FIG. 4 which has been subjected to predetermined patterning and metallization by a full additive method is prepared. In the figure, 1 is a substrate, 2 is a metal layer, and 4 is a resist. Next, the metal layer 2 at a location other than the location where the component mounting portion 3 is to be formed.
Is covered with a resist 4 to obtain a printed circuit board as shown in FIG. Then, by forming (thickening) a metal layer on the component mounting portion 3 of the printed circuit board by electroless plating or the like, the surface of the metal layer at that portion becomes higher than the surface of the solder resist layer. By doing so, a printed circuit board as shown in FIG. 1 is obtained.

【0013】なお、金属の厚付けを要する箇所すべてが
電気的に導通している場合は、この厚付けは、電気めっ
き法によって行うこともできる。ここで、フルアディテ
ィブ法で得た、図4に示すような従来の配線回路基板で
も、金属部へのリフロー時におけるはんだ濡れ性に関し
ていえば、全く問題はないが、以下の点で欠点を有す
る。すなわち、従来のフルアディティブ法では、部品実
装部となる箇所以外の配線回路部にもリフロー時にはん
だコーティングがなされてしまうため、例えば、他の配
線回路基板と張り合わせて、多層配線回路基板を作製し
ようとする場合には、はんだの溶融によって配線間が短
絡してしまったり、あるいは張り合わす相手の配線回路
基板とのコンタクト箇所以外の部分とコンタクトしてし
まうなどの不都合を生じる。
In the case where all portions requiring thickening of the metal are electrically conductive, the thickening can be performed by an electroplating method. Here, even with the conventional printed circuit board as shown in FIG. 4 obtained by the full additive method, there is no problem with respect to the solder wettability at the time of reflow to the metal part, but it has the following disadvantages. . That is, in the conventional full-additive method, since the wiring coating is also applied to the wiring circuit portion other than the portion where the component is to be mounted at the time of reflow, for example, a multi-layer wiring circuit board is to be manufactured by bonding to another wiring circuit board. In such a case, inconveniences such as short-circuiting between the wirings due to the melting of the solder, or contact with a portion other than the contact portion with the wiring circuit board to be bonded are caused.

【0014】[0014]

【作用】この発明にかかる配線回路基板では、部品実装
部となる金属層の表面が、はんだレジスト層の表面より
も高い位置に配置されているため、はんだリフロー時に
おける溶融はんだの濡れ性が改善される。
In the printed circuit board according to the present invention, the surface of the metal layer serving as the component mounting portion is higher than the surface of the solder resist layer.
Is also located at a higher position, so that the wettability of the molten solder during solder reflow is improved.

【0015】[0015]

【実施例】以下に、この発明にかかる配線回路基板の一
実施例を挙げ、さらに詳述する。 −実施例1− 全面に所定の厚みの銅層が形成されたセラミック基板を
用意し、図2に示したフロー工程に従って配線回路基板
を作製した。
An embodiment of the printed circuit board according to the present invention will be described below in more detail. Example 1 A ceramic substrate having a copper layer of a predetermined thickness formed on the entire surface was prepared, and a printed circuit board was manufactured according to the flow process shown in FIG.

【0016】先ず、上記セラミック基板にポジ型の液状
レジストをディップ法によって塗布し、フォトリソグラ
フ法を用いて部品実装部となる部分のみ露光現像を行っ
た。なお、本実施例ではリフロー時のはんだ濡れ性を評
価するために、部品実装部が0.2〜2mmφとなるよ
うなテストパターンを準備した。前工程で露出した銅
に、イエロールーム内で硫酸銅電気めっきを行い、20
μmの銅の厚付けを行った。
First, a positive type liquid resist was applied to the ceramic substrate by a dipping method, and exposure and development were performed only on a part to be a component mounting portion by using a photolithographic method. In addition, in this example, in order to evaluate the solder wettability at the time of reflow, a test pattern was prepared such that the component mounting portion had a diameter of 0.2 to 2 mmφ. The copper exposed in the previous process is subjected to copper sulfate electroplating in a yellow room,
A μm thick copper was applied.

【0017】次に、前工程で用いたものと同じポジ型の
液状レジストを全面に3μm程度塗布し、続いて、回路
となる部分の露光現像を行った。次に、前工程で露出し
た銅層を塩化銅エッチング液を用いて除去し、続いて残
ったレジストを炭酸ナトリウムの溶液で剥離した。そし
て、最後にペースト状のはんだレジストで、部品実装部
となる金属部以外の領域を被覆し、図1に示す配線回路
基板を得た。
Next, the same positive type liquid resist as that used in the previous step was coated on the entire surface to a thickness of about 3 μm, and subsequently, a portion to be a circuit was exposed and developed. Next, the copper layer exposed in the previous step was removed using a copper chloride etching solution, and the remaining resist was subsequently peeled off with a solution of sodium carbonate. Then, finally, a region other than the metal portion serving as the component mounting portion was covered with a paste-like solder resist to obtain the printed circuit board shown in FIG.

【0018】られた配線回路基板を予熱炉で予熱した
後、250°Cにセットされたはんだリフロー槽に通し
て、はんだコーティングを実施したところ、部品実装部
として用意した0.2〜2mmφのラウンド部すべてに
均一なはんだコーティングが実施できた。
After the obtained printed circuit board was preheated in a preheating furnace, it was passed through a solder reflow bath set at 250 ° C. and solder coating was performed. Uniform solder coating was performed on all round parts.

【0019】−実施例2− 従来のフルアディティブ法によって図4に示すような構
造を有するガラスエポキシの銅配線回路基板を用意し、
図3に示したフロー工程図に従って、図1の配線回路基
板を作製した。すなわち、具体的には、本実施例でも、
実施例1と同様にリフロー時のはんだ濡れ性を評価する
ために、部品実装部が0.2〜2mmφとなるようなテ
ストパターンを準備した。先ず、上記ガラスエポキシの
銅配線回路基板にめっきレジスト兼フォトソルダーレジ
ストをスクリーン印刷法により20μm塗布し、露光現
像により部品実装部となる以外の部分を被覆した。
Example 2 A glass epoxy copper wiring circuit board having a structure as shown in FIG. 4 is prepared by a conventional full additive method.
The printed circuit board of FIG. 1 was manufactured according to the flow process diagram shown in FIG. That is, specifically, in this embodiment,
In order to evaluate the solder wettability at the time of reflow in the same manner as in Example 1, a test pattern having a component mounting portion having a diameter of 0.2 to 2 mmφ was prepared. First, a plating resist and a photo solder resist were applied to the above-mentioned glass epoxy copper wiring circuit board by a screen printing method to a thickness of 20 μm, and portions other than the component mounting portion were covered by exposure and development.

【0020】次いで、厚付けタイプの無電解銅めっき液
を用いて、露出している銅層のみ厚付けし、図1に示
すとおり部品実装部となる銅層表面はんだレジスト表
よりも高くなるようにして、図1に示す構造の配線回
路基板を得たのである。得られた配線回路基板を予熱炉
で予熱した後、230°Cにセットされたはんだリフロ
ー槽に通して、はんだコーティングを実施したところ、
部品実装部として用意した0.2〜2mmφのラウンド
部すべてに均一なはんだコーティングが実施できた。
Next, using an electroless copper plating solution of a thick type, only the exposed copper layer is thickened, and the thickness is shown in FIG.
As described above, the printed circuit board having the structure shown in FIG. 1 was obtained in such a manner that the surface of the copper layer serving as the component mounting portion was higher than the surface of the solder resist. After pre-heating the obtained wiring circuit board in a pre-heating furnace, it was passed through a solder reflow tank set at 230 ° C. to perform solder coating.
Uniform solder coating was able to be performed on all the round portions of 0.2 to 2 mmφ prepared as the component mounting portions.

【0021】−実施例3− 実施例1と同じ方法で作製した厚さ0.3mmの2種類
のセラミック配線回路基板を、それぞれの配線回路基板
のコンタクト部となる銅層表面にリフロー工程によって
はんだコーティングした後、はんだ溶融温度の下でそれ
ぞれの基板を張り合わせ、多層構造の配線回路基板とし
た。
Example 3 Two types of ceramic printed circuit boards having a thickness of 0.3 mm produced in the same manner as in Example 1 were soldered to the surface of a copper layer serving as a contact portion of each printed circuit board by a reflow process. After coating, the respective substrates were bonded together at a solder melting temperature to obtain a multilayered printed circuit board.

【0022】張り合わせた多層構造の配線回路基板に対
して電気導通試験を実施したところ、全コンタクト部が
良好な接続をなされていることが確認された。 −比較例1− 実施例1と同じパターンを有し、図5に示す従来法で作
製されたセラミック配線回路基板に対し、実施例1と同
じ条件でリフロー工程におけるはんだ濡れ性の評価を実
施した。なお、本比較例で用いた配線回路基板における
部品実装部の銅層表面とはんだレジストの表面との高低
差(段差)は20μmであった。
When an electrical continuity test was conducted on the printed circuit board having the laminated multilayer structure, it was confirmed that all the contact portions were connected well. -Comparative Example 1- An evaluation of the solder wettability in the reflow process was performed on the ceramic printed circuit board having the same pattern as in Example 1 and manufactured by the conventional method shown in FIG. 5 under the same conditions as in Example 1. . The height difference (step) between the surface of the copper layer of the component mounting portion and the surface of the solder resist in the printed circuit board used in this comparative example was 20 μm.

【0023】はんだ濡れ性評価の結果、0.2mmφの
ラウンド部には全くはんだコーティングが行えず、ま
た、0.5mmφのラウンド部でも一部はんだコーティ
ングが行えない箇所が見られた。 −比較例2− 図5に示すような従来法によって作製した以外は実施例
3と同様の条件で2種類のセラミック配線回路基板を張
り合わせて多層構造の配線回路基板を得た。この多層構
造配線回路基板に対して、実施例3と同様の電気導通試
験を実施したところ、一部、はんだコーティング量の不
足が原因と思われる導通不良が観察された。
As a result of the evaluation of the solder wettability, it was found that no solder coating could be performed at all on the round portion of 0.2 mmφ, and some portions could not be coated on the round portion of 0.5 mmφ. Comparative Example 2 Two types of ceramic printed circuit boards were bonded together under the same conditions as in Example 3 except that they were manufactured by the conventional method as shown in FIG. 5 to obtain a printed circuit board having a multilayer structure. When an electrical continuity test similar to that of Example 3 was performed on this multilayered wiring circuit board, a conduction failure that was partially due to an insufficient amount of solder coating was observed.

【0024】[0024]

【発明の効果】この発明にかかる配線回路基板では、部
品実装部となる金属層の表面がはんだレジスト層表面よ
りも高く位置するので、従来法のようにリフロー工程時
に溶融はんだと金属部分との接触が阻害されることがな
く、所定量のはんだがコーティングできる。そのため、
従来のように、リフロー工程後、部品実装部となる金属
表面のはんだ量が不均一となったり、あるいは部分的に
はんだコーティングがなされない等の不良を起こすこと
がなく、均一なはんだコーティングを実施することがで
きるのである。
In the printed circuit board according to the present invention, the surface of the metal layer serving as the component mounting portion is located higher than the surface of the solder resist layer. A predetermined amount of solder can be coated without hindering contact. for that reason,
Performs uniform solder coating after the reflow process, without causing defects such as uneven solder amount on the metal surface that will be the component mounting part or partial lack of solder coating. You can do it.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明にかかる配線回路基板の構造の一例
を示す断面図
FIG. 1 is a sectional view showing an example of the structure of a printed circuit board according to the present invention.

【図2】 この発明にかかる配線回路基板の作製方法の
一例を示すフロー工程図
FIG. 2 is a flowchart showing an example of a method for manufacturing a printed circuit board according to the present invention.

【図3】 この発明にかかる配線回路基板の作製方法の
別の例を示すフロー工程図
FIG. 3 is a flowchart showing another example of the method of manufacturing a printed circuit board according to the present invention.

【図4】 フルアディティブ法によって作製された配線
回路基板の一例を示す断面図
FIG. 4 is a cross-sectional view illustrating an example of a printed circuit board manufactured by a full additive method.

【図5】 従来の配線回路基板の構造の一例を示す断面
FIG. 5 is a cross-sectional view showing an example of the structure of a conventional printed circuit board.

【符号の説明】[Explanation of symbols]

1 基板 2 金属層 3 部品実装部 4 はんだレジスト層 DESCRIPTION OF SYMBOLS 1 Substrate 2 Metal layer 3 Component mounting part 4 Solder resist layer

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 部品実装部となる金属層以外の部分がは
んだレジストによって被覆された配線回路基板であっ
て、前記はんだレジスト層の表面が、前記部品実装部と
なる金属層の表面よりも低い位置に配置されていること
を特徴とする配線回路基板。
1. A printed circuit board in which a portion other than a metal layer serving as a component mounting portion is covered with a solder resist, wherein a surface of the solder resist layer is lower than a surface of the metal layer serving as the component mounting portion. printed circuit board, characterized that you have been placed in the position.
【請求項2】記部品実装部となる金属層の表面が、
それ以外のはんだレジストによって被覆された部分の
属層の表面よりも高くなっている請求項1に記載の配線
回路基板。
Wherein the surface of the pre-SL component mounting portion and comprising a metal layer,
The printed circuit board according to claim 1, wherein the wiring circuit board is higher than the surface of the metal layer in a portion covered with the other solder resist .
JP4068405A 1992-03-26 1992-03-26 Printed circuit board Expired - Fee Related JP2665293B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4068405A JP2665293B2 (en) 1992-03-26 1992-03-26 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4068405A JP2665293B2 (en) 1992-03-26 1992-03-26 Printed circuit board

Publications (2)

Publication Number Publication Date
JPH05275836A JPH05275836A (en) 1993-10-22
JP2665293B2 true JP2665293B2 (en) 1997-10-22

Family

ID=13372746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4068405A Expired - Fee Related JP2665293B2 (en) 1992-03-26 1992-03-26 Printed circuit board

Country Status (1)

Country Link
JP (1) JP2665293B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018088191A1 (en) * 2016-11-11 2018-05-17 株式会社村田製作所 Ceramic substrate and method for manufacturing ceramic substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472590A (en) * 1987-09-14 1989-03-17 Furukawa Electric Co Ltd Method of mounting component of aluminum conductor circuit substrate

Also Published As

Publication number Publication date
JPH05275836A (en) 1993-10-22

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