JP4043146B2 - Package substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a package substrate on which an electronic component such as an IC chip is placed, and more particularly to a package substrate in which an interlayer resin insulation layer and a wiring layer are built up on a ceramic plate.
[0002]
[Prior art]
As a package substrate, a multilayer wiring board formed by building up an interlayer resin insulation layer and a wiring layer on a ceramic board is known. In such a multilayer wiring board, as shown in FIG. 8, interlayer resin insulation layers 240 and 340 are arranged on a ceramic board 210 having a through hole 212. Vias 246 and conductor circuits 248 are formed in the interlayer resin insulation layer 240, and vias 346 are formed in the interlayer resin insulation layer 340. In the multilayer wiring board, a daughter board 280 is connected to the ceramic board 210 side via bumps 266, and an IC chip 270 is connected to the interlayer resin insulating layer 340 side via bumps 266.
[0003]
[Problems to be solved by the invention]
The package substrate is disposed to connect the IC chip and the external substrate and absorb the difference in thermal expansion between them. However, in the package substrate having the above-described configuration, cracks are generated in the vias 248 and 348, the conductor circuit 248, the interlayer resin insulating layers 240 and 340, and the like due to the difference in thermal expansion between the IC chip 270 and the daughter board. May occur.
[0004]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a package substrate in which no failure occurs due to a difference in thermal expansion between the IC chip and the external substrate.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problems, in the package substrate of claim 1, an interlayer resin insulation layer and a wiring layer are built up on a ceramic plate in which through holes formed by filling copper plating are formed in the formed through holes. A package substrate comprising:
Bumps for connection to the IC chip are disposed on the ceramic plate,
A technical feature is that bumps or pins for connection to an external resin substrate are disposed on the wiring layer on the interlayer resin insulation layer.
[0007]
As a result of research by the present inventor, the above-described crack due to the difference in thermal expansion between the IC chip and the external substrate is formed by attaching an IC chip made of silicon and having a small coefficient of thermal expansion on an interlayer resin insulating layer having a large coefficient of thermal expansion. It was discovered that this is due to the fact that an external substrate with a high coefficient of thermal expansion is attached to the ceramic plate with a low coefficient of thermal expansion.
[0008]
Therefore, in claim 1, an IC chip having a low coefficient of thermal expansion is attached to the ceramic plate side having a small coefficient of thermal expansion, and an external resin substrate made of resin and having a large coefficient of thermal expansion is used as an interlayer resin insulation layer having a large coefficient of thermal expansion. Installed on top to prevent the occurrence of cracks due to differences in thermal expansion coefficient. Further, since the fine pitch IC chip pads are mounted on the flat ceramic plate, the connection reliability can be improved. Furthermore, since the ceramic plate side having high thermal conductivity and heat resistance is attached to the IC chip, the IC chip can be efficiently cooled and the reliability during high heat can be improved.
[0009]
According to the first aspect of the present invention , the through-hole formed in the ceramic plate is filled with copper plating to form a through hole, so that the wiring resistance can be reduced as compared with a through-hole formed by firing metallized ink.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the package substrate according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5 showing cross-sectional views.
As shown in FIG. 4, the package substrate 100 includes a ceramic plate 10 and interlayer resin insulating layers 40 and 140 constituting a buildup layer. Through holes 12 are formed in the ceramic plate 10, and bumps 66 for connection to the pads 72 of the IC chip 70 are formed in the through holes 12 as shown in FIG. On the other hand, a via hole 46 and a conductor circuit 48 are formed in the interlayer resin insulation layer 40, and a via hole 146 connected to the conductor circuit 48 is formed in the interlayer resin insulation layer 140. In the via hole 146, bumps 66 for connection to the pads 82 of the daughter board 80 are disposed as shown in FIG.
[0011]
The pad 82 of the daughter board 80 shown in FIG. 5 is connected to the pad 72 of the IC chip 70 through the bump 66 -via hole 146 -conductor circuit 48 -via hole 46 -wiring 22 -wiring 16 -through hole 12 -bump 66. Has been.
[0012]
In the package substrate 100 of the present embodiment, an IC chip 70 made of silicon and having a low coefficient of thermal expansion is attached to the ceramic plate 10 side having a low coefficient of thermal expansion, and a daughter board 80 made of resin and having a high coefficient of thermal expansion is used. Attached to the large interlayer resin insulation layers 40 and 140 side. For this reason, generation | occurrence | production of the crack etc. resulting from a thermal expansion difference can be prevented.
[0013]
Further, since the fine pitch IC chip pads 72 are mounted on the flat ceramic plate, the connection reliability can be improved. That is, the pads 72 on the IC chip 70 side have a pitch of several tens of μm, whereas the pads 82 on the daughter board 80 side have a pitch of several hundreds of μm. In the package substrate of the prior art described above with reference to FIG. 8, the fine pitch IC chip side pads are attached to the uneven interlayer resin insulating layer 340 side, whereas in the present embodiment, there is no unevenness. Since the bumps 66 on the ceramic plate 10 side are attached to the IC chip 70, the reliability can be improved.
[0014]
Further, since the ceramic plate 10 side having high thermal conductivity and heat resistance is attached to the IC chip 70, the IC chip can be efficiently cooled, and the resin is not melted, so that the reliability during high heat can be improved. Become.
[0015]
Next, a method for manufacturing the package substrate described above with reference to FIG. 4 will be described with reference to FIGS.
(1) Alumina-lead borosilicate glass powder is made into a 200 to 1000 μm green sheet 10α by a known method. Then, through holes 10a for forming through holes are formed in the green sheet 10α (step (A) shown in FIG. 1).
[0016]
(2) The Ag paste 12α is filled into the through hole 10a of the green sheet 10α (step (B)).
[0017]
(3) The green sheet 10α is fired in air at 950 ° C. for 30 minutes to form the ceramic plate 10 provided with the through holes 12 (step (C)). After firing, the surface of the ceramic plate 10 on the side where the IC chip is placed can be polished and flattened.
[0018]
(4) Next, the insulating resin 40α is applied to the lower surface of the ceramic plate 10 (step (G) shown in FIG. 2). As the insulating resin, a thermosetting resin such as epoxy, BT, polyimide, or olefin, or a mixture of a thermosetting resin and a thermoplastic resin can be used. Moreover, it is also possible to affix a resin film instead of applying resin.
[0019]
(5) After the insulating resin 40α is heated and cured to form the interlayer resin insulating layer 40, the opening diameter 100 to the through hole 12 is formed in the interlayer resin insulating layer 40 by a CO2 laser, YAG laser, excimer laser or UV laser. A 250 μm non-through hole 40a is formed (step (E)).
[0020]
(6) After the desmear treatment, a palladium catalyst is applied and immersed in an electroless plating solution to deposit an electroless plating film 42 having a thickness of 15 μm uniformly on the surface of the interlayer resin insulation layer 40 (FIG. 2). Step (F)). Here, electroless plating is used, but a metal film such as copper or nickel can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage of improving adhesion with the resin.
[0021]
(7) Subsequently, a photosensitive dry film is pasted on the surface of the electroless plating film 42, a mask is placed, exposure and development are performed, and a plating resist resist 43 having a thickness of 15 μm is formed (step (G)). . Then, the ceramic plate 10 is immersed in an electroless plating solution, and an electric current is passed through the electroless plating film 42 to form the electrolytic plating 44 on the non-formed portion of the resist 43 (step (H)).
[0022]
(8) Then, the resist 43 is stripped and removed with 5% KOH and then etched with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove the electroless plating film 42 under the plating resist, and the electroless plating 42 and electrolytic copper plating. A conductor circuit 48 and a via hole 46 having a thickness of 18 μm (10 to 30 μm) made of 44 are obtained (step (I) shown in FIG. 3).
[0023]
Furthermore, it is immersed in chromic acid for 3 minutes, and the surface of the interlayer resin insulation layer 40 between the conductor circuits 48 is etched by 1 μm to remove the palladium catalyst on the surface. Further, a roughened surface (not shown) is formed on the surfaces of the conductor circuit 48 and the via hole 46 by an etching solution containing a cupric complex and an organic acid, and Sn substitution is performed on the surface.
[0024]
(9) The processes (4) to (8) described above are repeated to form the interlayer resin insulation layer 140 and the via hole 146 (step (J) shown in FIG. 3).
[0025]
Solder bumps are formed on the package substrate described above. A solder resist composition is applied to both sides of the substrate in a thickness of 20 μm, dried, and then a 5 mm thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is adhered. And exposed to ultraviolet light for development. Further, heat treatment is performed to form a solder resist layer (thickness 20 μm) 60 having openings 60a in solder pad portions (including via holes and land portions thereof) (step (K)).
[0026]
Then, an electroless nickel plating solution having a pH of 4.5 comprising nickel chloride 2.3 × 10 −1 mol / l, sodium hypophosphite 2.8 × 10 −1 mol / l, sodium citrate 1.6 × 10 −1 mol / l So as to form a nickel plating layer 62 having a thickness of 5 μm in the opening 60a. Furthermore, the substrate was made of potassium gold cyanide 7.6 × 10-3 mol / l, ammonium chloride 1.9 × 10-1 mol / l, sodium citrate 1.2 × 10-1 mol / l, sodium hypophosphite 1.7 × 10-1 mol / l. A gold plating layer 64 having a thickness of 0.03 μm is formed on the nickel plating layer 62 by immersing in an electroless gold plating solution made of l for 7.5 minutes at 80 ° C. (step (L)).
[0027]
Then, a solder paste is filled in the opening 60a of the solder resist layer 60 (not shown). Thereafter, solder bumps (solder bodies) 66 are formed by reflowing the solder filled in the openings 62 at 200 ° C. (see FIG. 4).
[0028]
Next, placement of the IC chip on the package substrate and attachment to the daughter board will be described with reference to FIG. The IC chip 70 is mounted so that the solder pads 72 of the IC chip 70 correspond to the solder bumps 66 of the completed package substrate 100, and the IC chip 70 is attached by performing reflow. Similarly, the package substrate 100 is attached to the daughter board 80 by reflowing the pads 82 of the daughter board 80 onto the solder bumps 66 of the package substrate 100.
[0029]
Subsequently, a package substrate according to a second embodiment of the present invention will be described with reference to FIG. The package substrate of the second embodiment is substantially the same as that of the first embodiment described above. However, in the package substrate of the second embodiment, conductive pins 166 are disposed on the daughter board side, and are formed so as to be connected to the daughter board via the conductive pins 166. In FIG. 6, the conductive pin 166 is a T-type having a protrusion, but a commonly used T-type pin may be used. The material is preferably an alloy such as 42 alloy.
[0030]
Moreover, in 1st Embodiment mentioned above, the through hole 12 of the ceramic board 10 was formed by baking Ag metallizing ink. In contrast, in the second embodiment, the through hole 12 is formed by copper plating.
[0031]
A manufacturing process of the package substrate according to the second embodiment will be described with reference to FIG. First, through-holes 10a are formed in a green sheet 10α of 200 to 1000 μm, and Ag paste 11α is printed on the lower surface (step (A) shown in FIG. 7). Here, an Ag paste is used, but a paste such as W can also be used. The green sheet 10α is fired in air at 950 ° C. for 30 minutes to form the ceramic plate 10 having the conductive layer 11 on the lower surface (step (B)). Then, current is passed through the conductive layer 11 in the electrolytic plating solution to fill the through holes 10a with the copper plating 13 (step (C)). Finally, the conductive layer 11 is removed by polishing, and the ceramic plate 10 having the through holes 12 made of copper plating is formed. Since the subsequent steps are the same as those in the first embodiment, description thereof will be omitted.
[0032]
In the package substrate using the ceramic body 10 of the second embodiment, the resistance of the through hole is lower than that of the first embodiment and the package substrate, so that the wiring resistance can be lowered and all the wiring can be formed of copper. It is possible to reduce the reflection of signals generated at interfaces having different conductivities.
[0033]
【The invention's effect】
Since the thermal expansion coefficient is matched by the package substrate having the structure of the present invention, cracks are hardly generated in the interlayer resin insulating layer. Therefore, reliability is improved. Further, since the IC chip is arranged on the ceramic substrate, the heat released from the IC chip is also diffused from the ceramic substrate, so that cracks and peeling near the interface between the ceramic substrate and the resin layer are prevented. .
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a package substrate according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 3 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of the package substrate according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of the package substrate according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a package substrate according to a second embodiment of the present invention.
FIG. 7 is a manufacturing process diagram of a package substrate according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view of a package substrate according to the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Ceramic board 10a Through-hole 12 Through-hole 22 Wiring 40 Interlayer resin insulation layer 40a Non-through-hole 42 Electroless plating film 43 Resist 44 Electroplating 46 Via hole 48 Conductor circuit 60 Solder resist 60a Opening 62 Nickel plating film 64 Gold plating film 66 Solder bump 70 IC chip 72 Pad 80 Daughter board 82 Pad 140 Resin layer 146 Via hole 166 Conductive pin

Claims (1)

On a ceramic plate in which through holes formed by filling copper plating into the formed through holes are arranged, a package substrate formed by building up an interlayer resin insulation layer and a wiring layer,
Bumps for connection to the IC chip are disposed on the ceramic plate,
A package substrate, wherein bumps or pins for connection to an external resin substrate are disposed on a wiring layer on the interlayer resin insulation layer.

Images