JPH04363093A - Manufacture of printed board - Google Patents
Manufacture of printed boardInfo
- Publication number
- JPH04363093A JPH04363093A JP3285718A JP28571891A JPH04363093A JP H04363093 A JPH04363093 A JP H04363093A JP 3285718 A JP3285718 A JP 3285718A JP 28571891 A JP28571891 A JP 28571891A JP H04363093 A JPH04363093 A JP H04363093A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- solder
- copper
- plating
- electroless
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 70
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000007772 electroless plating Methods 0.000 claims abstract description 10
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 8
- 239000000956 alloy Substances 0.000 claims abstract description 8
- UMGDCJDMYOKAJW-UHFFFAOYSA-N thiourea Chemical compound NC(N)=S UMGDCJDMYOKAJW-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 50
- LSNNMFCWUKXFEE-UHFFFAOYSA-M Bisulfite Chemical compound OS([O-])=O LSNNMFCWUKXFEE-UHFFFAOYSA-M 0.000 claims description 3
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 31
- 229910052802 copper Inorganic materials 0.000 abstract description 31
- 239000010949 copper Substances 0.000 abstract description 31
- 238000007747 plating Methods 0.000 abstract description 30
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 10
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 abstract description 6
- 229910001870 ammonium persulfate Inorganic materials 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract description 3
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 239000002075 main ingredient Substances 0.000 abstract 2
- 239000000243 solution Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000002378 acidificating effect Effects 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- USHAGKDGDHPEEY-UHFFFAOYSA-L potassium persulfate Chemical compound [K+].[K+].[O-]S(=O)(=O)OOS([O-])(=O)=O USHAGKDGDHPEEY-UHFFFAOYSA-L 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/48—Coating with alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0392—Pretreatment of metal, e.g. before finish plating, etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、プリント基板の製造
方法に関し、特に、配線パターン上にはんだを被覆する
プリント基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed circuit board, and more particularly to a method of manufacturing a printed circuit board in which a wiring pattern is coated with solder.
【0002】0002
【従来の技術】プリント基板の銅パターン上にはんだを
被覆する従来の方法を、ガスレベラー法を例に図7に基
づいて説明する。まず、パターニングしてソルダーレジ
ストを塗布したプリント基板1を、槽2内の融解したは
んだ3の中に所定時間浸漬する。その後、図7に示すよ
うに、プリント基板1を槽2から引き上げながら、その
表面に高温高圧のガス4を吹きつけ、銅パターンの余分
なはんだを吹き飛ばすことにより、銅パターン上の所望
の位置にはんだを被覆する。2. Description of the Related Art A conventional method for coating a copper pattern on a printed circuit board with solder will be explained with reference to FIG. 7, using a gas leveler method as an example. First, a printed circuit board 1 that has been patterned and coated with a solder resist is immersed in melted solder 3 in a tank 2 for a predetermined time. Thereafter, as shown in FIG. 7, while the printed circuit board 1 is pulled up from the tank 2, high-temperature, high-pressure gas 4 is blown onto the surface of the printed circuit board 1 to blow off excess solder on the copper pattern, thereby placing it at a desired position on the copper pattern. Cover with solder.
【0003】次に、上記のようなはんだ被覆方法を適用
した多層プリント基板は、
プロセス(1) 内層導体板のパターニングプロセス
(2) 内層導体板の表面処理(黒化処理)プロセス
(3) 積層プレス
プロセス(4) スルホールの穴明け加工プロセス(
5) パネル銅めっき
プロセス(6) 多層導体板のパターニングプロセス
(7) ソルダーレジストおよびシンボル印刷プロセ
ス(8) はんだガスレベラープロセス(9) 外
形加工
のプロセスを経て製造される。[0003] Next, a multilayer printed circuit board to which the above-mentioned solder coating method is applied includes the following steps: (1) Patterning process of the inner layer conductor plate (2) Surface treatment (blackening treatment) process of the inner layer conductor plate (3) Lamination Press process (4) Through-hole drilling process (
5) Panel copper plating process (6) Multilayer conductor plate patterning process (7) Solder resist and symbol printing process (8) Solder gas leveler process (9) Manufactured through external shape processing process.
【0004】0004
【発明が解決しようとする課題】以上のような従来のプ
リント基板の製造方法では、図8および図9に示すよう
に、銅パターン5上に均一かつ平坦にはんだ6を被覆す
ることが困難で、銅パターン5の面積がせまく且つパタ
ーン間隔が狭い部分は、はんだ6の界面張力のためには
んだ6の厚さが大きくなり、図8中でAに示すようには
んだ6同士が短絡をおこしやすくなる。また、短絡を防
ぐために、はんだ6を吹き飛ばすガス4の圧力を大きく
すると、図9中でBに示すように面積の広いパターン上
のはんだ6の厚さが不足し、部品実装の際にはんだぬれ
性が悪くなり接続信頼性を低下させる。さらに、画像認
識装置により部品実装位置を決める場合、認識用パター
ン上のはんだが光沢を持った曲面であるため、周囲の情
景を反射してしまい、位置精度が低下するという等の問
題点があった。[Problems to be Solved by the Invention] In the conventional printed circuit board manufacturing method as described above, it is difficult to uniformly and flatly coat the copper pattern 5 with the solder 6, as shown in FIGS. 8 and 9. In areas where the area of the copper pattern 5 is small and the spacing between the patterns is narrow, the thickness of the solder 6 increases due to the interfacial tension of the solder 6, and the solder 6 tends to short-circuit with each other as shown in A in FIG. Become. Furthermore, if the pressure of the gas 4 used to blow away the solder 6 is increased to prevent short circuits, the thickness of the solder 6 on a pattern with a large area will be insufficient, as shown by B in FIG. This results in poor connection reliability. Furthermore, when determining the component mounting position using an image recognition device, the solder on the recognition pattern has a glossy curved surface, which causes problems such as reflecting the surrounding scene and reducing positioning accuracy. Ta.
【0005】この発明は上記のような問題点を解消する
ためになされたもので、パターン面積の大小によらず表
面の凹凸がなく、均一、かつ平坦にはんだを被覆するこ
とができ、パターン面積が狭くパターン間隔の狭い部分
があっても短絡せず、かつ部品の接続信頼性が高く、さ
らに、部品実装の際の画像認識装置の認識率が向上し、
部品の位置精度を高めることができるプリント基板の製
造方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to coat the solder uniformly and flatly without surface irregularities regardless of the size of the pattern area. Even if there are parts with narrow pattern spacing, there will be no short circuits, and the connection reliability of components is high.Furthermore, the recognition rate of image recognition equipment when mounting components is improved.
The purpose of the present invention is to obtain a method for manufacturing a printed circuit board that can improve the positional accuracy of components.
【0006】[0006]
【課題を解決するための手段】この発明に係る請求項1
のプリント基板の製造方法は、配線パターンを形成した
後に、上記配線パターンに無電解めっきによりスズ・鉛
を主成分とするはんだ合金を被覆するようにしたもので
あり、又、請求項2のプリント基板の製造方法は、配線
パターンを形成した後に、上記配線パターンの一部にソ
ルダーレジストを塗布し、残部露出部分に無電解はんだ
めっきによりスズ・鉛を主成分とするはんだ合金を被覆
するようにしたものであり、さらに、請求項3のプリン
ト基板の製造方法は、スズ(0.1モル/l)、鉛(0
.01モル/l)、有機スルホン酸(0.2モル/l)
、チオ尿素(2モル/l)を主成分とする無電解はんだ
めっき液を使用するものである。[Means for solving the problem] Claim 1 of this invention
The method of manufacturing a printed circuit board according to claim 2 is such that after forming a wiring pattern, the wiring pattern is coated with a solder alloy mainly composed of tin and lead by electroless plating. The manufacturing method of the board is as follows: After forming the wiring pattern, a solder resist is applied to a part of the wiring pattern, and the remaining exposed part is coated with a solder alloy mainly composed of tin and lead by electroless solder plating. Further, the method for manufacturing a printed circuit board according to claim 3 further includes tin (0.1 mol/l), lead (0.
.. 01 mol/l), organic sulfonic acid (0.2 mol/l)
, an electroless solder plating solution containing thiourea (2 mol/l) as a main component is used.
【0007】[0007]
【作用】この発明においては、露出した金属パターン上
に被覆されたはんだは、無電解めっきにより平坦で、か
つ、均一な厚さに形成される。In the present invention, the solder coated on the exposed metal pattern is formed by electroless plating to have a flat and uniform thickness.
【0008】[0008]
実施例1.以下、この発明の実施例1に係るプリント基
板の製造方法におけるプロセスを示す。
プロセス(1) 内層導体板のパターニングプロセス
(2) 内層導体板の表面処理プロセス(3) 積
層プレス
プロセス(4) スルホールの穴明け加工プロセス(
5) パネル銅めっき
プロセス(6) 多層導体板のパターニング(パター
ンメッキ法またはテンティング法)
プロセス(7) ソルダーレジストおよびシンボル印
刷プロセス(8) 無電解はんだめっきプロセス(9
) 外形加工
以上のような製造プロセスによって銅パターン上に無電
解めっきによりはんだを被覆したプリント配線板を形成
する。なお、プロセス(8)と(9)は入れかえても同
様である。Example 1. Hereinafter, a process in a method for manufacturing a printed circuit board according to Example 1 of the present invention will be described. Process (1) Patterning process of inner layer conductor plate (2) Surface treatment process of inner layer conductor plate (3) Lamination press process (4) Through hole drilling process (
5) Panel copper plating process (6) Multilayer conductor plate patterning (pattern plating method or tenting method) Process (7) Solder resist and symbol printing process (8) Electroless solder plating process (9)
) Outline processing A printed wiring board is formed by coating the copper pattern with solder by electroless plating through the manufacturing process described above. Note that processes (8) and (9) are the same even if they are replaced.
【0009】次に、上記プロセス(8)の無電解はんだ
めっきの詳細プロセスについて図1に沿って説明する。
プロセス(8−1) 脱脂(酸性)
プリント配線板表面のよごれ、油脂分、銅パターン上の
酸化物を除去する。
プロセス(8−2) ソフトエッチング(過硫酸アン
モニウム水溶液)
銅パターンの表面を0.5〜2μmエッチングにより除
去して清浄な銅表面を露出させる。
プロセス(8−3) 酸洗(希硫酸)銅表面の酸化物
を除去する。
プロセス(8−4) プリディップ
めっき本浴前にpH、添加剤等の濃度を本浴と同じにし
た液によりプリント基板を濡らすことにより、めっきの
析出の安定化をはかり、本浴への不純物もち込みを防ぎ
、めっき液の寿命を長くする。Next, the detailed process of electroless solder plating in process (8) will be explained with reference to FIG. Process (8-1) Degreasing (acidic) Removes dirt, oil and fat on the surface of the printed wiring board, and oxides on the copper pattern. Process (8-2) Soft etching (ammonium persulfate aqueous solution) The surface of the copper pattern is removed by etching of 0.5 to 2 μm to expose a clean copper surface. Process (8-3) Pickling (dilute sulfuric acid) Removes oxides from the copper surface. Process (8-4) Before the pre-dip plating main bath, the printed circuit board is wetted with a solution with the same pH and concentration of additives as the main bath to stabilize plating precipitation and prevent impurities from entering the main bath. Prevents contamination and extends the life of the plating solution.
【0010】プロセス(8−5) 無電解はんだめっ
き(酸性)
まず、スズ(0.1モル/l)、鉛(0.01モル/l
)、有機スルホン酸(0.2モル/l)、チオ尿素(2
モル/l)を主成分とする無電解はんだめっき液を使用
し、めっき温度70℃、めっき時間15分で、250μ
mピッチ、幅100μmの基板の銅フットパッドパター
ン上に無電解はんだめっきを行った。図3はこのように
して銅フットパッドパターン上に被覆されたはんだ皮膜
の状態を示し、図4はこのはんだ皮膜の厚さとスズ組成
割合を示す。なお、上記のような成分の無電解はんだめ
っき液を使用した場合、図5に示すように、めっき時間
を調節することによって任意のめっき厚さのはんだ皮膜
を銅フットパッドパターン上に形成することができる。Process (8-5) Electroless solder plating (acidic) First, tin (0.1 mol/l), lead (0.01 mol/l)
), organic sulfonic acid (0.2 mol/l), thiourea (2
Using an electroless solder plating solution whose main component is mol/l), the plating temperature is 70°C, and the plating time is 15 minutes.
Electroless solder plating was performed on a copper foot pad pattern of a substrate with m pitch and width of 100 μm. FIG. 3 shows the state of the solder film coated on the copper foot pad pattern in this way, and FIG. 4 shows the thickness and tin composition ratio of this solder film. In addition, when using an electroless solder plating solution with the above components, a solder film with an arbitrary plating thickness can be formed on the copper foot pad pattern by adjusting the plating time, as shown in Figure 5. Can be done.
【0011】無電解はんだめっきでは、金属銅/めっき
液界面で反応が起こり皮膜が形成されるため、隣接する
銅フットパッドパターンから何等影響を受けることなく
、はんだ皮膜が形成される。さらに、金属銅/めっき液
界面でのみ反応が起こるので、はんだ皮膜が析出しても
元の銅フットパッドパターンの形状が維持され、図2に
示すように銅フットパッドパターン5上部は平坦なまま
である。このように、本実施例によれば、微細ピッチの
銅フットパッド上でも、高精度で且つ平坦なはんだ皮膜
7が形成できる。[0011] In electroless solder plating, a reaction occurs at the metal copper/plating solution interface and a film is formed, so that the solder film is formed without being affected by the adjacent copper foot pad pattern. Furthermore, since the reaction occurs only at the metallic copper/plating solution interface, the original shape of the copper footpad pattern is maintained even if the solder film is deposited, and the top of the copper footpad pattern 5 remains flat as shown in Figure 2. It is. In this way, according to this embodiment, a highly accurate and flat solder film 7 can be formed even on copper foot pads with a fine pitch.
【0012】図6に上記実施例によりはんだ被覆された
フットパッドパターン上に、パルスヒート方式によりI
Cパッケージを270℃で、5秒間加熱してはんだ付け
を行った一例を示す。はんだ付け部のピール強度を測定
したところ、はんだ付部が剥離することなくICパッケ
ージのリードが破断し、良好なはんだ付部が得られた。
このように、本実施例によれば、プリント基板の微細ピ
ッチフットパッドパターン上に、厚さを高精度に制御し
てはんだ皮膜を形成できるので、微細ピッチのICパッ
ケージのはんだ付けを容易に行うことができる。
プロセス(8−6) はんだ表面活性化(酸性)はん
だ表面のよごれ酸化物を除去する。FIG. 6 shows that the foot pad pattern coated with solder according to the above embodiment is coated with I by a pulse heating method.
An example in which soldering was performed by heating a C package at 270° C. for 5 seconds is shown. When the peel strength of the soldered part was measured, the leads of the IC package were broken without the soldered part peeling off, and a good soldered part was obtained. As described above, according to this embodiment, it is possible to form a solder film on the fine pitch foot pad pattern of a printed circuit board with the thickness controlled with high precision, making it easy to solder a fine pitch IC package. be able to. Process (8-6) Solder surface activation (acidic) Removes dirt oxides from the solder surface.
【0013】実施例2.上記実施例1においては、ソル
ダーレジストを配線パターンの一部に塗布し、残部露出
部分に無電解めっきによりはんだ合金を被覆しているが
、ソルダーレジストを塗布せずに、配線パターン全体に
無電解めっきによりはんだ合金を被覆しても同様の効果
が得られる。Example 2. In Example 1 above, solder resist is applied to a part of the wiring pattern, and the remaining exposed parts are coated with solder alloy by electroless plating. A similar effect can be obtained by covering the solder alloy with plating.
【0014】実施例3.銅パターン上に被覆されたはん
だ中に1%以下のアンチモンが含まれていてもよい。Example 3. The solder coated on the copper pattern may contain 1% or less antimony.
【0015】実施例4.上記実施例1におけるプロセス
(8−1)の脱脂はアルカリ性であってもよい。Example 4. The degreasing in process (8-1) in Example 1 above may be alkaline.
【0016】実施例5.上記実施例1におけるプロセス
(8−2)のソフトエッチングは、過硫酸ナトリウム、
過硫酸カリウム、硫酸+過酸化水素または過硫酸アンモ
ニウム+硫酸を主成分とする液でもよい。Example 5. The soft etching of process (8-2) in Example 1 above includes sodium persulfate,
A liquid whose main components are potassium persulfate, sulfuric acid + hydrogen peroxide, or ammonium persulfate + sulfuric acid may be used.
【0017】実施例6.上記実施例1におけるプロセス
(8−3)の酸洗は、有機酸、塩酸または硝酸でもよい
。Example 6. The pickling in process (8-3) in Example 1 above may be performed using an organic acid, hydrochloric acid, or nitric acid.
【0018】実施例7.上記実施例1におけるプロセス
(1)の銅パターンの形成は、フルアデイテイブ法、パ
ートリーアッデイテイブ法によってもよい。Example 7. The formation of the copper pattern in process (1) in Example 1 may be performed by a full additive method or a part additive method.
【0019】尚、無電解はんだめっきの処理プロセスは
、プロセス(8−1)〜(8−6)のうち、全てを使用
することを強制するものではなく、又、プリント基板は
、片面、両面、4層以上の多層、セラミック基板、射出
成形基板、曲面基板、ガラス基板等の基板に適用できる
ことはいうまでもない。It should be noted that it is not mandatory to use all of the electroless solder plating processes (8-1) to (8-6), and printed circuit boards can be printed on one or both sides. It goes without saying that the present invention can be applied to multilayer substrates of four or more layers, ceramic substrates, injection molded substrates, curved substrates, glass substrates, and the like.
【0020】[0020]
【発明の効果】以上のように、この発明によれば配線パ
ターンを形成した後、あるいは配線パターンを形成しソ
ルダーレジストを塗布した後に、露出した金属パターン
に無電解めっきにより、スズ、鉛を主成分とするはんだ
合金を被覆するようにしたので、パターンの寸法や、パ
ターン間隔等によらず、パターン上にはんだを均一で、
かつ、平坦に被覆することができる。また、そのために
部品実装時の接続信頼性や位置精度が向上する等の効果
がある。As described above, according to the present invention, after forming a wiring pattern or after forming a wiring pattern and applying a solder resist, tin and lead are mainly applied to the exposed metal pattern by electroless plating. Since the solder alloy that is the component is coated, the solder can be applied uniformly over the pattern regardless of the pattern dimensions or pattern spacing.
Moreover, it can be coated flatly. Moreover, this has the effect of improving connection reliability and positional accuracy during component mounting.
【図1】この発明の実施例1のプリント基板の製造方法
における主要プロセスとしての無電解はんだめっきの詳
細プロセスを示すフロー図である。FIG. 1 is a flowchart showing a detailed process of electroless solder plating as a main process in a printed circuit board manufacturing method according to a first embodiment of the present invention.
【図2】図1における無電解はんだめっきによって形成
されたはんだ皮膜の状態を示す模式断面図である。FIG. 2 is a schematic cross-sectional view showing the state of a solder film formed by electroless solder plating in FIG. 1;
【図3】図2におけるはんだ皮膜の一例を示す図で、(
A)は基板上のはんだ皮膜の表面の状態を示す写真、(
B)ははんだ皮膜の一部を拡大して示す写真である。FIG. 3 is a diagram showing an example of the solder film in FIG.
A) is a photograph showing the surface condition of the solder film on the board, (
B) is an enlarged photograph of a part of the solder film.
【図4】図3におけるはんだ皮膜の厚さとスズ組成割合
を示す特性図である。FIG. 4 is a characteristic diagram showing the thickness and tin composition ratio of the solder film in FIG. 3;
【図5】図1に示す無電解はんだめっきプロセスにおけ
るめっき時間とめっき厚さとの関係を示す特性図である
。5 is a characteristic diagram showing the relationship between plating time and plating thickness in the electroless solder plating process shown in FIG. 1. FIG.
【図6】図3に示すはんだ皮膜上にICパッケージをは
んだ付けした例を示す図で、(A)ははんだ付け部の状
態を示す写真、(B)ははんだ付け部の1部を拡大して
示す写真である。FIG. 6 is a diagram showing an example of an IC package soldered onto the solder film shown in FIG. 3, where (A) is a photograph showing the state of the soldered part, and (B) is an enlarged view of a part of the soldered part. This is a photo shown.
【図7】従来のガスレベラー法によってプリント基板上
にはんだを被覆する要領を説明するための図である。FIG. 7 is a diagram for explaining the procedure for coating solder on a printed circuit board using a conventional gas leveler method.
【図8】従来の方法で形成されたはんだ皮膜の状態の一
例を示す模式断面図である。FIG. 8 is a schematic cross-sectional view showing an example of the state of a solder film formed by a conventional method.
【図9】従来の方法で形成されたはんだ皮膜の状態の他
の例を示す模式断面図である。FIG. 9 is a schematic cross-sectional view showing another example of the state of a solder film formed by a conventional method.
1 基板 5 銅パターン 7 はんだ皮膜 1 Board 5 Copper pattern 7 Solder film
Claims (3)
線パターンに無電解めっきによりスズ・鉛を主成分とす
るはんだ合金を被覆するようにしたことを特徴とするプ
リント基板の製造方法。1. A method for manufacturing a printed circuit board, characterized in that after forming a wiring pattern, the wiring pattern is coated with a solder alloy containing tin and lead as main components by electroless plating.
線パターンの一部にソルダーレジストを塗布し、残部露
出部分に無電解めっきによりスズ・鉛を主成分とするは
んだ合金を被覆するようにしたことを特徴とするプリン
ト基板の製造方法。[Claim 2] After the wiring pattern is formed, a solder resist is applied to a part of the wiring pattern, and the remaining exposed part is coated with a solder alloy mainly composed of tin and lead by electroless plating. A method for manufacturing a printed circuit board, characterized by:
1モル/l)、有機スルホン酸(0.2モル/l)、チ
オ尿素(2モル/l)を主成分とする無電解はんだめっ
き液を使用したことを特徴とする請求項1または請求項
2のいずれかに記載のプリント基板の製造方法。Claim 3: Tin (0.1 mol/l), lead (0.0
1 mol/l), organic sulfonic acid (0.2 mol/l), and thiourea (2 mol/l) as main components. 2. The method for manufacturing a printed circuit board according to any one of 2.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3285718A JPH04363093A (en) | 1990-11-27 | 1991-10-04 | Manufacture of printed board |
AU88078/91A AU8807891A (en) | 1990-11-27 | 1991-11-22 | Method of preparing a printed substrate |
CA002056218A CA2056218A1 (en) | 1990-11-27 | 1991-11-26 | Method of preparing a printed substrate |
KR1019910021292A KR940009173B1 (en) | 1990-11-27 | 1991-11-26 | Method of preparing a printed substrate |
GB9125275A GB2250866A (en) | 1990-11-27 | 1991-11-27 | Method of coating solder on a printed circuit |
DE4139031A DE4139031A1 (en) | 1990-11-27 | 1991-11-27 | METHOD FOR PRODUCING A PRINTED SUBSTRATE |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-321183 | 1990-11-27 | ||
JP32118390 | 1990-11-27 | ||
JP3285718A JPH04363093A (en) | 1990-11-27 | 1991-10-04 | Manufacture of printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04363093A true JPH04363093A (en) | 1992-12-15 |
Family
ID=26556002
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3285718A Pending JPH04363093A (en) | 1990-11-27 | 1991-10-04 | Manufacture of printed board |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPH04363093A (en) |
KR (1) | KR940009173B1 (en) |
AU (1) | AU8807891A (en) |
CA (1) | CA2056218A1 (en) |
DE (1) | DE4139031A1 (en) |
GB (1) | GB2250866A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114885510A (en) * | 2022-04-18 | 2022-08-09 | 安捷利美维电子(厦门)有限责任公司 | Method for reducing black spot pollution of copper surface ink |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4142658A1 (en) * | 1991-12-19 | 1993-06-24 | Siemens Ag | Deposition of solder pattern on circuit boards - applying charge drum collecting pattern of soldered powder particles for transfer to board. |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1690274A1 (en) * | 1967-06-28 | 1971-05-13 | Telefunken Patent | Process for the production of wiring boards with more than two line levels (multilayer circuit boards) |
GB1310880A (en) * | 1969-06-13 | 1973-03-21 | Microponent Dev Ltd | Multi-layer printed circuit board assemblies |
US4093466A (en) * | 1975-05-06 | 1978-06-06 | Amp Incorporated | Electroless tin and tin-lead alloy plating baths |
GB2137421A (en) * | 1983-03-15 | 1984-10-03 | Standard Telephones Cables Ltd | Printed circuits |
DE3425214A1 (en) * | 1984-07-09 | 1986-02-06 | Riedel-De Haen Ag, 3016 Seelze | MEANS FOR THE DEFLECTIVE DEPOSITION OF TIN AND / OR LEAD |
DE3716640C2 (en) * | 1986-05-19 | 1996-03-28 | Harima Chemicals Inc | Process for producing a metal coating on a substrate metal |
JPH02197580A (en) * | 1989-01-24 | 1990-08-06 | Okuno Seiyaku Kogyo Kk | Electroless solder plating bath |
-
1991
- 1991-10-04 JP JP3285718A patent/JPH04363093A/en active Pending
- 1991-11-22 AU AU88078/91A patent/AU8807891A/en not_active Abandoned
- 1991-11-26 CA CA002056218A patent/CA2056218A1/en not_active Abandoned
- 1991-11-26 KR KR1019910021292A patent/KR940009173B1/en not_active IP Right Cessation
- 1991-11-27 DE DE4139031A patent/DE4139031A1/en not_active Ceased
- 1991-11-27 GB GB9125275A patent/GB2250866A/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114885510A (en) * | 2022-04-18 | 2022-08-09 | 安捷利美维电子(厦门)有限责任公司 | Method for reducing black spot pollution of copper surface ink |
CN114885510B (en) * | 2022-04-18 | 2023-07-04 | 安捷利美维电子(厦门)有限责任公司 | Method for reducing black dot pollution of copper surface ink |
Also Published As
Publication number | Publication date |
---|---|
KR940009173B1 (en) | 1994-10-01 |
DE4139031A1 (en) | 1992-06-11 |
GB2250866A (en) | 1992-06-17 |
AU8807891A (en) | 1992-06-04 |
CA2056218A1 (en) | 1992-05-28 |
GB9125275D0 (en) | 1992-01-29 |
KR920011299A (en) | 1992-06-27 |
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