JPH11284316A - Formation of conductor pattern of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming conductor pattern of wiring board by which a conductor pattern forming process can be simplified and the interval between conductor patterns can be made narrower by suppressing the etching of the side face portion of an electroplated copper layer. SOLUTION: A method for forming conductor pattern of wiring board is used for a wiring board on which an electroless-plated copper layer 12 and an electroplated copper layer 16 are successively formed on the surface of an insulating layer 10 formed on the board. The method includes an electroless- plated copper layer 12 forming process for forming the copper layer 12 on the insulating layer 10, a resist forming process for patterning a resist 14 on the copper layer 12, an electroplated copper layer forming process for forming the copper layer 16 on the part of the copper layer 12 exposed from the resist 14, a resist stripping-off process for exposing the other part of the copper layer 12 than the part covered with the copper layer 16 by removing the resist 14, and an electroless-plated copper layer stripping-off process for stripping off the copper layer 12 by using an etchant composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide, and a Cu chelating agent. By this method, a conductor pattern 20 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductive pattern on a wiring board such as a multilayer wiring board.

[0002]

2. Description of the Related Art A conventional method for forming a conductor pattern on a wiring board will be described with reference to FIG. First, the electroless copper plating layer 12 is formed on the insulating layer 10 of the wiring board. FIG.
See (a). Here, the insulating layer includes an insulating layer interposed between the conductive patterns for the purpose of ensuring electrical insulation between the conductive patterns formed in multiple layers on the base material in the case of a multilayer wiring board. And the substrate itself. The same applies hereinafter. Next, a plating resist 14 is patterned on the electroless copper plating layer 12. See FIG. 5 (b).

[0003] Next, an electrolytic copper plating layer 1 is formed on the electroless copper plating layer 12 exposing the electroless copper plating layer 12 as a power supply layer.
6 is subjected to pattern plating. See FIG. 5 (c). Next, an etching resist 18 is formed on the electrolytic copper plating layer 16. See FIG. 5 (d). Examples of the etching resist 18 include solder plating and tin plating. Next, the plating resist 14 is peeled off. See FIG. 5 (e). Next, the exposed electroless copper plating layer 12 is peeled off using an etching solution. See FIG. 5 (f). An alkaline etchant is used as the etchant. Finally, the etching resist 18 on the electrolytic copper plating layer 16 is removed. Thereby, the electroless copper plating layer 1 is formed on the insulating layer 10 of the wiring board.
2, a conductive pattern 20 formed by laminating an electrolytic copper plating layer 16 is formed. See FIG. 5 (g).

[0004]

However, in the above-described method for forming a conductor pattern on a wiring board, an alkaline etching solution is used as an etching solution for peeling off the electroless copper plating layer 12, so that not only the electroless copper plating but also the electroless copper plating is used. Then, electrolytic copper plating is also etched. Therefore, in order to prevent the thickness of the electrolytic copper plating layer 16 mainly forming the conductor pattern 20 from becoming thin, the etching resist 1 as a protective film against the etching solution of the electrolytic copper plating layer 16 is used.
8 is formed on the electrolytic copper plating layer 16, the step of forming the etching resist 18 and the step of removing the etching resist 18 become essential steps, and the step of forming a conductor pattern becomes complicated.

[0005] Even when the etching resist 18 is formed on the electrolytic copper plating layer 16, the side portions of the electrolytic copper plating layer 16 that are not covered with the etching resist 18 may be used as long as the alkaline etching solution is used as the etching solution. The width of the electrolytic copper plating layer 16 is reduced by etching.
For this reason, conventionally, in consideration of the thinning of the electrolytic copper plating layer 16, the electrolytic copper plating layer 16 wider than the target width of the conductor pattern 20 is formed in advance. The width of the electrolytic copper plating layer 16 must be formed wider than the width of the conductive pattern 20 to be formed, and the problem that the interval (gap) between the conductive patterns 20 cannot be reduced to the limit of the resolution of the plating resist 14. is there. Therefore, the present invention has been made to solve the above-mentioned problem, and an object of the present invention is to simplify a process of forming a conductor pattern on a wiring board, and to suppress etching of a side surface portion of an electrolytic copper plating layer to form a conductor pattern between conductor patterns. It is an object of the present invention to provide a method for forming a conductor pattern on a wiring board, which can further reduce the interval.

[0006]

That is, according to the present invention, an electroless copper plating layer is formed on a surface of an insulating layer of a wiring board,
In the method for forming a conductor pattern of a wiring board having an electroless copper plating layer formed on the electroless copper plating layer, an electroless copper plating layer forming step of forming an electroless copper plating layer on the insulating layer; A resist forming step of patterning a plating resist on the electrolytic copper plating layer, an electrolytic copper plating layer forming step of forming an electrolytic copper plating layer on the electroless copper plating layer exposed from the plating resist, and stripping the plating resist A resist stripping step of exposing the electroless copper plating layer other than the electrolytic copper plating layer forming portion, and the exposed electroless copper plating layer is made of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and a Cu chelating agent. And an electroless copper plating layer stripping step of stripping with an etching solution. According to this, in an etching solution composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide, and a Cu chelating agent, the etching rates for these two platings are greatly different from the crystal state difference between electroless copper plating and electrolytic copper plating. It becomes possible to selectively etch the electroless copper plating layer. Therefore, an etching resist for protecting the electrolytic copper plating layer from an etching solution is not required, and a step of forming the etching resist and a step of removing the etching resist can be omitted, and the entire conductor pattern forming step can be simplified. In addition, since the thickness and width of the electrolytic copper plating layer do not become thin or narrow, the thickness and width of the electrolytic copper plating layer can be set to the target thickness and width of the conductor pattern from the beginning. Therefore, a conductor pattern in which the gap is narrowed down to the limit of the resolution of the plating resist can be formed.

Further, if an annealing treatment step of heating the electrolytic copper plating layer is provided before the electroless copper plating layer peeling step, the difference between the crystal states of the electroless copper plating and the electrolytic copper plating is further increased. As a result, the difference in the etching rate increases, so that the electroless copper plating layer can be more selectively etched. Thereby, the etching amount of the electrolytic copper plating layer is further reduced, and a finer conductive pattern can be formed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the method for forming a conductor pattern on a wiring board according to the present invention will be described with reference to the accompanying drawings. First, a method for forming a conductor pattern on a wiring board will be described with reference to FIG. As an example, as in the conventional example, a case where a conductor pattern 20 in which an electrolytic copper plating layer 16 is formed on an electroless copper plating layer 12 on an insulating layer 10 of a wiring board will be described as an example.

First, an electroless copper plating layer forming step of forming an electroless copper plating layer 12 on the surface of the insulating layer 10 of the wiring board is performed. See FIG. 1 (a). Next, the electroless copper plating layer 12
A resist forming step of patterning the plating resist 14 on the surface of the substrate is performed. See FIG. 1 (b). Next, an electrolytic copper plating layer forming step of forming an electrolytic copper plating layer 16 on the surface of the electroless copper plating layer 12 exposed from the plating resist 14 is performed. See FIG. 1 (c). The above is the same as the conventional method for forming a conductor pattern on a wiring board.

Next, in the conventional example, as shown in FIG. 5D, an etching resist 1 is formed on the surface of the electrolytic copper plating layer 16.
However, in the present embodiment, a resist stripping step of stripping the plating resist 14 is performed without performing the step of forming the etching resist 18. Thereby, the electroless copper plating layer 12 other than the portion where the electrolytic copper plating layer 16 is formed is exposed. See FIG. 1 (d). And finally, the electroless copper plating layer 12 exposed using the etching solution.
An electroless copper plating layer peeling step of peeling off. FIG.
See (f). As an etchant, sulfuric acid (4 to 6
%), Hydrogen peroxide (5 to 10%) and a mixed aqueous solution containing a Cu chelating agent (trace amount) is preferable. Further, it is preferable to use a mixed aqueous solution containing CuSO ₄ .5H ₂ O (1% or less) and a sulfonic acid-based organic substance (1% or less). Further, as the Cu chelating agent, a heterocyclic organic substance can be considered. Such an etching solution has different etching rates for the electroless copper plating and the electrolytic copper plating due to a difference in crystal state between the electroless copper plating and the electrolytic copper plating. It can be selectively etched.

Here, the reason why the etching rates of the electroless copper plating and the electrolytic copper plating with respect to the etching solution are different is that, first, X-ray diffraction is performed on each plating film formed by each plating method. Cu film shows the state where Cu atoms are arranged most closely (11).
1) Although there is a peak on the surface, this peak does not exist in the film formed by electroless copper plating, which is considered to be because the electrolytic copper plated film has higher crystallinity than the electroless copper plated film. The peak existing in the film formed by the electrolytic copper plating becomes more remarkable by performing the heat treatment on the electrolytic copper plating film. Second, the electroless copper plating film
Copper deposits in a dotted pattern on the surface of the object to be plated, and the dotted copper is connected to form a plating film. On the other hand, the electrolytic copper plating film is formed by depositing copper in the form of a sheet on the surface of the object to be plated, and due to the difference in the formation method, the electroless copper plating film is compared with the electrolytic copper plating film. It is considered that the surface tends to be rough and is likely to be attacked by the etching solution.

As a result, since the thickness and width of the electrolytic copper plating layer 16 do not become thin,
Since the thickness and width of the electrolytic copper plating layer 16 can be set from the beginning according to the target thickness and width of the conductor pattern 20, the formation of the conductor pattern 20 narrowed to the limit of the resolution of the plating resist 14 And a fine conductor pattern can be formed. Further, as compared with the conventional conductor pattern forming method, an etching resist for protecting the electrolytic copper plating layer 16 from an etching solution is not required, so that the step of forming and removing the etching resist is omitted, and the entire conductor pattern forming step is simplified. In addition, there is an effect that the process time can be reduced.

After the step of forming an electrolytic copper plating layer (FIG. 1C) for forming an electrolytic copper plating layer, a step of peeling off the electroless copper plating layer 12 using an etching solution (FIG. 1).
Before (f)), as shown in FIG. 1 (e), when an annealing treatment step of heating the electrolytic copper plating layer 16 is added, the difference between the crystal states of the electroless copper plating and the electrolytic copper plating is further increased. As a result, the difference in the etching rates increases, so that the electroless copper plating layer 12 can be more selectively etched. Thereby, the etching amount of the electrolytic copper plating layer 16 is further reduced, and a finer conductor pattern can be formed. The conditions of the annealing treatment are, for example, 150 ° C. and 60 minutes in an inert gas (for example, N ₂ gas).

Here, among the etching solutions composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and a Cu chelating agent, those using a heterocyclic organic compound as the Cu chelating agent are most preferred. The thickness (film) of the electrolytic copper plating layer 16 before and after selectively etching the electroless copper plating layer 12 when an annealing treatment is performed and an etching solution containing a heterocyclic organic compound is used. FIG. 2 shows the measurement results of the thickness) and the width (pattern width). In this case, the thickness of the electroless copper plating layer 12 is 2
The annealing conditions were 150 ° C. for 60 minutes, and the etching conditions were immersion time of 3 to 3.5 minutes at a liquid temperature of 25 ° C. or 30 ° C. at a liquid temperature of 30 ° C. in the case of etching by immersion. Is 2 to 2.5 minutes. In the case of etching by spraying, the spray pressure is 0.5 to
Under a condition of 0.7 kgf / cm ² , a spray time is 60 seconds (1 m / min) at a liquid temperature of 30 ° C., or a spray time is 45 seconds (1.2 to 1.4 m / min) at a liquid temperature of 35 ° C. is there. According to this result, the electrolytic copper plating layer 16 after the etching process is thinner by about 1 μm in the thickness of the plating layer than the one before the etching process, and the width is only about 1 μm, and hardly changes. Here, L of L / S indicates the width of the conductor pattern, and S indicates the length of the gap between the conductor patterns.

Further, for the formed conductor pattern 20 of the wiring board, the L / S is set to 20/20, 30/3.
Line-to-line migration when changing as 0, 40/40, 50/50 (Relationship between insulation resistance and time)
FIG. 6 shows the results of the evaluation (insulation evaluation). In the graph of FIG. 6, the data of 40/40 is substantially the same as the data of 30/30. Thus, for any L / S,
Even after a lapse of time, the insulation resistance is larger than the reference insulation resistance value (about 1.0 × 10 ⁸ ohms), and is at a level without any problem. This line-to-line migration uses the evaluation circuit 30 shown in FIG. In the evaluation circuit 30, part A is the conductor pattern 20 formed by the method of the present invention, the pattern width is L, the conductor patterns 20 are parallel to each other, and the interval (gap) between the conductor patterns 20 is Set to S. The voltage applied between the conductor patterns 20 is DC 5 volts.

The reason why the annealing treatment is performed on the electrolytic copper plating layer 16 after the plating resist 14 is peeled off is that if the annealing treatment is also performed on the plating resist 14, the plating resist 14 is generally peeled off. In particular, if the peeling of the plating resist 14 does not decrease even after the annealing treatment, the electrolytic copper plating layer 16 may be subjected to the annealing treatment without peeling the plating resist.

The above-described method for forming a conductor pattern on a wiring board can be used not only for a single-sided wiring board or a double-sided wiring board, but also for a conductor pattern 20a located in an inner layer of a multilayer wiring board 22 or an outer surface as shown in FIG. It can also be used when forming the conductor pattern 20b located. Specifically, the multilayer wiring board 22 is formed by the process (build-up method) shown in FIG. 4, and the conductor pattern 20 a is formed on the surface of the base material 24 of the multilayer wiring board 22 as shown in FIG. The above-described method for forming a conductor pattern of a wiring board can be used for the formation. Further, as shown in FIG. 4B, an insulating layer 10 is formed thereon, and a recess for forming a via is formed on the insulating layer 10. It can also be used when forming the conductor pattern 20a that partially covers 26. See FIG. 4 (c). Further, by repeating the same steps as those shown in FIGS. 4B and 4C, the conductor pattern 20b is formed on the outermost layer via the insulating layer 10 as shown in FIGS. 4D and 4E. Can be formed.

[0018]

According to the present invention, in an etching solution comprising a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and a Cu chelating agent, the etching of these two platings is performed due to the difference in crystal state between electroless copper plating and electrolytic copper plating. Since the rates are greatly different, the electroless copper plating layer can be selectively etched. Therefore, an etching resist for protecting the electrolytic copper plating layer from the etching solution is not required, and the step of forming the etching resist and the step of removing the etching resist can be omitted, and the entire conductor pattern forming step can be simplified. In addition, since the thickness and width of the electrolytic copper plating layer do not become thin or narrow, the thickness and width of the electrolytic copper plating layer can be set to the target thickness and width of the conductor pattern from the beginning. Therefore, there is also an effect that a conductor pattern having a narrow gap can be formed up to the limit of the resolution of the plating resist. Further, after forming the electrolytic copper plating layer and before peeling the electroless copper plating layer using an etchant, a heat treatment is performed on the electrolytic copper plating layer to further crystallize the electroless copper plating and the electrolytic copper plating. Since the difference between the states is increased and the difference between the etching rates is increased, the electroless copper plating layer can be more selectively etched. As a result, there is an effect that the etching amount of the electrolytic copper plating layer is further reduced and a finer conductive pattern can be formed.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for forming a conductor pattern on a wiring board according to the present invention.

FIG. 2 is an evaluation diagram showing the degree of decrease in the film thickness and pattern width of the conductor pattern formed by the conductor pattern forming method shown in FIG. 1 by an etching solution.

FIG. 3 is a sectional view of a multilayer wiring board.

FIG. 4 is a process chart showing a process of forming the multilayer wiring board of FIG. 3 by a build-up method.

FIG. 5 is a process chart showing a conventional method for forming a conductor pattern on a wiring board.

FIG. 6 is a graph showing evaluation results of migration between lines.

FIG. 7 is an evaluation circuit of FIG. 6;

[Description of Signs] 10 Insulating layer 12 Electroless copper plating layer 14 Plating resist 16 Electrolytic copper plating layer 20 Conductor pattern

Claims (2)

[Claims] 1. A method for forming a conductive pattern on a wiring board, comprising: forming an electroless copper plating layer on a surface of an insulating layer of the wiring board; and forming an electrolytic copper plating layer on the electroless copper plating layer. An electroless copper plating layer forming step of forming an electroless copper plating layer on a layer, a resist forming step of patterning a plating resist on the electroless copper plating layer, and the electroless copper plating layer exposed from the plating resist An electrolytic copper plating layer forming step of forming an electrolytic copper plating layer thereon; a resist peeling step of removing the plating resist to expose the electroless copper plating layer other than the electrolytic copper plating layer forming portion; An electroless copper plating layer stripping step of stripping the electroless copper plating layer using an etching solution comprising a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and a Cu chelating agent; The conductive pattern forming method of the wiring board, which comprises. 2. Before the electroless copper plating layer peeling step,
2. The method for forming a conductor pattern on a wiring board according to claim 1, further comprising an annealing step of performing a heat treatment on the electrolytic copper plating layer.