CA2056218A1 - Method of preparing a printed substrate - Google Patents
Method of preparing a printed substrateInfo
- Publication number
- CA2056218A1 CA2056218A1 CA002056218A CA2056218A CA2056218A1 CA 2056218 A1 CA2056218 A1 CA 2056218A1 CA 002056218 A CA002056218 A CA 002056218A CA 2056218 A CA2056218 A CA 2056218A CA 2056218 A1 CA2056218 A1 CA 2056218A1
- Authority
- CA
- Canada
- Prior art keywords
- solder
- wiring pattern
- substrate
- mole
- printed substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/48—Coating with alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0392—Pretreatment of metal, e.g. before finish plating, etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
ABSTRACT
A method of preparing a printed substrate comprises forming a wiring pattern on a substrate and a coating a solder alloy including tin and lead as major components on the wiring pattern by means of electroless plating.
A method of preparing a printed substrate comprises forming a wiring pattern on a substrate and a coating a solder alloy including tin and lead as major components on the wiring pattern by means of electroless plating.
Description
: The present invention relates to a method of preparing a printed substrate. More particularly, it relates to a method of preparing a printed substrate in which solder is coated on a wiring pattern.
Aspec~s of the prior art and present invention will be described by reference to the accompanying drawings in which:
Figure 1 is a flow chart showing the processes o~
electroless plating as major processes in detail in a method of preparing a printed substrate according to Example 1 of the present invention;
Figure 2 is a diagram in cross-section which shows a surface portion of the printed substrate prepared by the electroless plating in Example l;
Figure 3A is a picture showing the surface area of a æolder layer formed on the printed substrate;
Figure 3B is a picture which shows a part of the solder l~yer in a large scale;
Figure 4 is a characteristic diagram showing xelations of the thickness of the solder layer and the formulation of tin in the layer shown in Figure 3;
Figure 5 is a characteristic diagram showing the relation of plating time and the thickness of the solder layer in an electroless plating process in Figure l;
~aL I `
.
, Figure 6 shows an example obtained by soldering an IC ::
package on the solder layer in Figure 3 wherein Figure 6A
is a picture showing a state at a soldered portion and Figure 6B is a picture showing a part of the soldered portion in a large scale;
Figure 7 is a diagram illustrating how solder is coated on a printed substrate by means of hot-air-leveling method;
~ igure 8 is a diagram in cross-section showing a surface area of a printed substrate prepared by a conventional method; and Figure 9 is a diagram in cross-section showing another example of a surface area of a printed substrate prepared by a conventional method.
A conventional method of coating solder on a wiring pattern of copper on a substrate w.i'il be described, by taking a hot-air-levelin~ method as an e~ample, with reference to Fi~ure 7.
The printed substrate 1 which has been subjected to a patterning operation and the coatiny operation of a solder resist is im~ersed for a predetermined time in a vessel 2 in wbich the solder 3 is received in a molten state. When the printed substrate ~ is raised from the ~:
vessel, gas 4 of high temperature and high pressure is blasted on the su~strate surface to blow off an excessive amount of solder deposited on the wiring pattern of copper; thus the solder is covered at a predetermined - la -' - , .
:
a6~8 portion of the wiring pattern of copper.
A method of preparing a multi-layered printed ' substrate in which the above-mentioned solder coating technique is used will be described.
; 5 Process 1: patterning electric conductive plates ; which constitute inner layers.
Process 2: treating the surface of the electric conductive plates constituting inner layers ~blackening).
; Process 3: laminating layers including the inner layers and pressing the lamination.
Process 4: forming a through hole in the lamination.
Process 5: copper-plating the lamination.
Process 6: patterning wire lines on the lamination.
Process 7: printing a solder resist and symbols.
Process 8: hot-air-leveling of solder.
Process 9: processing the outer configuration of the printed substrate.
However, the conventional method of preparing a printed substrate had problems as follows. Namely, as shown in Figures 8 and 9, it was difficult to uniformly and evenly cover the solder 6 on the copper wiring pattern 5, and the thickness of the solder layer was apt to be large due to the interfacial tension of the solder 6 at the portion where the surface area of the copper wiring pattern was small and the distance between the patterned wires was narrow, whereby there was a danger of short-circuitting between adjacent wires (as indicated by 2~362:~&
A in Figure 8). On the other hand, when a pressure of gas 4 for blowing off an excessive amount of the solder 6 was made large in order to avoid the danger of short-circuitting, the thickness of the solder layer on the wiring pattern became insufficient (indicated by B in Figure g), wettability became inferior when structural elements were mounted and reliability to the connection of the elements was reduced.
Further, when element mounting positions were to be determined by means of an image recognition device, accurate positions could not be obtained because the solder has a curved surface which tends to be glossy and therefore, a sight around the solder was reflected.
It is an object of the present invention to provide a method of preparing a printed substrate capable of coating uniformly and evenly solder on the wirin~ pattern irrespective of the magnitude of t;he surface area in which the wiring pattern is formed, without causing unevenn~ss in the surface of the solder, eliminating a 2~ danger of short-circuitting even at a portion ln which the surface area of the wiring pattern is small and the distance between adjacent wires is narrow, providing high reliability to the connection of the structural elements, improving recognizing capability of an image recognition device when the structural elements are to be mounted, and increasing the positional precision of the elements.
In accordance with the present invention, there is provided a method of preparing a printed s~bstrate comprising a step of forming a wiring pattern on a substrate and a step of coating a solder alloy including tin and lead as major components on the wiring pattern by means of ielectroless plating.
In accordance with the present invention, there is provided a method of preparing a printed substrate comprising a ætep of forming a wirin~ pattern on a ~ubstrate, a step of applying a solder resist to a part of the wiring pattern, and a step of coating a solder alloy including tiD and lead as major components on the remaining exposure portion of the wiring pattern by means of electroless plating.
In the method of preparing the printed substrate according to the present invention, a plating solution for electroless plating including ID.l mole/e of tin, 0~01 mole/~ o~ lead, 0.2 mole/e of organic ~ulfonic acid and 2 mole/~ of thiourea as major compon~ents is used.
Since the electroless plating is used for the present invention, solder coated on an exposed metal wiring pattern has a flat surface and an even thickness.
Ai - 4 ~
Pre~erred embodiment o the method of a printed ,~
' :~ 5 .
n .
, .
:
: : "' .
, .
'' ,; ., " ' , :' :
:, ~ ' ,' ' l --" 2~2~ ~
substrate of the present invention will be described.
An example of preparing a printed substrate having a wiring pattern of copper, will be described.
Process 1: patterning electric conductive plates which constitute inner layers.
Process 2: treating the surface of each of the electric conductive plates.
Process 3: laminating plates including the inner conductive plates, and pressing them.
Process 4: drilling a through hole in the lamination.
Process ~: copper-plating of a panel.
Process 6: patterning a mu]ti-layered electric conductive plate (by a pattern-plating method or a tenting method).
Process 7: printing a solder resist and symbols.
Process 8: electroless solder plating.
Process 9: processing the outer configuration of the multi-layered electric conductive plate.
By the above-mentioned processes, a printed wiring board in which solder is coated on the copper wiring pattern by means of electroless plating is obtainable.
In the above-mentioned processes, the processes 8 and 9 may be substituted for each other.
Next, the process of electroless solder plating in the process 8 will be described in detail.
Process 8-1: degreasing (an acid type) 2 ~
Stain and oil on the surface of the printed wiring board and o~ides on the copper wiring pattern are removed.
Process 8-20 soft-etching (ammonium persulfate aqueous solution) The surface of the copper wiring pattern is etched by about 0.5 ~m-2 ~m to expose a clean copper surface.
Process 8-3: pickling tdilute sulfuric acid) Oxides on the copper surface are removed.
Process 8-4: predipping Before conducting the regular dipping of the printed substrate, it is dipped into a liquid having the same p~
and the same concentration of an additive as those of the regular solder bath to wet the printed substrate so as to stabilize the precipitation of the solder, to prevent impurities from entering in the regular solder bath and to prolong the service life o the plating solution.
Process 8-S: electroless solder plating (acid type) A plating solution for electroless plating including 0.1 mole/e of tin, 0.01 mole/~ of lead, 0.2 mole/e of organic sulfonic acid and 2 mole/e of thiourea as major components was used. Electroless plating was conducted on a copper foot pad pattern on a substrate having a pitch of 250 ~m and a width of 100 ~m at plating temperature of 70C for 15 minutes.
Figure 3 shows a state of the solder layer coated on the copper foot pad pattern which is obtained in .. . ~ . .
, ,.
accordance with the above-mentioned process. Figure 4 shows the relation of the thickness of the solder layer and the formulation of tin.
In the case of using the plating solution for electroless plating having the composition described above, the solder layer having a desired thickness can be formed on the copper foot pad pattern by adjusting a plating time as shown in Figure 5.
A reaction takes place at the interface of copper/plating solution in the electroless plating of solder whereby a solder layer is formed without suffering any influence from an adjacent copper foot pad pattern.
Further, since the reaction takes place only at the interface of copper/plating solution, the original shape of the copper foot pad pattern can be maintained even when the solder layer is precipitated, and the upper portion of the copper foot pad pattern 5 can keep a flat state as shown in Figure 2.
Thus, according to this Example, a flat solder layer 7 can be accurately formed on the copper foot pad pattern having a minute pitch.
Figures 6A and 6B show an example wherein an IC
package is soldered by a pulse heat method at 270C for 5 minutes on the foot pad pattern on which a solder layer is coated in accordance with the processes described above.
On measuring peel strength at the soldered portion, 2~2~ ~
it was found that a lead wire of the IC package is broken without peelin~ at the soldered portion. Thus, an excellent result could be obtained.
As described above, in this Example, a solder layer having a thickness which is precisely controlled can be formed on a foot pad pattern having a minute pitch of a printed substrate, and accordingly, an IC package having a minute pitch can be easily attached by soldering to the foot pad pattern.
Process 8-6: Activating the solder surface (acid type) Stain and oxides on the solder layer are removed.
In the above Example 1, the solder resist is applied to a part of the wiring pattern and the solder alloy is coated on the remaining exposed portion by electroless plating. In this Example, however, the solder alloy is coated on the entire wiring pattern without the application of the solder resist, by electroless plating~
The same effect can be obtained in this Example.
The solder alloy coated on the copper wiring pattern may contain antimony of 1 wt~ or less.
The degreaser used for the process 8-1 may ~e of an alkali type.
For the soft-etching in the process 8-2 r a solution comprising sodium persulfate, potassium persulfate, sulfuric acid + hydrogen peroxide, or ammonium persulfate + sulfuric acid as major components may be used.
`:
2 ~ ~ 6 2 ~ 8 For the pickling in the process 8-3, organic acid, hydrochloric acid or nitric acid may be used.
The copper wiring pattern may be formed by a fully additive process or a semi-additive process.
One or more processes among the processes 8-1 to 8-6 for the electroless solder plating may be omitted.
In the printed substrate, a copper wiring pattern may be formed on a single surface or both surfaces of the substrateO Further, the printed substrate may be a multi-layered substrate such as one consisting of four or ; more laminated layers. Further, the substrate may be of ceramics, plastics formed by injection molding, or glass.
Further, the substrate may have a curved surface.
As described above, in accordance with the present lS invention, a wiring pattern is formed on a substrate and a solder alloy including tin and lead as major components is coated entirely or a part of the wiring pattern by electroless plating wherein a solder resist may be applied after forming the wiring pattern. Accordingly, the solder alloy can be coated on the wiring pattern in uniform and flat manner irrespective of the dimensions of the wiring pattern and the distance between adjacent wires in the wiring pattern, whereby reliability to the connection of the elements in mounting and accuracy in positional relation of the elements can be improved.
Aspec~s of the prior art and present invention will be described by reference to the accompanying drawings in which:
Figure 1 is a flow chart showing the processes o~
electroless plating as major processes in detail in a method of preparing a printed substrate according to Example 1 of the present invention;
Figure 2 is a diagram in cross-section which shows a surface portion of the printed substrate prepared by the electroless plating in Example l;
Figure 3A is a picture showing the surface area of a æolder layer formed on the printed substrate;
Figure 3B is a picture which shows a part of the solder l~yer in a large scale;
Figure 4 is a characteristic diagram showing xelations of the thickness of the solder layer and the formulation of tin in the layer shown in Figure 3;
Figure 5 is a characteristic diagram showing the relation of plating time and the thickness of the solder layer in an electroless plating process in Figure l;
~aL I `
.
, Figure 6 shows an example obtained by soldering an IC ::
package on the solder layer in Figure 3 wherein Figure 6A
is a picture showing a state at a soldered portion and Figure 6B is a picture showing a part of the soldered portion in a large scale;
Figure 7 is a diagram illustrating how solder is coated on a printed substrate by means of hot-air-leveling method;
~ igure 8 is a diagram in cross-section showing a surface area of a printed substrate prepared by a conventional method; and Figure 9 is a diagram in cross-section showing another example of a surface area of a printed substrate prepared by a conventional method.
A conventional method of coating solder on a wiring pattern of copper on a substrate w.i'il be described, by taking a hot-air-levelin~ method as an e~ample, with reference to Fi~ure 7.
The printed substrate 1 which has been subjected to a patterning operation and the coatiny operation of a solder resist is im~ersed for a predetermined time in a vessel 2 in wbich the solder 3 is received in a molten state. When the printed substrate ~ is raised from the ~:
vessel, gas 4 of high temperature and high pressure is blasted on the su~strate surface to blow off an excessive amount of solder deposited on the wiring pattern of copper; thus the solder is covered at a predetermined - la -' - , .
:
a6~8 portion of the wiring pattern of copper.
A method of preparing a multi-layered printed ' substrate in which the above-mentioned solder coating technique is used will be described.
; 5 Process 1: patterning electric conductive plates ; which constitute inner layers.
Process 2: treating the surface of the electric conductive plates constituting inner layers ~blackening).
; Process 3: laminating layers including the inner layers and pressing the lamination.
Process 4: forming a through hole in the lamination.
Process 5: copper-plating the lamination.
Process 6: patterning wire lines on the lamination.
Process 7: printing a solder resist and symbols.
Process 8: hot-air-leveling of solder.
Process 9: processing the outer configuration of the printed substrate.
However, the conventional method of preparing a printed substrate had problems as follows. Namely, as shown in Figures 8 and 9, it was difficult to uniformly and evenly cover the solder 6 on the copper wiring pattern 5, and the thickness of the solder layer was apt to be large due to the interfacial tension of the solder 6 at the portion where the surface area of the copper wiring pattern was small and the distance between the patterned wires was narrow, whereby there was a danger of short-circuitting between adjacent wires (as indicated by 2~362:~&
A in Figure 8). On the other hand, when a pressure of gas 4 for blowing off an excessive amount of the solder 6 was made large in order to avoid the danger of short-circuitting, the thickness of the solder layer on the wiring pattern became insufficient (indicated by B in Figure g), wettability became inferior when structural elements were mounted and reliability to the connection of the elements was reduced.
Further, when element mounting positions were to be determined by means of an image recognition device, accurate positions could not be obtained because the solder has a curved surface which tends to be glossy and therefore, a sight around the solder was reflected.
It is an object of the present invention to provide a method of preparing a printed substrate capable of coating uniformly and evenly solder on the wirin~ pattern irrespective of the magnitude of t;he surface area in which the wiring pattern is formed, without causing unevenn~ss in the surface of the solder, eliminating a 2~ danger of short-circuitting even at a portion ln which the surface area of the wiring pattern is small and the distance between adjacent wires is narrow, providing high reliability to the connection of the structural elements, improving recognizing capability of an image recognition device when the structural elements are to be mounted, and increasing the positional precision of the elements.
In accordance with the present invention, there is provided a method of preparing a printed s~bstrate comprising a step of forming a wiring pattern on a substrate and a step of coating a solder alloy including tin and lead as major components on the wiring pattern by means of ielectroless plating.
In accordance with the present invention, there is provided a method of preparing a printed substrate comprising a ætep of forming a wirin~ pattern on a ~ubstrate, a step of applying a solder resist to a part of the wiring pattern, and a step of coating a solder alloy including tiD and lead as major components on the remaining exposure portion of the wiring pattern by means of electroless plating.
In the method of preparing the printed substrate according to the present invention, a plating solution for electroless plating including ID.l mole/e of tin, 0~01 mole/~ o~ lead, 0.2 mole/e of organic ~ulfonic acid and 2 mole/~ of thiourea as major compon~ents is used.
Since the electroless plating is used for the present invention, solder coated on an exposed metal wiring pattern has a flat surface and an even thickness.
Ai - 4 ~
Pre~erred embodiment o the method of a printed ,~
' :~ 5 .
n .
, .
:
: : "' .
, .
'' ,; ., " ' , :' :
:, ~ ' ,' ' l --" 2~2~ ~
substrate of the present invention will be described.
An example of preparing a printed substrate having a wiring pattern of copper, will be described.
Process 1: patterning electric conductive plates which constitute inner layers.
Process 2: treating the surface of each of the electric conductive plates.
Process 3: laminating plates including the inner conductive plates, and pressing them.
Process 4: drilling a through hole in the lamination.
Process ~: copper-plating of a panel.
Process 6: patterning a mu]ti-layered electric conductive plate (by a pattern-plating method or a tenting method).
Process 7: printing a solder resist and symbols.
Process 8: electroless solder plating.
Process 9: processing the outer configuration of the multi-layered electric conductive plate.
By the above-mentioned processes, a printed wiring board in which solder is coated on the copper wiring pattern by means of electroless plating is obtainable.
In the above-mentioned processes, the processes 8 and 9 may be substituted for each other.
Next, the process of electroless solder plating in the process 8 will be described in detail.
Process 8-1: degreasing (an acid type) 2 ~
Stain and oil on the surface of the printed wiring board and o~ides on the copper wiring pattern are removed.
Process 8-20 soft-etching (ammonium persulfate aqueous solution) The surface of the copper wiring pattern is etched by about 0.5 ~m-2 ~m to expose a clean copper surface.
Process 8-3: pickling tdilute sulfuric acid) Oxides on the copper surface are removed.
Process 8-4: predipping Before conducting the regular dipping of the printed substrate, it is dipped into a liquid having the same p~
and the same concentration of an additive as those of the regular solder bath to wet the printed substrate so as to stabilize the precipitation of the solder, to prevent impurities from entering in the regular solder bath and to prolong the service life o the plating solution.
Process 8-S: electroless solder plating (acid type) A plating solution for electroless plating including 0.1 mole/e of tin, 0.01 mole/~ of lead, 0.2 mole/e of organic sulfonic acid and 2 mole/e of thiourea as major components was used. Electroless plating was conducted on a copper foot pad pattern on a substrate having a pitch of 250 ~m and a width of 100 ~m at plating temperature of 70C for 15 minutes.
Figure 3 shows a state of the solder layer coated on the copper foot pad pattern which is obtained in .. . ~ . .
, ,.
accordance with the above-mentioned process. Figure 4 shows the relation of the thickness of the solder layer and the formulation of tin.
In the case of using the plating solution for electroless plating having the composition described above, the solder layer having a desired thickness can be formed on the copper foot pad pattern by adjusting a plating time as shown in Figure 5.
A reaction takes place at the interface of copper/plating solution in the electroless plating of solder whereby a solder layer is formed without suffering any influence from an adjacent copper foot pad pattern.
Further, since the reaction takes place only at the interface of copper/plating solution, the original shape of the copper foot pad pattern can be maintained even when the solder layer is precipitated, and the upper portion of the copper foot pad pattern 5 can keep a flat state as shown in Figure 2.
Thus, according to this Example, a flat solder layer 7 can be accurately formed on the copper foot pad pattern having a minute pitch.
Figures 6A and 6B show an example wherein an IC
package is soldered by a pulse heat method at 270C for 5 minutes on the foot pad pattern on which a solder layer is coated in accordance with the processes described above.
On measuring peel strength at the soldered portion, 2~2~ ~
it was found that a lead wire of the IC package is broken without peelin~ at the soldered portion. Thus, an excellent result could be obtained.
As described above, in this Example, a solder layer having a thickness which is precisely controlled can be formed on a foot pad pattern having a minute pitch of a printed substrate, and accordingly, an IC package having a minute pitch can be easily attached by soldering to the foot pad pattern.
Process 8-6: Activating the solder surface (acid type) Stain and oxides on the solder layer are removed.
In the above Example 1, the solder resist is applied to a part of the wiring pattern and the solder alloy is coated on the remaining exposed portion by electroless plating. In this Example, however, the solder alloy is coated on the entire wiring pattern without the application of the solder resist, by electroless plating~
The same effect can be obtained in this Example.
The solder alloy coated on the copper wiring pattern may contain antimony of 1 wt~ or less.
The degreaser used for the process 8-1 may ~e of an alkali type.
For the soft-etching in the process 8-2 r a solution comprising sodium persulfate, potassium persulfate, sulfuric acid + hydrogen peroxide, or ammonium persulfate + sulfuric acid as major components may be used.
`:
2 ~ ~ 6 2 ~ 8 For the pickling in the process 8-3, organic acid, hydrochloric acid or nitric acid may be used.
The copper wiring pattern may be formed by a fully additive process or a semi-additive process.
One or more processes among the processes 8-1 to 8-6 for the electroless solder plating may be omitted.
In the printed substrate, a copper wiring pattern may be formed on a single surface or both surfaces of the substrateO Further, the printed substrate may be a multi-layered substrate such as one consisting of four or ; more laminated layers. Further, the substrate may be of ceramics, plastics formed by injection molding, or glass.
Further, the substrate may have a curved surface.
As described above, in accordance with the present lS invention, a wiring pattern is formed on a substrate and a solder alloy including tin and lead as major components is coated entirely or a part of the wiring pattern by electroless plating wherein a solder resist may be applied after forming the wiring pattern. Accordingly, the solder alloy can be coated on the wiring pattern in uniform and flat manner irrespective of the dimensions of the wiring pattern and the distance between adjacent wires in the wiring pattern, whereby reliability to the connection of the elements in mounting and accuracy in positional relation of the elements can be improved.
Claims (7)
1. A method of preparing a printed substrate comprising a step of forming a wiring pattern on a substrate and a step of coating a solder alloy including tin and lead as major components on said wiring pattern by means of electroless plating.
2. The method according to Claim 1, wherein said substrate is a multi-layered substrate.
3. The method according to Claim 1, wherein said substrate is dipped in a solution to wet the same before the electroless plating.
4. The method according to Claim 1, wherein a plating solution for electroless plating including 0.1 mole/? of tin, 0.01 mole/? of lead, 0.2 mole/? of organic sulfonic acid and 2 mole/? of thiourea as major components is used.
5. A method of preparing a printed substrate comprising a step of forming a wiring pattern on a substrate, a step of applying a solder resist to a part of said wiring pattern, and a step of coating a solder alloy including tin and lead as major components on the remaining exposure portion of the wiring pattern by means of electroless plating.
6. The method according to Claim 5, wherein said substrate is a multi-layered substrate.
7. The method according to Claim 5, wherein a plating solution for electroless plating including 0.1 mole/? of tin, 0.01 mole/? of lead, 0.2 mole/? of organic sulfonic acid and 2 mole/? of thiourea as major components is used.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP321183/1990 | 1990-11-27 | ||
| JP32118390 | 1990-11-27 | ||
| JP285718/1991 | 1991-10-04 | ||
| JP3285718A JPH04363093A (en) | 1990-11-27 | 1991-10-04 | Manufacture of printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2056218A1 true CA2056218A1 (en) | 1992-05-28 |
Family
ID=26556002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002056218A Abandoned CA2056218A1 (en) | 1990-11-27 | 1991-11-26 | Method of preparing a printed substrate |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04363093A (en) |
| KR (1) | KR940009173B1 (en) |
| AU (1) | AU8807891A (en) |
| CA (1) | CA2056218A1 (en) |
| DE (1) | DE4139031A1 (en) |
| GB (1) | GB2250866A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4142658A1 (en) * | 1991-12-19 | 1993-06-24 | Siemens Ag | Deposition of solder pattern on circuit boards - applying charge drum collecting pattern of soldered powder particles for transfer to board. |
| CN114885510B (en) * | 2022-04-18 | 2023-07-04 | 安捷利美维电子(厦门)有限责任公司 | Method for reducing black dot pollution of copper surface ink |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1690274A1 (en) * | 1967-06-28 | 1971-05-13 | Telefunken Patent | Process for the production of wiring boards with more than two line levels (multilayer circuit boards) |
| GB1310880A (en) * | 1969-06-13 | 1973-03-21 | Microponent Dev Ltd | Multi-layer printed circuit board assemblies |
| US4093466A (en) * | 1975-05-06 | 1978-06-06 | Amp Incorporated | Electroless tin and tin-lead alloy plating baths |
| GB2137421A (en) * | 1983-03-15 | 1984-10-03 | Standard Telephones Cables Ltd | Printed circuits |
| DE3425214A1 (en) * | 1984-07-09 | 1986-02-06 | Riedel-De Haen Ag, 3016 Seelze | MEANS FOR THE DEFLECTIVE DEPOSITION OF TIN AND / OR LEAD |
| DE3716640C2 (en) * | 1986-05-19 | 1996-03-28 | Harima Chemicals Inc | Process for producing a metal coating on a substrate metal |
| JPH02197580A (en) * | 1989-01-24 | 1990-08-06 | Okuno Seiyaku Kogyo Kk | Electroless solder plating bath |
-
1991
- 1991-10-04 JP JP3285718A patent/JPH04363093A/en active Pending
- 1991-11-22 AU AU88078/91A patent/AU8807891A/en not_active Abandoned
- 1991-11-26 KR KR1019910021292A patent/KR940009173B1/en not_active IP Right Cessation
- 1991-11-26 CA CA002056218A patent/CA2056218A1/en not_active Abandoned
- 1991-11-27 DE DE4139031A patent/DE4139031A1/en not_active Ceased
- 1991-11-27 GB GB9125275A patent/GB2250866A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04363093A (en) | 1992-12-15 |
| DE4139031A1 (en) | 1992-06-11 |
| GB9125275D0 (en) | 1992-01-29 |
| KR920011299A (en) | 1992-06-27 |
| KR940009173B1 (en) | 1994-10-01 |
| GB2250866A (en) | 1992-06-17 |
| AU8807891A (en) | 1992-06-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |