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JP2531451B2 - Solder film forming method - Google Patents

Solder film forming method

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Publication number
JP2531451B2
JP2531451B2 JP23934493A JP23934493A JP2531451B2 JP 2531451 B2 JP2531451 B2 JP 2531451B2 JP 23934493 A JP23934493 A JP 23934493A JP 23934493 A JP23934493 A JP 23934493A JP 2531451 B2 JP2531451 B2 JP 2531451B2
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JP
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Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23934493A
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Japanese (ja)
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JPH0794852A (en )
Inventor
栄治 前畑
Original Assignee
日本電気株式会社
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Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半田膜形成方法に関し、 The present invention relates to an solder film forming method,
特にプリント配線板における半田膜形成方法に関する。 In particular to the solder film forming method of the printed wiring board.

【0002】 [0002]

【従来の技術】プリント配線板の銅回路表面には、半田付けや防食を目的として半田が被覆されている。 The surface of the copper circuit of the prior art printed wiring board, a solder is coated for the purpose of soldering or corrosion. 従来のプリント配線板の銅回路に半田を被覆する方法としては、溶融半田めっき法が用いられている。 As a method of coating the solder on the copper circuitry of a conventional printed circuit board, molten solder plating method is used. この方法は、 This method,
一般的には、溶融半田浴に銅回路パターンが形成されたプリント配線板を浸漬した後、銅回路上に過剰に付着した半田を240℃程度に加熱された空気を吹き付けて除去する方法である。 In general, after the copper circuit pattern was immersed printed wiring board formed in the molten solder bath is a method of removing by blowing air heated to solder excessively deposited on the copper circuit at about 240 ° C. .

【0003】近年、表面実装技術の進展に伴い、プリント配線板上に形成される半田膜は、均一かつ20μm程度の膜厚が要求されており、溶融半田のめっき膜厚が0.5〜30μmの範囲で大きくばらつくことが大きな問題点となっている。 In recent years, with the progress of surface mount technology, the solder film formed on a printed wiring board is a thickness of about uniform and 20μm is required, the plating film thickness of the solder melting 0.5~30μm has become a major problem is that the large variation in the range of. 溶融半田めっき法で形成された半田膜が薄い場合には、銅−スズの合金層が半田膜表面に拡散し半田濡れを著るしく損ね、逆に半田膜が厚い場合には、プリント配線板の回路間隔が狭い部分で溶融半田のブリッジによるショート不具合が多発するという問題点があった。 Melt when the solder plating solder film formed by the thin, copper - impaired Silurian properly alloy layers a diffusion solder wetting to solder film surface of the tin, when the solder film is thick on the contrary, the printed circuit board short defect circuit interval is due to molten solder of the bridge in a narrow part of the there has been a problem that frequently.

【0004】一方、プリント配線板のパターンめっき法でエッチングレジストとして使用される電気半田めっき皮膜を再溶融することによって半田を形成する方法が実施されているが、この場合、半田めっき皮膜の厚みを1 On the other hand, a method of forming a solder by re-melting the electrical solder plating film used as etching resist in a pattern plating method of the printed wiring board is carried out, in this case, the thickness of the solder plated film 1
0μm以上にすることは、めっきレジストの厚みの制限等から難かしい。 Be more than 0μm is Kashii flame from Restriction on the thickness of the plating resist. その改善方法として、特開昭63−1 As a method for improving, JP-A-63-1
42893号公報に電気半田めっき上に半田ペースト等により補助半田膜を形成後、再溶融することによって充分な膜厚を有する半田膜を形成する方法が開示されているが、スクリーン印刷技術の技術的制限により0.5m After forming an auxiliary solder layer by the solder paste on the electrical solder plating 42893 discloses, a method of forming a solder film having a sufficient thickness by re-melting it has been disclosed, the technical screen printing techniques limited by 0.5m
mピッチのSMT(Surface Mount Te m pitch of SMT (Surface Mount Te
chnology)部品パッドに対してこの技術を適用することは難かしい。 Chnology) applying this technique to the component pads Kashii flame.

【0005】 [0005]

【発明が解決しようとする課題】以上説明した様に、従来の溶融半田めっき方法は、均一な膜厚を有する半田膜の形成が困難であり、半田濡れ性の劣化,溶融半田のブリッジによるショートといった問題点があった。 As described INVENTION Problems to be Solved] above, solder plating method conventional melt is difficult to form a solder film having a uniform thickness, solderability degradation, short-circuit due to molten solder bridge a problem that there is.

【0006】また、電気半田めっき法では、充分な半田膜厚が得られないという問題点があり、充分な半田量を半田ペースト等で補充する技術でも現在の微細なSMT [0006] In the electric soldering plating, sufficient there is a problem that the solder thickness can not be obtained, sufficient solder amount of the current fine supplemented technology in the solder paste or the like SMT
部品パッドには適用ができないという問題点があった。 The parts pad there is a problem that can not be applied.

【0007】本発明の目的は、半田濡れ性の劣化や溶融半田のブリッジによるショートがなく均一な半田膜の形成が容易で、現在の微細なSMT部品パッドにも適用できる半田膜形成方法を提供することにある。 An object of the present invention is easy to form the solder wettability without damage or short circuit due to molten solder bridges uniform solder film, providing a solder film forming method can be applied to the current fine SMT components pads It is to.

【0008】 [0008]

【課題を解決するための手段】本発明の半田膜形成方法は、プリント配線板の銅回路上にドライフィルムレジストを含む感光性レジストよりなる半田めっきレジスト膜を被覆する工程と、この半田めっきレジスト膜が被覆されていない部分の前記銅回路上に緻密質な構造を有する薄付用無電解半田めっきを施し第1の半田皮膜を形成する工程と、前記半田めっきレジスト膜を除去する工程と、前記第1の半田皮膜が形成されていない部分の前記銅回路上に多孔質な構造を有する厚付け用無電解半田めっきを施し第2の半田皮膜を形成する工程と、加熱により前記第1の半田皮膜と前記第2の半田皮膜とを溶融一体化し前記銅回路上に半田膜を形成する工程とを含む。 Solder film forming method of the present invention, in order to solve the problems] includes the step of coating a solder plating resist film of a photosensitive resist comprising a dry film resist on the copper circuit of the printed wiring board, the solder plating resist a step of film forming the first solder film subjected to electroless solder plating with a thin having a dense structure on the copper circuit part which is not covered, and removing the solder plating resist layer, and forming the first of said copper circuit second solder film subjected to electroless solder plating thickness with having a porous structure on the portion where the solder coating is not formed, the first by heating solder coating and a second solder coating is melted integrally and forming a solder layer on the copper circuit.

【0009】 [0009]

【実施例】次に、本発明の実施例について図面を参照して説明する。 EXAMPLES will be described with reference to the accompanying drawings embodiments of the present invention.

【0010】図1(a)〜(e)は本発明の第1の実施例を説明する工程順に示した断面図である。 [0010] Figure 1 (a) ~ (e) are cross-sectional views showing a process sequence for illustrating a first embodiment of the present invention. 本発明の第1の実施例は、まず、図1(a)に示す様に、サブトラクティブ法等により幅0.3mmの銅回路1を0.3m The first embodiment of the present invention, first, as shown in FIG. 1 (a), the copper circuit 1 of width 0.3mm by a subtractive method 0.3m
mのピッチで形成し、銅回路1間にスクリーン印刷等により半田保護膜6を印刷しプリント配線板を形成する。 It was formed at a pitch of m, to form the printed printed circuit board the solder protective layer 6 by screen printing or the like between the copper circuit 1.
次に、図1(b)に示す様に、膜厚50μmの感光性ドライフィルムレジストをラミネートし、露光,現象により銅回路中央部に幅0.2mmの半田めっきレジスト膜2を形成する。 Next, as shown in FIG. 1 (b), by laminating a photosensitive dry film resist having a thickness of 50 [mu] m, exposing, forming solder plating resist film 2 having a width 0.2mm copper circuit central portion by phenomenon.

【0011】次に、図1(c)に示す様に、このプリント配線板に前処理として過酸化水素水溶液で30℃、1 [0011] Next, as shown in FIG. 1 (c), 30 ° C. in an aqueous hydrogen peroxide solution as a pretreatment in the printed circuit board, 1
分間のエッチングを行い水洗処理後、液温55℃の薄付用無電解半田めっき液に約30 間浸漬し、約3μmの緻密質な構造を有する第1の半田被膜3を得た。 After water washing treatment was etched in minutes, liquid temperature 55 between thin with a electroless solder plating solution for about 30 minutes immersion ° C., to obtain a first solder coating 3 having a dense structure of approximately 3 [mu] m. 薄付用無電解半田めっき液としては、チオ尿素100g/l, The thin electroless solder plating solution for with, thiourea 100g / l,
ホウフッ化スズ0.1mol/l,フッ化鉛0.03m Borofluoride tin 0.1mol / l, lead fluoride 0.03m
ol/lの組成のものを用いた。 Used was a composition of ol / l. 次に、図1(d)に示す様に、半田めっきレジスト膜2をドライフィルムレジスト剥離液により除去した後、厚付用無電解半田めっき液に約1時間浸漬し約20μmの多孔質な第2の半田被膜4を得た。 Next, as shown in FIG. 1 (d), after the solder plating resist film 2 is removed by a dry film resist stripping solution, porous approximately 1 hour immersion for about 20μm in an electroless solder plating solution for with thicknesses first 2 was obtained solder coating 4. 厚付用無電解半田めっき液としては、上村工業(株)のビームソルダーPCを用いた。 The electroless solder plating solution for with thickness, using a beam solder PC of Uemura & Co., Ltd.. その後、図1(e)に示す様に、200℃の溶融油に約20秒間浸漬し第1の半田被膜3と第2の半田被膜4を溶融一体化させ20μmの膜厚を有する半田膜5を得た。 Thereafter, as shown in FIG. 1 (e), the solder film has a first solder coating 3 was dipped for about 20 seconds to 200 ° C. of melting oil film thickness of the second 20μm solder coating 4 is melted integrally 5 It was obtained.

【0012】この結果、図1(d),(e)に示す様に、銅回路1の表面は凹状となり、凹部の半田膜5の厚みは約20μm,凹部肩部分の半田膜5の厚みは約3μ [0012] Consequently, as shown in FIG. 1 (d), (e), the surface of the copper circuit 1 becomes concave, approximately the thickness of the solder layer 5 of the recess 20 [mu] m, the thickness of the solder layer 5 of the recess shoulder about 3μ
mとなった。 It became a m. これは、第1の半田皮膜3が緻密質な構造を有しているため、第2の半田皮膜4形成時にめっき液が銅回路1の銅と置換反応を生じることがないため、第2の半田皮膜4は第1の半田皮膜3に被覆されていな銅回路1上のみに析出するためである。 This is because the first solder film 3 has a dense structure, the plating solution when the second solder film 4 formed because there is not caused copper and substitution reaction of the copper circuit 1, the second the solder coating 4 is to deposit only the first solder film 3 coated have a copper circuit on 1.

【0013】図2(a)〜(e)は本発明の第2の実施例を説明する工程順に示した断面図である。 [0013] FIG. 2 (a) ~ (e) are cross-sectional views showing a process order to explain the second embodiment of the present invention. 本発明の第2の実施例は、図2(a)〜(e)に示す様に、幅が0.3mmの銅回路1上に0.3mm幅の半田めっきレジスト膜2を形成した以外は、図1(a)〜(e)に示す第1の実施例と同じである。 Second embodiment of the present invention, as shown in FIG. 2 (a) ~ (e), except that the width of the formation of the solder plating resist film 2 of 0.3mm width on the copper circuit 1 of 0.3mm is the same as that of the first embodiment shown in FIG. 1 (a) ~ (e). 第2の実施例では、図2 In a second embodiment, FIG. 2
(d),(e)に示す様に、銅回路1の断面は長方形になり、厚み約18μmの半田膜5が銅回路1上に均一に形成された。 As shown in (d), (e), the cross section of the copper circuit 1 becomes rectangular, solder film 5 having a thickness of about 18μm is uniformly formed on the copper circuit 1. 一方、第1の半田皮膜3と第2の半田皮膜4の濡れ性が良いため、隣接する銅回路1同士のブリッジによるショートや半田ボール等の不具合の発生は皆無であった。 Meanwhile, since the first solder film 3 good second wettability of the solder film 4, occurrence of defects such as short circuit or solder balls by bridging between the copper circuit 1 adjacent there was no.

【0014】 [0014]

【発明の効果】以上説明した様に本発明は、銅回路上に緻密質な構造を有する第1の半田皮膜と、第1の半田皮膜が形成されていない銅回路上に多孔質な構造の第2の半田皮膜を形成し、加熱により第1の半田皮膜と第2の半田皮膜とを溶融一体化し銅回路上に半田膜を形成することにより、半田濡れ性の劣化や溶融半田のブリッジによるショートがなく均一な半田膜の形成が容易で、現在の微細なSMT部品の実装にも適用できる半田膜形成方法を提供できるという効果がある。 The present invention as described above, according to the present invention includes a first solder coating having a dense structure on the copper circuitry, a porous structure to the first solder coating on a copper circuit is not formed forming a second solder coating of the first solder coating and the second and by forming a solder film on the molten integrated on the copper circuitry a solder coating, solder wettability deteriorates and the molten solder bridges by heating short without forming a uniform solder film is easy, there is an effect that it provides a solder film forming method can be applied to the implementation of the current fine SMT components.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】(a)〜(e)は本発明の第1の実施例を説明する工程順に示した断面図である。 [1] (a) ~ (e) are cross-sectional views showing a process sequence for illustrating a first embodiment of the present invention.

【図2】(a)〜(e)は本発明の第2の実施例を説明する工程順に示した断面図である。 Figure 2 (a) ~ (e) are cross-sectional views showing a process order to explain the second embodiment of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 銅回路 2 半田めっきレジスト膜 3 第1の半田皮膜 4 第2の半田皮膜 5 半田膜 6 半田保護膜 1 copper circuit 2 solder plating resist film 3 first solder coating 4 second solder film 5 solder film 6 solder protective film

Claims (1)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】 プリント配線板の銅回路上の一部分に半田めっきレジスト膜を被覆する工程と、この半田めっきレジスト膜が被覆されていない部分の前記銅回路上およびこの銅回路側面に薄付用無電解半めっきを施し第1 1. A a process for coating a portion of the copper circuit of the printed wiring board solder plating resist film, for with thin on the copper circuit and on the copper circuit side of the portion where the solder plating resist film is not coated first subjected to non-electrolytic half field-plated 1
    の半田被膜を形成する工程と、前記半田めっきレジスト膜を除去する工程と、前記第1の半田被膜が形成されていない部分の前記銅回路上に置換半田めっきによる厚付用無電解半田めっきを施し第2の半田被膜を形成する工程と、加熱により互に隣接した前記第1の半田被膜と前記第2の半田被膜とを溶融一体化し前記銅回路上に半田膜を形成工程とを含むことを特徴とする半田膜形成方法。 Of forming a solder coating, removing the solder plating resist film, the first of the copper circuit electroless solder plating with a thickness by substitution solder plating on the portion where the solder coating is not formed the subjecting comprises forming a second solder coating, and each other form adjacent said first and said solder coating the second solder coating melts integrated solder layer on the copper circuit step by heating solder film forming method comprising.
JP23934493A 1993-09-27 1993-09-27 Solder film forming method Expired - Fee Related JP2531451B2 (en)

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Application Number Priority Date Filing Date Title
JP23934493A JP2531451B2 (en) 1993-09-27 1993-09-27 Solder film forming method

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JPH0794852A true JPH0794852A (en) 1995-04-07
JP2531451B2 true JP2531451B2 (en) 1996-09-04

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JP2001075501A (en) * 1999-07-02 2001-03-23 Seiko Instruments Inc Display device and method for inspection of display device

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