JPH0354873B2 - - Google Patents
Info
- Publication number
- JPH0354873B2 JPH0354873B2 JP14358184A JP14358184A JPH0354873B2 JP H0354873 B2 JPH0354873 B2 JP H0354873B2 JP 14358184 A JP14358184 A JP 14358184A JP 14358184 A JP14358184 A JP 14358184A JP H0354873 B2 JPH0354873 B2 JP H0354873B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- solder dam
- circuit board
- soldering
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920001721 polyimide Polymers 0.000 claims description 30
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 28
- 238000007747 plating Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 239000004642 Polyimide Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 229910052763 palladium Inorganic materials 0.000 claims description 14
- 239000009719 polyimide resin Substances 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000005476 soldering Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 11
- 239000002243 precursor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 21
- 239000000758 substrate Substances 0.000 description 14
- 239000000919 ceramic Substances 0.000 description 4
- 239000002966 varnish Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、回路部品を搭載する回路基板および
その製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a circuit board on which circuit components are mounted and a method for manufacturing the same.
従来、基板上におけるはんだ付け部分のソルダ
ーダムをポリイミド樹脂を用いて形成する方法と
しては、例えば特開昭55−43252号を参照できる。
すなわち、金属パターン上に非感光性ポリイミド
前駆体（プレポリマー）溶液を塗布し、それから
それを熱処理してポリイミド樹脂層とする。その
後、このポリイミド樹脂層に、ホトレジスト等を
用いて必要とするソルダーダムのパターンをエツ
チングする。ところが、このような方法では、ポ
リイミド樹脂層を形成した後に、レジスト等を用
いてのエツチングを行なうため、必要工程数が多
く、完成までに長い時間を要する。
For a conventional method of forming a solder dam at a soldered portion on a board using polyimide resin, see, for example, Japanese Patent Laid-Open No. 43252/1983.
That is, a non-photosensitive polyimide precursor (prepolymer) solution is applied onto the metal pattern, and then it is heat treated to form a polyimide resin layer. Thereafter, a required solder dam pattern is etched into this polyimide resin layer using photoresist or the like. However, in such a method, etching using a resist or the like is performed after forming the polyimide resin layer, so a large number of steps are required and it takes a long time to complete the process.
しかも、ポリイミド樹脂のエツチング剤に耐え
ることのできるレジスト等が少ないために、高精
度、高密度なパターン形成が困難であるという欠
点がある。 Moreover, since there are few resists that can withstand etching agents for polyimide resins, it is difficult to form patterns with high precision and high density.
本発明の目的は、ポリイミド樹脂によるソルダ
ーダムを容易にかつ高精度、高密度に形成した回
路基板およびその製造方法を提供することにあ
る。
An object of the present invention is to provide a circuit board in which a polyimide resin solder dam is easily formed with high precision and high density, and a method for manufacturing the same.
本発明の構成について説明すると、まず第１の
発明である回路基板は、回路部品を搭載する回路
基板において、基板本体上に、銅メツキ層の上に
パラジウムメツキ層が形成されてなるはんだ付け
用導体部と、感光性ポリイミド前駆体溶液で構成
されたポリイミド樹脂のソルダーダムとを有する
ことを特徴とするものである。
To explain the structure of the present invention, the first invention is a circuit board on which circuit components are mounted, and a palladium plating layer is formed on a copper plating layer on a board body, and is suitable for soldering. It is characterized by having a conductor portion and a polyimide resin solder dam made of a photosensitive polyimide precursor solution.
また、上記回路基板の製造方法である第２の発
明は、回路部品を搭載する回路基板の製造方法で
あつて、基板本体上にてはんだ付け用導体部のパ
ターンを成す銅メツキ層の上にパラジウムメツキ
を施こし、次いで、基板上に感光性ポリイミド前
駆体溶液を塗布し、その後乾燥工程、露光工程、
現像工程、熱硬化工程を経てポリイミド樹脂のソ
ルダーダムを形成することを特徴としている。 Further, the second invention, which is a method for manufacturing the above-mentioned circuit board, is a method for manufacturing a circuit board on which circuit components are mounted. Palladium plating is applied, and then a photosensitive polyimide precursor solution is applied onto the substrate, followed by a drying process, an exposure process,
It is characterized by forming a polyimide resin solder dam through a development process and a thermosetting process.
次に本願発明の実施例を第１図に基づいて説明
する。
Next, an embodiment of the present invention will be described based on FIG.
図中１は、基板本体となるセラミツク多層基板
である。ソルダーダムとしてポリイミドを用いる
ためには300℃以上の温度に耐える基板材料が必
要である。この点、セラミツク基板を用いれば問
題はない。なお、本図では省略しているが、この
セラミツク多層基板１の内層及び表面層に導体回
路が形成されていることはもちろんである。２は
銅メツキ層、３はパラジウムメツキ層であり、こ
れら両者によつてはんだ付け導体部が形成されて
いる。銅メツキ層２は、基板１の絶縁層上にて、
はんだ付け用導体部と共にその他必要な配線部の
パターンを成している。銅がsn／pb等のはんだ
付けに対してすぐれた特性を有していることは周
知のとおりである。この銅メツキ層２の上にはパ
ラジウムメツキが施こされ、これによつてパラジ
ウムメツキ層３が形成されている。 In the figure, numeral 1 indicates a ceramic multilayer substrate that serves as the main body of the substrate. In order to use polyimide as a solder dam, a substrate material that can withstand temperatures of 300°C or higher is required. In this respect, there is no problem if a ceramic substrate is used. Although not shown in this figure, it goes without saying that conductive circuits are formed on the inner and surface layers of the ceramic multilayer substrate 1. 2 is a copper plating layer, and 3 is a palladium plating layer, both of which form a soldering conductor portion. The copper plating layer 2 is on the insulating layer of the substrate 1,
Together with the soldering conductor part, it forms a pattern for other necessary wiring parts. It is well known that copper has excellent properties for soldering such as SN/PB. Palladium plating is applied on this copper plating layer 2, thereby forming a palladium plating layer 3.
そして、このように銅メツキ層２とパラジウム
メツキ層３が形成された基板１上には、感光性ポ
リイミド前駆体（プレポリマー）溶液で構成され
たポリイミド樹脂のソルダーダム４が形成されて
いる。このソルダーダム４の形成に際しては、ま
ず感光性ポリイミドワニスをスピンナなどによつ
て基板１上に塗布し、それからオープン中での乾
燥を行なう。その後、例えばフオトレジストをパ
ターン印刷して露光を行ない、それから専用現像
液で現像を行なう。このとき、導体部表面をパラ
ジウムとしていることにより、現像残りは発生し
なかつた。その後、熱処理してポリイミドによる
ソルダーダム４を形成する。感光性ポリイミドワ
ニスとしては、例えば東レ株式会社製のフオトニ
ースUR―3100がある。 A polyimide resin solder dam 4 made of a photosensitive polyimide precursor (prepolymer) solution is formed on the substrate 1 on which the copper plating layer 2 and the palladium plating layer 3 are formed in this way. In forming the solder dam 4, first, a photosensitive polyimide varnish is applied onto the substrate 1 using a spinner or the like, and then dried in an open state. Thereafter, for example, a pattern of photoresist is printed, exposed, and then developed with a special developer. At this time, since the surface of the conductor portion was made of palladium, no development residue was generated. Thereafter, a heat treatment is performed to form a solder dam 4 made of polyimide. As a photosensitive polyimide varnish, there is, for example, Fotonis UR-3100 manufactured by Toray Industries, Inc.
このようにして、ソルダーダム４が形成された
後に、はんだ付けが行われはんだ層５が形成され
る。このとき、導体部表面をパラジウムとしてい
ることにより、ソルダーダム４の剥離が発生せず
に良好なはんだ付け作業ができた。したがつて、
このパラジウムは、前述したようにポリイミドワ
ニスの現像残りをなくすこと、およびはんだねれ
性の改善、さらにポリイミドとの密着のためにき
わめて有効である。 After the solder dam 4 is formed in this manner, soldering is performed to form the solder layer 5. At this time, since the surface of the conductor part was made of palladium, the solder dam 4 did not peel off and a good soldering work was possible. Therefore,
As mentioned above, palladium is extremely effective in eliminating undeveloped polyimide varnish, improving solderability, and adhesion to polyimide.
ちなみに、基板の絶縁層の上に、はんだ付け用
導体部およびその他必要な配線部を、銅メツキで
形成したものと、銅メツキ上に金メツキを行なつ
て形成したものとをそれぞれ用意して、これら両
者の基板に対して前述と同様のポリイミドによる
ソルダーダム４を形成した場合、前者の基板には
現像残りが発生して良好なはんだ付け用導体部が
形成できない。この点、後者の基板には問題がな
い。しかし、この後者の基板は、はんだ付けの作
業中に、ソルダーダム４が導体部表面より剥離し
て、不良な部分が発生するという問題がある。 By the way, the soldering conductor part and other necessary wiring parts are formed on the insulating layer of the board with copper plating, and with gold plating on the copper plating. When a polyimide solder dam 4 similar to that described above is formed on both of these substrates, a good conductor portion for soldering cannot be formed on the former substrate due to residual development. In this respect, there is no problem with the latter substrate. However, this latter board has a problem in that the solder dam 4 peels off from the surface of the conductor part during the soldering operation, resulting in defective parts.
以上説明したように、本発明によれば、銅メツ
キ層の上にパラジウムメツキ層を形成してはんだ
付け用導体部を成し、そして感光性ポリイミド前
駆体溶液でポリイミド樹脂のソルダーダムを構成
するようにしたから、パラジウムとポリイミドと
の良好な密着が得られ、ポリイミド樹脂によるソ
ルダーダムを高精度、高密度に形成することがで
きる。しかも、感光性ポリイミド前駆体溶液の塗
布、乾燥、露光、現像、熱硬化の一連の工程によ
つて、ソルダーダムを容易に形成することができ
る。特に、感光性ポリイミド前駆体塗布膜の現像
は容易である。
As explained above, according to the present invention, a palladium plating layer is formed on a copper plating layer to form a soldering conductor part, and a polyimide resin solder dam is formed with a photosensitive polyimide precursor solution. Therefore, good adhesion between palladium and polyimide can be obtained, and a solder dam made of polyimide resin can be formed with high precision and high density. Moreover, a solder dam can be easily formed through a series of steps of applying a photosensitive polyimide precursor solution, drying, exposing, developing, and thermosetting. In particular, the development of a photosensitive polyimide precursor coating film is easy.
第１図は本発明の一実施例を示す回路基板の断
面図でる。
１…セラミツク層基板（基板本体）、２…銅メ
ツキ層、３…パラジウムメツキ層、４…ソルダー
ダム、５…はんだ層。
FIG. 1 is a sectional view of a circuit board showing one embodiment of the present invention. 1... Ceramic layer substrate (substrate body), 2... Copper plating layer, 3... Palladium plating layer, 4... Solder dam, 5... Solder layer.
Claims (1)
本体上に銅メツキ層の上にパラジウムメツキ層が
形成されてなるはんだ付け用導体部と、感光性ポ
リイミド前駆体溶液で構成されたポリイミド樹脂
のソルダーダムとを有することを特徴とする回路
基板。 ２ 回路部品を搭載する回路基板の製造方法であ
つて、基板本体にてはんだ付け用導体部のパター
ンを成す銅メツキ層の上にパラジウムメツキを施
こし、次いで、基板上に感光性ポリイミド前駆体
溶液を塗布し、その後乾燥工程、露光工程、現像
工程、熱硬化工程を経てポリイミド樹脂のソルダ
ーダムを形成することを特徴とする回路基板の製
造方法。[Scope of Claims] 1. A circuit board on which circuit components are mounted, which comprises a soldering conductor portion in which a palladium plating layer is formed on a copper plating layer on a board body, and a photosensitive polyimide precursor solution. A circuit board comprising a polyimide resin solder dam. 2. A method for manufacturing a circuit board on which circuit components are mounted, in which palladium plating is applied on the copper plating layer forming the pattern of the conductor part for soldering on the board body, and then a photosensitive polyimide precursor is applied on the board. A method for manufacturing a circuit board, comprising applying a solution, and then forming a polyimide resin solder dam through a drying process, an exposure process, a development process, and a thermosetting process.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14358184A JPS6123390A (en) | 1984-07-11 | 1984-07-11 | Circuit board and method of producing same |
| FR858510660A FR2567709B1 (en) | 1984-07-11 | 1985-07-11 | GLITTER ASSEMBLY INCLUDING A MULTI-LAYER WIRING SUBSTRATE |
| FR8615585A FR2590105A1 (en) | 1984-07-11 | 1986-11-07 | GLITTER ASSEMBLY COMPRISING A MULTILAYER WIRING SUBSTRATE |
| US07/115,565 US4840924A (en) | 1984-07-11 | 1987-10-29 | Method of fabricating a multichip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14358184A JPS6123390A (en) | 1984-07-11 | 1984-07-11 | Circuit board and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6123390A JPS6123390A (en) | 1986-01-31 |
| JPH0354873B2 true JPH0354873B2 (en) | 1991-08-21 |
Family
ID=15342061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14358184A Granted JPS6123390A (en) | 1984-07-11 | 1984-07-11 | Circuit board and method of producing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123390A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07115217B2 (en) * | 1986-08-25 | 1995-12-13 | カルソニック株式会社 | Piston rod manufacturing method |
| JPH03160786A (en) * | 1989-11-20 | 1991-07-10 | Fujitsu Ltd | Thin film printed wiring circuit board |
-
1984
- 1984-07-11 JP JP14358184A patent/JPS6123390A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123390A (en) | 1986-01-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |