JPH03160786A - Thin film printed wiring circuit board - Google Patents
Thin film printed wiring circuit boardInfo
- Publication number
- JPH03160786A JPH03160786A JP30104489A JP30104489A JPH03160786A JP H03160786 A JPH03160786 A JP H03160786A JP 30104489 A JP30104489 A JP 30104489A JP 30104489 A JP30104489 A JP 30104489A JP H03160786 A JPH03160786 A JP H03160786A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- printed wiring
- solder
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title abstract description 70
- 239000010410 layer Substances 0.000 claims abstract description 66
- 229910000679 solder Inorganic materials 0.000 claims abstract description 60
- 239000011241 protective layer Substances 0.000 claims abstract description 24
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000004642 Polyimide Substances 0.000 claims abstract description 13
- 229920001721 polyimide Polymers 0.000 claims abstract description 13
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 26
- 239000011651 chromium Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000007261 regionalization Effects 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 101100008048 Caenorhabditis elegans cut-4 gene Proteins 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 235000016623 Fragaria vesca Nutrition 0.000 description 1
- 240000009088 Fragaria x ananassa Species 0.000 description 1
- 235000011363 Fragaria x ananassa Nutrition 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
電子計算機等の電子機器に用いられる印刷配線回路基板
に関し、
高温に曝されてもはんだ流出の無い薄膜印刷配線回路基
板の提供を目的とし、
基板上に形成されたＣｕ薄膜からなる印刷配線パターン
と、Ｃｕ薄膜にＮｉとＡｕをめっきし形成されたはんだ
電極と、最上層に被着形或されたポリイミドからなる保
護層を有し、はんだを載せる部分を取り囲むようにはん
だ電極の周縁部が保護層で覆われるように構成する。[Detailed Description of the Invention] [Summary] Regarding printed wiring circuit boards used in electronic devices such as computers, the present invention aims to provide a thin film printed wiring circuit board that does not cause solder to flow out even when exposed to high temperatures. A printed wiring pattern made of a formed Cu thin film, a solder electrode formed by plating Ni and Au on the Cu thin film, and a protective layer made of polyimide deposited on the top layer, and a part on which solder is placed. The peripheral edge of the solder electrode is covered with a protective layer so as to surround the solder electrode.
本発明は電子計算機等の電子機器に用いられる印刷配線
回路基板に係り、特に電極からのはんだ流出を無くした
薄膜印刷配線回路基板に関する．近年、電子計算機等の
電子機器が大型化するに伴い高密度実装を図るため、半
導体集積回路やその他の回路部品が薄膜印刷配線回路基
板に実装されている．かかる薄膜印刷配線回路基板にお
いては熱による電極剥離を無くし、且つ部品のはんだ付
け時に隣接電極に盛られたはんだの溶融を防止するため
、部品のはんだ付けにインジュウム（Ｉｎ）と鉛（Ｐｂ
）を含み、低温（１２０℃程度）で溶融するいわゆるＩ
ｎはんだが用いられることがある。The present invention relates to a printed circuit board used in electronic devices such as computers, and more particularly to a thin film printed circuit board that eliminates solder leakage from electrodes. In recent years, as electronic devices such as computers have become larger, semiconductor integrated circuits and other circuit components have been mounted on thin-film printed wiring circuit boards in order to achieve high-density mounting. In such thin film printed wiring circuit boards, indium (In) and lead (Pb) are used to solder parts in order to eliminate electrode peeling due to heat and to prevent melting of solder applied to adjacent electrodes when soldering parts.
) and melts at low temperatures (about 120°C).
n solder is sometimes used.
しかしＩｎはんだは高温（融点より５０゜Ｃ程度高い温
度）に曝されると電極の周囲に流れ、例えばＣｕ薄膜か
らなる印刷配線パターンに固溶して断線を乗しる。或い
ははんだ付け強度が低下して部品が電極から離れる等の
障害を発生する。そこで高温に曝されてもはんだ流出の
無い薄膜印刷配線回路基板の実現が望まれている。However, when In solder is exposed to high temperatures (approximately 50° C. higher than its melting point), it flows around the electrodes, dissolves in a printed wiring pattern made of, for example, a Cu thin film, and causes wire breaks. Alternatively, the soldering strength decreases, causing problems such as parts separating from the electrodes. Therefore, it is desired to realize a thin film printed wiring circuit board that does not leak solder even when exposed to high temperatures.
第６図は従来の薄膜印刷配線回路基板を示す側断面図で
ある。FIG. 6 is a side sectional view showing a conventional thin film printed wiring circuit board.
従来の薄膜印刷配線回路基板は第６図（ａ）に示す如く
ガラスやセラミックからなる基板１上に、銅（Ｃｕ）薄
膜からなる少なくとも一層の印刷配線パターン２が形成
されており、ＣｕＦｉ膜にニッケル（Ｎｉ）と金（＾Ｕ
）をめっきすることによって、最上層の印刷配線パター
ン２にははんだ電極３が形成されている。そして部品実
装時には図示の如くはんだ電極３にはんだ４が盛られる
。As shown in FIG. 6(a), a conventional thin film printed wiring circuit board has at least one layer of printed wiring pattern 2 made of a copper (Cu) thin film formed on a substrate 1 made of glass or ceramic. Nickel (Ni) and gold (^U
), solder electrodes 3 are formed on the printed wiring pattern 2 of the uppermost layer. When mounting components, solder 4 is applied to the solder electrodes 3 as shown in the figure.
またはんだ電極３を除いて最上層の印刷配線パターン２
は、被着されたポリイミドからなる保護層５によって保
護されている。なお図中、６は基板ｌと印刷配線パター
ン２、或いは印刷配線パターン２と保護層５の密着力を
高めるため、印刷配線パターン２の両面に形成されたク
ロム（Ｃｒ）からなる密着層である。The printed wiring pattern 2 on the top layer except for the solder electrode 3
is protected by a protective layer 5 of deposited polyimide. In the figure, 6 is an adhesion layer made of chromium (Cr) formed on both sides of the printed wiring pattern 2 in order to increase the adhesion between the substrate l and the printed wiring pattern 2, or between the printed wiring pattern 2 and the protective layer 5. .
〔発明が解決しようとする課題］
しかし従来の薄膜印刷配線回路基板ははんだ電極と保護
層の間に隙間ができやすく、Ｉｎはんだを盛った後これ
を高記に曝すと第６図（１））に示す如く、はんだ電極
から流出したＩｎはんだがこの隙間に流入し、Ｉｎはん
だによって保護層が印刷配線パターンから剥離する。或
いはＩｎはんだがＣｕｔ４膜中に固溶して劣化せしめ印
刷配線パターンの断線を招く。[Problems to be Solved by the Invention] However, in conventional thin film printed wiring circuit boards, gaps tend to form between the solder electrodes and the protective layer. ), the In solder flowing out from the solder electrode flows into this gap, and the protective layer is peeled off from the printed wiring pattern by the In solder. Alternatively, In solder dissolves in the Cut4 film and deteriorates, leading to disconnection of the printed wiring pattern.
更にはんだ付け強度が低下し部品が電極から離れるとい
う問題があった。Furthermore, there was a problem that the soldering strength decreased and the parts separated from the electrodes.
本発明の目的は高温に曝されてもはんだ流出の餌い薄膜
印刷配線回路基板を提供することにある。An object of the present invention is to provide a thin film printed wiring circuit board that prevents solder from flowing out even when exposed to high temperatures.
第１図は本発明になる薄膜印刷配線回路基板を示す側断
面図である。なお全図を通し同じ対象物は同一記号で表
している。FIG. 1 is a side sectional view showing a thin film printed wiring circuit board according to the present invention. The same objects are represented by the same symbols throughout the figures.
上記課題は基板１上に形成されたＣｕ薄膜からなる印刷
配線パターン２と、Ｃｕｌｌ膜にＮｉとＡｕをめっきし
形戒されたはんだ電極３と、最上層に被着形成されたポ
リイミドからなる保護層５を有し、はんだ４を載せる部
分を取り囲むようにはんだ電極３の周縁部が、保護層５
で覆われてなる本発明の薄膜印刷配線回路基板によって
達威される。The above-mentioned problem consists of a printed wiring pattern 2 made of a Cu thin film formed on a substrate 1, a solder electrode 3 formed by plating Ni and Au on the Cull film, and a protection made of polyimide formed on the top layer. The peripheral edge of the solder electrode 3 has a protective layer 5 surrounding the part on which the solder 4 is placed.
This is achieved by the thin film printed wiring circuit board of the present invention which is covered with.
第１図において基板上に形成されたＣｕｌ膜からなる印
刷配線パターンと、Ｃｕｉ膜にＮｉとＡｕをめっきし形
成されたはんだ電極と、最上層に被着形戒されたポリイ
ミドからなる保護層を有し、はんだを載せる部分を取り
囲むようにはんだ電極の周縁部が、保護層で覆われてな
る本発明の薄膜印刷配線回路基板は、パターンずれやポ
リイミドの収縮があってもはんだ電極と保護層の間に隙
間ができず、高温に曝されてもはんだ流出の無い薄膜印
刷配線回路基板を実現することができる。Figure 1 shows a printed wiring pattern made of a Cu film formed on a substrate, a solder electrode formed by plating Ni and Au on the Cu film, and a protective layer made of polyimide deposited on the top layer. The thin film printed wiring circuit board of the present invention, in which the periphery of the solder electrode is covered with a protective layer so as to surround the part on which the solder is to be placed, will protect the solder electrode and the protective layer even if there is pattern displacement or shrinkage of the polyimide. It is possible to realize a thin film printed wiring circuit board with no gaps between the two and no solder flowing out even when exposed to high temperatures.
以下添付図により本発明の実施例について説明する。第
２図は本発明の一実施例を示す側断面図、第３図は実施
例の製造工程を示す側断面図、第４図は本発明の変形例
を示す側断面図、第５図は変形例の製造工程を示す側断
面図である。Embodiments of the present invention will be described below with reference to the accompanying drawings. Fig. 2 is a side sectional view showing an embodiment of the present invention, Fig. 3 is a side sectional view showing the manufacturing process of the embodiment, Fig. 4 is a side sectional view showing a modification of the invention, and Fig. 5 is a side sectional view showing a modification of the invention. It is a side sectional view showing the manufacturing process of a modification.
本発明になる薄膜印刷配線回路基板の実施例は第２図に
示す如く、基板１上に形成された少なくとも一層のＣｕ
薄膜からなる印刷配線パターン２を有し、最上層の印刷
配線パターン２にははんだ電極３が形成されている。As shown in FIG. 2, an embodiment of the thin film printed wiring circuit board according to the present invention includes at least one layer of Cu formed on a substrate 1.
It has a printed wiring pattern 2 made of a thin film, and a solder electrode 3 is formed on the printed wiring pattern 2 of the uppermost layer.
はんだ電極３はめっきにより形成されたＮｉｌ膜層３１
とＡｕ薄膜層３２からなり、はんだが盛られるＡｕ薄膜
層３２を取り囲むようにＮｔ薄膜層３１が露出している
。このＡｕｎｔ膜Ｊｉ３２を取り囲むように露出させた
Ｎｉ薄膜層３１は、ＡｕやＣｕに比べてはんだに対する
溶食速度が遅くはんだ流出防止に特に有効である。The solder electrode 3 is a Nil film layer 31 formed by plating.
and an Au thin film layer 32, and the Nt thin film layer 31 is exposed so as to surround the Au thin film layer 32 on which solder is applied. The Ni thin film layer 31 exposed so as to surround the Aunt film Ji32 has a slower corrosion rate for solder than Au or Cu, and is particularly effective in preventing solder from flowing out.
またＮｉ薄膜層３Ｉの露出部分と最上層の印刷配線パタ
ーン２は、被着されたポリイミドからなる保護層５によ
って保護されている。なお図中、６は基板１と印刷配線
パターン２、或いは印刷配線パターン２と保護層５の密
着力を高めるため、印刷配線パターン２の両面に形戒さ
れたＣｒからなる密着層である。Further, the exposed portion of the Ni thin film layer 3I and the uppermost printed wiring pattern 2 are protected by a protective layer 5 made of polyimide. In the figure, reference numeral 6 denotes an adhesion layer made of Cr formed on both sides of the printed wiring pattern 2 in order to enhance the adhesion between the substrate 1 and the printed wiring pattern 2, or between the printed wiring pattern 2 and the protective layer 5.
かかる薄膜印刷配線回路基板の製造工程を第３図により
説明する。なおこの製造工程は印刷配線パターンが一層
の場合について説明しており、二層以上の印刷配線パタ
ーンを有する薄膜印刷配線回路基板の場合は、最上層の
印刷配線パターンの形成にこの工程が適用される。The manufacturing process of such a thin film printed wiring circuit board will be explained with reference to FIG. Note that this manufacturing process is explained for the case where the printed wiring pattern is one layer, and in the case of a thin film printed wiring circuit board having two or more layers of printed wiring patterns, this process is applied to the formation of the top layer printed wiring pattern. Ru.
■ Ｃｕ薄膜生成工程
ガラスやセラ稟ツタからなる基板１上にＣｒとＣｕとＣ
ｒを交互にスパッタリングし、第３図（ａ）に示す如＜
Ｃｒからなる密着Ｎ６とＣｕ薄膜層２１を生或する。■ Cu thin film production process Cr, Cu and C are
sputtering alternately, and as shown in Fig. 3(a).
A close contact N6 made of Cr and a Cu thin film layer 21 are formed.
■ 第１のレジストパターン形戒工程
第３図（ｂ）に示す如くエッチングによりＣｒ膜を除去
すると共に、Ｃｕ薄膜層２１にＮｉめっきを施すための
第１のレジストパターン２２を被着する。(2) First resist pattern formation process As shown in FIG. 3(b), the Cr film is removed by etching, and a first resist pattern 22 for Ni plating is applied to the Cu thin film layer 21.
■ Ｎｉ薄膜層形或工程
エッチングによりＣｒ膜を除去しＣｕ薄膜！２１にＮｉ
めっきを施した後、レジストパターン２２を除去し第３
図（Ｃ）に示すＮｉｌ膜層３１を形或する。■ Remove the Cr film by etching the Ni thin film layer and create a Cu thin film! Ni to 21
After plating, the resist pattern 22 is removed and the third
A Nil film layer 31 shown in Figure (C) is formed.
■ 第２のレジストパターン形戒工程
ＮｉｆＮ膜層３ｌにＡｕめっきを施すための第２のレジ
ストパターン２３を第３図（ｄ）に示す如く被着する。(2) Second resist pattern formation process A second resist pattern 23 for applying Au plating to the NifN film layer 3l is deposited as shown in FIG. 3(d).
■ Ａｕ薄膜層形或工程
Ｎｉ薄膜層３１上にＡｕストライクめっきを施した後更
にＡｕめっきを施し、第２のレジストパターン２３を除
去することにより第３図（ｅ）に示すＡｕｌ膜層３２を
形或する。なおＡｕめっきに先立ってＮｉ薄膜層３１上
に施すＡｕストライクめっきは、第２のレジストパター
ン形戒時２Ｎｉ薄膜層３１の表面が酸化し、Ａｕ薄膜層
が剥離しやすくなるのを防止するためのものである。■ Au thin film layer type or process After applying Au strike plating on the Ni thin film layer 31, further Au plating is applied and the second resist pattern 23 is removed to form the Au film layer 32 shown in FIG. 3(e). take shape Note that the Au strike plating applied on the Ni thin film layer 31 prior to the Au plating is used to prevent the surface of the Ni thin film layer 31 from being oxidized when the second resist pattern is formed and the Au thin film layer from becoming easily peeled off. It is something.
■ 第３のレジストパターン形成工程
印刷配線パターンを形或するための第３のレジストパタ
ーン２４を、第３図（ｆ）に示す如く薄膜印刷配線回路
基板全体に被着する。(2) Third resist pattern forming step A third resist pattern 24 for forming a printed wiring pattern is applied over the entire thin film printed wiring circuit board as shown in FIG. 3(f).
■ 印刷配線パターン形戒工程
余分な密着層６とＣｕ薄膜層２ｌをエッチングにより除
去した後、第３のレジストパターン２４を除去し第３図
（８）に示す印刷配線パターン２を形戒する。(2) Printed wiring pattern forming process After removing the excess adhesive layer 6 and Cu thin film layer 2l by etching, the third resist pattern 24 is removed to form the printed wiring pattern 2 shown in FIG. 3(8).
■ 保護層形或工程
＾Ｕ薄膜層３２の上面を除いた薄膜印刷配線回路基板全
体に、第３図中）に示す如くポリイミドからなる保護層
５を被着する。(2) Protective Layer Form A protective layer 5 made of polyimide is applied to the entire thin film printed wiring circuit board except for the upper surface of the thin film layer 32, as shown in FIG.
既に述べたようにＡｕ薄膜層を取り囲むように露出させ
たＮｉ薄膜層は、ＡｕやＣｕに比べてはんだに対する溶
食速度が遅くはんだ流出防止に特に有効である。第４図
に示す本発明の変形例はＮｉ薄膜層のかかる性質に着眼
したもので、基板ｌ上に形或された少なくとも一層のＣ
ｕ薄膜からなる印刷配線パターン２を有し、最上層の印
刷配線パターン２にははんだ電極３が形成されている。As already mentioned, the Ni thin film layer exposed so as to surround the Au thin film layer has a slower corrosion rate for solder than Au or Cu, and is particularly effective in preventing solder from flowing out. A modification of the present invention shown in FIG. 4 focuses on such properties of the Ni thin film layer, and includes at least one layer of C
It has a printed wiring pattern 2 made of a U thin film, and a solder electrode 3 is formed on the printed wiring pattern 2 of the uppermost layer.
はんだ電極３はめっきにより形成されたＮｉ薄膜層３ｌ
とＡｕ薄膜層３２からなり、はんだが盛られるＡｕｔｌ
膜層３２を取り囲むようにＮｉ薄膜層３１が露出してい
る。The solder electrode 3 is a Ni thin film layer 3l formed by plating.
and Au thin film layer 32, on which solder is applied.
The Ni thin film layer 31 is exposed so as to surround the film layer 32.
ただし、第１図および第２図に示す薄膜印刷配線回路基
板とは異なり、最上層に被着形戒されたポリイミドから
なる保護層５が省略されており、Ａｕ薄膜層３２に盛ら
れたはんだ４の流出はＮｉ薄膜層３ｌの露出部によって
阻止されている。なお図中、６は基板ｌと印刷配線パタ
ーン２、或いは印刷配線パターン２と保護層５の密着力
を高めるため、印刷配線パターン２の両面に形成された
Ｃｒからなる密着層である。However, unlike the thin film printed wiring circuit board shown in FIGS. 1 and 2, the protective layer 5 made of polyimide deposited on the top layer is omitted, and the solder applied to the Au thin film layer 32 is omitted. 4 is prevented from flowing out by the exposed portion of the Ni thin film layer 3l. In the figure, reference numeral 6 denotes an adhesion layer made of Cr formed on both sides of the printed wiring pattern 2 in order to increase the adhesion between the substrate l and the printed wiring pattern 2, or between the printed wiring pattern 2 and the protective layer 5.
かかる変形例を製造するための工程を第５図により説明
する。The process for manufacturing such a modified example will be explained with reference to FIG.
■ 第１のレジストパターン形戒工程
ガラスやセラミックからなる基板ｌに少なくとも一層の
導体パターンが形戒されており、Ｃｕ薄膜１１２１から
なる導体パターンはＣｒ膜からなる密着層６によって挟
まれている。かかる導体パターンの上に第５図（ａ）に
示す如く第１のレジストパターン２２を被着する。(2) First resist pattern formation process At least one conductor pattern is formed on the substrate l made of glass or ceramic, and the conductor pattern made of the Cu thin film 1121 is sandwiched between the adhesive layers 6 made of the Cr film. A first resist pattern 22 is deposited on the conductor pattern as shown in FIG. 5(a).
■ Ｎｉ薄膜層形戒工程
エッチングによってＣｒ膜を除去した後ＣｕＦｌ膜層２
ｌにＮｉめっきを施し、第５図（ｂ）に示す如＜Ｎｉ薄
膜層３１からなるはんだ電極を形戒する．■ 第２のレ
ジストパターン形戒工程
第５図（Ｃ）に示す如＜Ｎｉ薄膜層３１にＡｕめっきを
施すための第２のレジストパターン２３を被着する。■ After removing the Cr film by etching the Ni thin film layer, the CuFl film layer 2 is removed.
1 is plated with Ni, and a solder electrode consisting of a Ni thin film layer 31 is formed as shown in FIG. 5(b). (2) Second resist pattern formation step As shown in FIG. 5(C), a second resist pattern 23 for applying Au plating to the Ni thin film layer 31 is applied.
■ Ａｕ薄膜層形戒工程
Ｎｉ薄膜層３１上にＡｕストライクめっきを施した後更
にＡｕめっきを施し、第５図（ｄ）に示すはんだ濡れ性
のよいＡｕ薄膜層３２をはんだ電極に形成する。(2) Au thin film layer formation process After Au strike plating is applied to the Ni thin film layer 31, further Au plating is applied to form an Au thin film layer 32 with good solder wettability as shown in FIG. 5(d) on the solder electrode.
■ レジストパターン剥離工程
第５図（ｅ）に示す如く第１のレジストパターン２２お
よび第２のレジストパターン２３を剥離する。(2) Resist pattern peeling process As shown in FIG. 5(e), the first resist pattern 22 and the second resist pattern 23 are peeled off.
このように基板上に形成されたＣｕ薄膜からなる印刷配
線パターンと、Ｃｕ薄膜にＮｉとＡｕをめっきし形成さ
れたはんだ電極と、最上層に被着形戒されたポリイミド
からなる保護層を有し、はんだを載せる部分を取り囲む
ようにはんだ電極の周縁部が、保護層で覆われてなる本
発明の薄膜印刷配線回路基板は、パターンずれやポリイ
ミドの収縮があつてもはんだ電極と保護層の間に隙間が
できず、高温に曝されてもはんだ流出の無い薄膜印刷配
線回路基板を実現することができる。It has a printed wiring pattern made of a Cu thin film formed on the substrate in this way, a solder electrode formed by plating the Cu thin film with Ni and Au, and a protective layer made of polyimide adhered to the top layer. However, in the thin film printed wiring circuit board of the present invention, in which the peripheral edge of the solder electrode is covered with a protective layer so as to surround the part on which the solder is to be placed, the solder electrode and the protective layer can be easily bonded even if the pattern is misaligned or the polyimide shrinks. It is possible to realize a thin film printed wiring circuit board with no gaps between the two and no solder flowing out even when exposed to high temperatures.
上述の如く本発明によれば高温に曝されてもはんだ流出
の無い薄膜印刷配線回路基板を提供することができる。As described above, according to the present invention, it is possible to provide a thin film printed wiring circuit board that does not cause solder leakage even when exposed to high temperatures.
４4
第１図は本発明になる薄膜印刷配線回路基板を示す側断
面図、
第２図は本発明の一実施例を示す側断面図、第３図は製
造工程を示す側断面図、
第４図は本発明の変形例を示す側断面図、第５図は変形
例の製造工程を示す側断面図、第６図は従来の薄膜印刷
配線回路基板を示す側断面図、
である。図において
１は基板、 ２は印刷配線パターン、３ははん
だ電極、
５は保護層、
２１はＣｕ薄膜層、
３１はＮｉ薄膜層、
をそれぞれ表す。
４ははんだ、
６は密着層、
２２．２３．２４はレジス
３２はＡｕ薄膜層、
トパターン、
（＆）
（１））
従来の清朕Ｅ！・Ｉ！己晃回路碁棲１示１制断面図第６
口
製苺Ｌ程を示Ｔ狽・断面（２）
．ｐ３［２ｌ
第
４
図Fig. 1 is a side sectional view showing a thin film printed circuit board according to the present invention, Fig. 2 is a side sectional view showing an embodiment of the invention, Fig. 3 is a side sectional view showing the manufacturing process, and Fig. 4. 5 is a side sectional view showing a modification of the present invention, FIG. 5 is a side sectional view showing the manufacturing process of the modification, and FIG. 6 is a side sectional view showing a conventional thin film printed wiring circuit board. In the figure, 1 is a substrate, 2 is a printed wiring pattern, 3 is a solder electrode, 5 is a protective layer, 21 is a Cu thin film layer, and 31 is a Ni thin film layer. 4 is solder, 6 is adhesive layer, 22, 23, 24 is resist 32 is Au thin film layer, top pattern, (&) (1)) Conventional clean E!・I! Kokoro Circuit Go Sei 1-1 Control Sectional Diagram No. 6
Cross-section (2) showing the size of the strawberry made in the mouth. p3 [2l Fig. 4
Claims (1)
配線パターン（２）と、該Ｃｕ薄膜にニッケル（Ｎｉ）
と金（Ａｕ）をめっきし形成されたはんだ電極（３）と
、最上層に被着形成されたポリイミドからなる保護層（
５）を有し、 はんだ（４）を載せる部分を取り囲むように該はんだ電
極（３）の周縁部が、該保護層（５）で覆われてなるこ
とを特徴とする薄膜印刷配線回路基板。[Claims] A printed wiring pattern (2) made of a thin copper (Cu) film formed on a substrate (1), and a printed wiring pattern (2) made of a thin copper (Cu) film formed on a substrate (1), and a printed wiring pattern (2) made of a thin copper (Cu) film formed on a substrate (1);
A solder electrode (3) formed by plating with gold (Au) and a protective layer made of polyimide formed on the top layer (
5), wherein the peripheral edge of the solder electrode (3) is covered with the protective layer (5) so as to surround the portion on which the solder (4) is placed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30104489A JPH03160786A (en) | 1989-11-20 | 1989-11-20 | Thin film printed wiring circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30104489A JPH03160786A (en) | 1989-11-20 | 1989-11-20 | Thin film printed wiring circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03160786A true JPH03160786A (en) | 1991-07-10 |
Family
ID=17892185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30104489A Pending JPH03160786A (en) | 1989-11-20 | 1989-11-20 | Thin film printed wiring circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03160786A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6123390A (en) * | 1984-07-11 | 1986-01-31 | 日本電気株式会社 | Circuit board and method of producing same |
| JPS63114081A (en) * | 1986-07-22 | 1988-05-18 | セイコーインスツルメンツ株式会社 | Construction of wire pattern |
| JPS6355574B2 (en) * | 1984-04-26 | 1988-11-02 | Tadanobu Izumi |
-
1989
- 1989-11-20 JP JP30104489A patent/JPH03160786A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6355574B2 (en) * | 1984-04-26 | 1988-11-02 | Tadanobu Izumi | |
| JPS6123390A (en) * | 1984-07-11 | 1986-01-31 | 日本電気株式会社 | Circuit board and method of producing same |
| JPS63114081A (en) * | 1986-07-22 | 1988-05-18 | セイコーインスツルメンツ株式会社 | Construction of wire pattern |
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