JP3430916B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects an integrated circuit portion of a semiconductor, secures electrical connection between an external device and a semiconductor element, and has the highest density. The present invention relates to a semiconductor device capable of being mounted and a method of manufacturing the same. The semiconductor device of the present invention facilitates miniaturization of information communication equipment, office electronic equipment, and the like. 2. Description of the Related Art In recent years, a semiconductor device and a method of manufacturing the same have been downsized and increased in density as electronic devices have become smaller and more sophisticated.
Higher speed is required, and for example, C4 (Con
controlled Collapse Chip Con
A mounting technique using so-called flip chip bonding, such as connection, has been developed. Hereinafter, a conventional semiconductor device called C4 and a method of manufacturing the same will be described with reference to sectional views. FIG. 4 is a sectional view of a semiconductor device using a conventional mounting technique called C4. In FIG. 4, 1 is a semiconductor element, 2 is a semiconductor element electrode, 3 is a metal layer, and 4 is a protruding electrode. [0005] As shown in FIG.
The structure is such that a metal layer 3 is formed on a semiconductor element electrode 2 on a semiconductor element 1 and a bump electrode 4 is formed on the metal layer. Next, a conventional method for manufacturing a semiconductor device will be described with reference to the sectional view of FIG. First, a plurality of semiconductor elements 1 are formed on a semiconductor wafer (not shown), and a plurality of semiconductor element electrodes 2 are formed on each semiconductor element 1. Then, the metal layer 3 is formed on the entire surface of the semiconductor wafer by a sputtering method. Next, a plating resist is applied, and a position corresponding to the semiconductor element electrode 2 is opened by a photographic method. Next, a metal such as Sn (tin) and Pb (lead) is formed on the metal layer 3 at the opening position by an electrolytic plating method. After removing the plating resist, the metal layer 3 is removed by etching using the plating metal as a resist. Next, a flux is applied to the entire surface of the semiconductor wafer and reflowed to form the protruding electrodes 4. A conventional semiconductor device is manufactured by the above-described method. However, in the conventional semiconductor device, when the semiconductor device is mounted on a resin circuit board, the coefficient of linear thermal expansion of the resin circuit board and the semiconductor device with respect to the projecting electrode portion is reduced. Since a thermal stress occurs due to the mismatch, a sealing resin has to be injected into a gap between the resin circuit board and the semiconductor device to reduce the thermal stress applied to the protruding electrode portion. In this case, there is a problem that the gap between the semiconductor device and the resin circuit board is narrow, it is very difficult to inject the sealing resin, and the individual semiconductor elements are individually sealed, so that the productivity is poor. Was. After resin sealing,
If a failure or defect is found in the semiconductor device, it is difficult to remove the defective or defective semiconductor device from the resin circuit board because the sealing resin and the resin circuit board are tightly adhered. Even so, the resin circuit board is damaged, so that it is impossible to remount the semiconductor device on the resin circuit board, and there are problems in productivity and production cost. SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and focuses on the productivity of a semiconductor device, enables repair, and provides an insulating resin layer on a semiconductor element to provide a hot wire between the semiconductor element and a resin circuit board. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can alleviate thermal stress due to mismatch of expansion coefficients. In the manufacturing method, a step of forming a metal wiring layer extending from an electrode of the semiconductor element on the semiconductor element, and forming an insulating resin layer on the semiconductor element and the metal wiring layer Forming, forming an opening in the insulating resin layer to expose a part of the metal wiring layer, and forming a metal layer connecting the exposed metal wiring layer and the surface of the insulating resin layer. A method of manufacturing a semiconductor device, comprising: a step of forming a projecting resin on the opening; and a step of forming a metal coat for electrically connecting a surface of the projecting resin to the metal layer . With the above configuration, the semiconductor device of the present invention has
Since the insulating resin layer having a low elastic modulus is provided, when the semiconductor device is mounted on the resin circuit board, it is possible to reduce the thermal stress applied to the protruding electrode portion due to the mismatch between the linear expansion coefficients of the semiconductor device and the resin circuit board. . Therefore, after the semiconductor device is mounted on the resin circuit board as in the related art, a sealing resin injection step is not required. In addition, since a sealing resin is not used as in the related art, when a defect or defect is found in a semiconductor device, the solder is melted by heating to melt the connection portion.
Since the semiconductor device can be easily removed from the resin circuit board, it is advantageous in terms of productivity and production cost. In addition, since the resin projection is formed of a low elastic modulus material to constitute the projection electrode, when the semiconductor device is mounted on the resin circuit board, the projection electrode is formed due to the mismatch of the coefficient of linear thermal expansion between the semiconductor device and the resin circuit board. The thermal stress applied to the portion can be reduced, and the reliability of board mounting can be improved. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, in the semiconductor device of the present embodiment, a metal wiring layer 7 extending from a semiconductor element electrode 6 on the semiconductor element 5 is provided on the semiconductor element 5, and an insulating resin is provided on the semiconductor element 5. A layer 8 is provided, and a metal layer 9 for electrically connecting the surface of the insulating resin layer 8 to the metal wiring layer 7 is provided. Then, a projection resin 10 is provided as a projection member on the metal layer 9, and a metal coat 11 for electrically connecting the projection resin 10 and the metal layer 9 is formed. That is, in the semiconductor device of this embodiment,
For external connection from the semiconductor element electrode 6 on the semiconductor element 5, wiring is routed by the metal wiring layer 7 and the metal layer 9, and the semiconductor element electrode 6 is formed by the insulating resin layer 8.
The metal wiring layer 7 is protected. In order to form a bump electrode, a bump resin 10 is formed on the metal layer 9, and a metal coat 11 is formed on the surface and the underlying metal layer 9, and the bump resin has substantially conductivity. In this case, a projection electrode (external electrode) is formed. Further, in the semiconductor device of this embodiment, the cross-sectional shape of the opening of the insulating resin layer 8 provided with the protruding resin 10 depends on the formation of the metal layer 9 formed on the surface thereof and the metal layer after the formation. In consideration of the reliability of the semiconductor device and the reliability of the connection between the external electrodes of the semiconductor device and the substrate when the substrate is mounted as a semiconductor device, the semiconductor device is formed to have a tapered cross section. In the present embodiment, the metal wiring layer 7 extending from the semiconductor element electrode 6 has a two-layer structure using Ti (titanium) as an adhesion metal and Cu (copper) as a conductor metal. In addition, Ti (titanium), C
r (chromium), TiW (titanium / tungsten), Cu
(Copper), Ni (nickel), Au (gold), Pd (palladium), Ag (silver), or the like, or a combination of the respective metals may be used. Hereinafter, a method of manufacturing the semiconductor device having the above-described structure will be described with reference to FIG. FIG. 2A shows a semiconductor wafer 12 on which individual semiconductor elements are formed, on which semiconductor element electrodes 6 are formed. Next, as shown in FIG. 2B, a metal layer is formed on the entire surface of the semiconductor wafer 12 by a vacuum evaporation method, a sputtering method, a CVD method, an electroless plating method or an electrolytic plating method, and the etching resist is masked. The metal wiring layer 7 extending from the semiconductor element electrode 6 is formed by etching the metal layer. Here, as an example of the metal wiring layer 7, a two-layer structure using Ti (titanium) as an adhesion metal and Cu (copper) as a conductor metal was used. As a metal material, T
i (titanium), Cr (chromium), TiW (titanium / tungsten), Cu (copper), Ni (nickel), Au
(Gold), Pd (palladium), Ag (silver) or the like may be used, or a combination of the respective metals may be used. Next, as shown in FIG. 2C, an insulating resin layer 8 is formed such that a part of the metal wiring layer 7 is exposed and the shape of the exposed portion (opening) is tapered. In the present embodiment, as an example of the formation of the insulating resin layer 8, a part of the metal wiring layer 7 is exposed by using a photosensitive polyimide and patterning the insulating resin layer 8 using a photographic method. As an insulating material of the insulating resin layer 8, an epoxy resin or the like may be used, but a low elastic modulus (3000 kg / mm ² or less)
It is preferable that the elastic modulus be in a range that can reduce the thermal stress applied to the protruding electrode portion. In addition, as a forming method, a part of the metal wiring layer 7 may be exposed by using an etching method, a sand blast method, a plasma method, or the like. The thickness of the insulating resin layer 8 is
For this purpose, it is desirable that the thickness be 10 [μm] or more. Next, as shown in FIG. 2D, a metal layer is formed on the entire surface of the semiconductor wafer 12 by a vacuum deposition method, a sputtering method, a CVD method, an electroless plating method, or an electrolytic plating method, and an etching resist is formed. By etching the metal layer as a mask, a metal layer 9 for electrically connecting the surface of the insulating resin layer 8 and the metal wiring layer 7 is formed. Here, as an example of the metal layer 9, Ti (titanium) is made of an adhesion metal,
A two-layer structure using Cu (copper) as a conductive metal was used. As the metal material, Ti (titanium), Cr (chromium), Ti
W (titanium / tungsten), Cu (copper), Ni (nickel), Au (gold), Pd (palladium), Ag (silver)
Etc. may be used, or a combination of each metal may be used. Further, since the shape of the opening of the insulating resin, that is, the portion of the insulating resin layer 8 where the underlying metal wiring layer 7 is exposed is tapered, it is possible to form the metal layer 9 with a uniform thickness. it can. Next, as shown in FIG. 2E, a projection resin 10 is formed on the metal layer 9 in the opening of the insulating resin layer 8 by a printing method. Here, as an example of the projection resin 10 as the projection member, a polyimide resin was used. Also, an epoxy resin or the like may be used as a material of the projection resin 10,
The projection resin 10 may be formed by using an etching method, a sand blast method, a plasma method, or the like. Note that the position where the projecting resin 10 is formed does not necessarily need to be at the opening of the insulating resin layer 8, but may be on the metal layer 9. Next, as shown in FIG. 2F, a metal layer is formed on the entire surface of the semiconductor wafer 12 by a vacuum deposition method, a sputtering method, a CVD method, an electroless plating method, or an electrolytic plating method, and an etching resist is formed. By etching the metal layer as a mask, a metal coat 11 for electrically connecting the surface of the projection resin 10 and the metal layer 9 is partially formed. The formation of the metal coat 11 is for using the protruding resin 10 as an external electrode, and is electrically connected to the semiconductor element electrode 6 via the metal layer 9 and the metal wiring layer 7.
Here, an example of the metal coat 11 is Ti (titanium).
Was used as a contact metal and a two-layer structure using Cu (copper) as a conductor metal was used. As the metal material, Ti (titanium), Cr (chromium), TiW (titanium / tungsten), Cu
(Copper), Ni (nickel), Au (gold), Pd (palladium), Ag (silver), or the like, or a combination of the respective metals may be used. In the present embodiment, the projecting resin 10 is used as a member constituting the projecting electrode. However, instead of the projecting resin, a metal ball having conductivity itself may be used, or the projection may be formed by metal plating. I do not care. Next, as shown in FIG. 2 (g), the semiconductor wafer 12 is divided into individual semiconductor elements along a scribe line (not shown) formed on the semiconductor wafer 12 by a dicing saw. Divide into semiconductor elements. By dividing, the metal wiring layer 7 extending from the semiconductor element electrode 6 on the semiconductor element 5 as shown in FIG.
Is provided on the metal wiring layer 7, and an insulating resin layer 8, a metal layer 9 electrically connected to the surfaces of the metal wiring layer 7 and the surface of the insulating resin layer 8 are provided. Resin 1
0 is formed, and a semiconductor device in which a metal coat 11 in which the surface of the protruding resin 10 is electrically connected to the metal layer 9 is formed. In this embodiment, the insulating resin layer 8 having a low elastic modulus is used.
When a semiconductor device is mounted on a resin circuit board, a protrusion electrode portion (protrusion resin 10 + metal coat 1) due to a mismatch in the coefficient of linear thermal expansion between the semiconductor device and the resin circuit board is provided.
Since the thermal stress applied to 1) can be reduced,
After mounting the semiconductor device on the resin circuit board as in the related art, a sealing resin injection step is not required. In addition, since a sealing resin is not used, if a defect or defect is found in the semiconductor device mounted on the board, the connection portion is melted by heating to easily remove the semiconductor device from the resin circuit board. Since it can be removed, it is advantageous in terms of productivity and production cost. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view illustrating the semiconductor device according to the present embodiment. As shown in FIG. 3, the semiconductor device of the present embodiment is provided with a metal wiring layer 15 extending from a semiconductor element electrode 14 on a semiconductor element 13, and an insulating resin layer 16 having a projection structure on the semiconductor element. A metal layer 17 that is provided and electrically connects the protrusion 16a of the insulating resin layer 16 and the metal wiring layer 15 is formed. Further, the protrusion 1 formed by the insulating resin layer 16
The shape of 6a depends on the formation of the metal layer 17 formed on the surface thereof, the reliability of the formed metal layer 17, and the reliability of the connection between the external electrode of the semiconductor device and the substrate when the semiconductor device is mounted on the substrate. In consideration of the characteristics, the cross-sectional shape is formed in a tapered shape. Hereinafter, a method of manufacturing the semiconductor device having the above-described structure will be described. As in the first embodiment, a vacuum evaporation method, a sputtering method,
A metal layer is formed on the entire surface of a semiconductor wafer by a method, electroless plating or electrolytic plating, and the metal layer is etched using an etching resist as a mask to form a metal wiring layer 15 extending from the semiconductor element electrode 14. Here, as an example of the metal wiring layer 15, a two-layer structure in which Ti (titanium) is a close contact metal and Cu (copper) is a conductive metal is used. As the metal material, Ti (titanium), Cr (chromium), TiW (titanium / tungsten), Cu (copper),
Ni (nickel), Au (gold), Pd (palladium),
Ag (silver) or the like may be used, or a combination of each metal may be used. Next, an insulating resin layer 16 in which a part of the metal wiring layer 15 is exposed and in which a projection 16a is provided is formed. In the present embodiment, as the formation of the insulating resin layer 16, a photosensitive polyimide was used, the projection 16 a was formed using a photographic method, and the photographic method was repeated again to expose a part of the metal wiring layer 15. As a material for forming the insulating resin layer 16, an epoxy resin or the like may be used.
0 kg / mm ² or less). As a forming method, the protrusion 16a and a part of the metal wiring layer 15 may be exposed by using an etching method, a sand blast method, a plasma method, or the like. Note that the thickness of the insulating resin layer 16 is desirably 10 [μm] or more. Next, vacuum deposition, sputtering, CVD
A metal layer is formed on the entire surface of a semiconductor wafer by a plating method, an electroless plating method or an electrolytic plating method, and the metal layer is etched using an etching resist as a mask to extend from the semiconductor element electrode 14 to the protrusion 16 a of the insulating resin layer 16. The formed metal wiring layer 15 is formed. Here, as an example of the metal wiring layer 15, Ti (titanium) is used as an adhesion metal, and Cu (copper) is used.
Was used as a conductive metal. As the metal material, Ti (titanium), Cr (chromium), TiW (titanium / tungsten), Cu (copper), Ni (nickel), A
u (gold), Pd (palladium), Ag (silver), or the like may be used, or a combination of respective metals may be used. Next, as the division of individual semiconductor elements on the semiconductor wafer, the semiconductor elements are individually divided by dicing saws along scribe lines formed on the semiconductor wafer, and the semiconductor elements are extended from the semiconductor element electrodes 14 on the semiconductor elements 13. A metal wiring layer 15 is provided, and an insulating resin layer 16 having a projection on the metal wiring layer 15 and a metal layer 17 extending from the metal wiring layer 15 to the projection of the insulating resin layer 16 are formed. A semiconductor device is formed. As described above, in the semiconductor device shown in the embodiment of the present invention, since the insulating resin layer 8 is provided in the first embodiment, when the semiconductor device is mounted on the resin circuit board, the semiconductor device and the resin circuit Protrusion electrode part (protrusion resin 10 + metal coat 11) due to mismatch of coefficient of linear thermal expansion with substrate
Can be reduced, and the reliability of the connection of the substrate mounting can be improved. In the second embodiment, since the protruding electrode itself is formed of a protruding portion made of an insulating resin, when the semiconductor device is mounted on a resin circuit board, the protruding electrode due to a mismatch in the coefficient of linear thermal expansion between the semiconductor device and the resin circuit board. The thermal stress applied to the portion (projection 16a + metal layer 17) can be reduced, and the reliability of the connection of the substrate mounting can be improved. In the first embodiment and the second embodiment, the structure of the protruding electrode is different from that of the one in which the protruding resin is formed separately and the one in which the protruding resin is integrally formed of insulating resin. Although there is a difference in the method of construction, the aim is to provide an insulating resin layer with a low elastic modulus and mount the semiconductor device on a resin circuit board, because the coefficient of linear thermal expansion between the semiconductor device and the resin circuit board does not match. The thermal stress applied to the protruding electrode portion can be reduced. As described above, according to the present invention, since the insulating resin layer having a low elastic modulus is provided, when the semiconductor device is mounted on the resin circuit board, the semiconductor device and the resin circuit board are not connected to each other. The thermal stress applied to the protruding electrode portion due to the mismatch of the linear thermal expansion coefficients can be reduced. Therefore, after the semiconductor device is mounted on the resin circuit board as in the related art, a sealing resin injection step is not required. In addition, since no sealing resin is used, if a defect or defect is found in the semiconductor element, heat treatment is performed to melt the solder at the connection portion and easily remove the semiconductor element from the resin circuit board. Because you can
It is also advantageous in terms of productivity and production cost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a conventional semiconductor device. Metal wiring layer 8 Insulating resin layer 9 Metal layer 10 Protrusion resin 11 Metal coat 12 Semiconductor wafer 13 Semiconductor element 14 Semiconductor element electrode 15 Metal wiring layer 16 Insulating resin layer 16a Projection 17 Metal layer

Continuation of the front page (72) Inventor Takahiro Kumakawa 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Inside Matsushita Electronics Corporation (56) References JP-A-8-222571 (JP, A) JP-A-4-188625 JP-A-6-326108 (JP, A) JP-A-2-272737 (JP, A) JP-A-1-289272 (JP, A) JP-A-1-196856 (JP, A) Kaihei 5-251455 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/60 H01L 21/60 311

Claims (1)

(57) Claims 1. A step of forming a metal wiring layer extending from an electrode of the semiconductor element on the semiconductor element, and forming an insulating resin layer on the semiconductor element and the metal wiring layer. Forming, forming an opening in the insulating resin layer to expose a part of the metal wiring layer, and forming a metal layer connecting the exposed metal wiring layer and the surface of the insulating resin layer. A method of forming a projecting resin on the opening, and a step of forming a metal coat for electrically connecting a surface of the projecting resin to the metal layer. .