JP3524441B2 - Wiring formation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming technique , and more particularly to copper (C) which is relatively inferior in environmental resistance as a wiring material.
The present invention relates to a wiring forming method that is useful for eliminating the inconvenience that occurs when a material such as u) or silver (Ag) is used.

[0002]

2. Description of the Related Art In recent years, wiring has become multi-layered and finer due to higher integration and higher speed of LSI. Especially in logic devices, it is essential to reduce the minimum wiring pitch to match the gate length in order to achieve high-performance transistor characteristics, and a wiring structure that can withstand use conditions at high current densities is required. To be done. When the wiring pitch is reduced, the signal delay due to the inter-wiring capacitance and the wiring resistance, which has not been a serious problem in the past, cannot be ignored. In order to avoid this, it is necessary to use a wiring material having a low resistivity and an interlayer insulating film having a low dielectric constant.

Aluminum (Al) has been conventionally used as the wiring material, but recently, Cu has been used which can realize a low wiring resistance with the same wiring cross-sectional area as compared with Al. Since Cu can reduce the thickness of the wiring with the same wiring pitch and the same wiring resistance as Al, as a result, the inter-wiring capacitance can be reduced. In particular, in a semiconductor device having a chip size package (CSP) structure that has been developed to meet the recent demands for miniaturization and high density of the semiconductor device, each semiconductor element formed on a wafer It is necessary to perform rewiring for connecting the electrode pad (the part which is finally separated as an individual semiconductor chip) to the outside of the package with the wafer through an insulating layer such as a polyimide layer. As the wiring material used for the rewiring, Cu is mainly used from the viewpoint of excellent electrical characteristics.

In addition to the advantage that the electrical characteristics are also excellent, the use of Ag as a wiring material is also considered from the viewpoint that the conductivity can be further enhanced by the skin effect at higher frequencies. ing.

[0005]

As described above, in the conventional semiconductor device having the CSP structure, the wiring material having excellent electrical characteristics is used for the rewiring, but in general, Cu or Ag is used.
As described above, a material having excellent electrical characteristics may cause contamination or migration due to diffusion in an environment of high temperature and high humidity.

For example, metal atoms penetrate into the adjacent insulating layer to deteriorate its insulating property, or metal atoms move with electron momentum due to high current density in the wiring layer to move, and Inconveniences such as disconnection and short circuit due to deformation are expected. That is, it is not appropriate to use a material having excellent electrical characteristics such as Cu or Ag as the wiring material as it is from the viewpoint of the environment surrounding the wiring.

Such a problem is not peculiar to a semiconductor device having a CSP structure, and is generally a structure having wirings formed of Cu, Ag, etc., which have relatively poor environment resistance, For example, a wiring board such as a build-up wiring board can similarly occur. In addition, if such contamination or migration occurs, the reliability of a wiring board such as a CSP-structured semiconductor device or a build-up wiring board that incorporates the wiring is deteriorated, which is not preferable.

The present invention was created in view of the above problems in the prior art, and realizes a wiring excellent not only in electrical characteristics but also in environmental resistance, and by extension, in a semiconductor device or a wiring board in which the wiring is incorporated. It is an object of the present invention to provide a wiring forming method capable of contributing to improvement in reliability of the wiring .

[0009]

In order to solve the above-mentioned problems of the prior art, according to one embodiment of the present invention, a via-hole is used.
A resist layer is formed on the insulating layer on which the
Add a certain margin to the required wiring pattern of the dist layer
And pattern to conform to the thickened pattern shape.
Of the area including the area corresponding to the via hole.
Forming an opening in the strike layer and filling the opening
The step of forming the conductor layer so that the upper surface side of the conductor layer
And the surface layer portion on the side surface, the pattern shape of the conductor layer is
Etching until the required wiring pattern shape is obtained
And removing the wiring layer to form a wiring layer.
The surface with nickel / gold, nickel / palladium, or nickel
It is a material with excellent environmental resistance consisting of kel / palladium / gold.
And a step of forming a coating layer made of
A wiring forming method is provided.

[0010]

According to another aspect of the present invention, the via
A first resist layer is formed on the insulating layer in which the holes are formed, and the first resist layer is patterned so as to follow a pattern shape that is thickened by adding a predetermined margin to a required wiring pattern. Forming a first opening in the first resist layer in a portion including a region corresponding to a via hole; and forming a second opening so as to cover the patterned first resist layer and the first opening. Forming a resist layer, and patterning the second resist layer so as to conform to the shape of the required wiring pattern to form the first opening portion.
Forming a side wall of the second resist layer on the side surface.
And a step of forming a second opening in the second resist layer at the position of the first opening, a step of forming a wiring layer in the second opening, and the patterned second Removing the resist layer, and forming nickel / gold, nickel / palladium, or nickel on the surface of the wiring layer.
And a step of forming a coating layer made of a material having excellent environmental resistance, which is made of aluminum / palladium / gold .

According to the wiring forming method of the present invention, Cu
Since the surface of the wiring (wiring layer) made of a material having excellent electrical characteristics such as Ag and Ag but relatively poor environment resistance is covered with a material (covering layer) having excellent environment resistance, Thus, it is possible to realize a structure in which environment resistance is added to the required electrical characteristics of the wiring as a whole. As a result, it is possible to eliminate the inconvenience (contamination and migration due to diffusion, etc.) seen in the conventional wiring, and it is possible to improve the reliability of the semiconductor device, the wiring board and the like having the wiring therein. Become.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a wiring forming method for realizing a wiring structure according to the present invention will be described below with reference to the accompanying drawings. 1 to 4 show an application example of the wiring forming method according to the first embodiment of the present invention.
3A and 3B sequentially show manufacturing steps of a semiconductor device having a CSP structure.

First, in the first step (see FIG. 1A),
A wafer 10 having a plurality of semiconductor chips (not shown) is manufactured. As an example, silicon nitride (SiN) or phosphorus glass (PSG) is formed on the surface of a silicon (Si) substrate.
After forming the passivation film 11 as a protective film made of, for example, a large number of aluminum (Al) conductor layers (electrode pads) formed in a required pattern on each semiconductor chip.
The passivation film 11 corresponding to the region 12 is removed. As a result, as shown in the drawing, the wafer 10 in which the electrode pad 12 is exposed and the surface of the wafer 10 is covered with the passivation film 11 except the region corresponding to the electrode pad 12 is manufactured. In this case, the passivation film 11 is formed on the wafer 10.
Alternatively, the insulating layer formed in the next step may also serve as the passivation film without providing the above.

In the next step (see FIG. 1B), a photosensitive polyimide as a photosensitive resist for forming an insulating layer on the surface of the wafer 10 is applied by photolithography to a thickness of about 6 μm. After the resist layer is soft-baked (pre-baked), exposure and development (patterning of the resist layer) are performed using a mask (not shown), and further hard baking (post-baking) is performed. The patterning of the resist layer is performed so as to follow the shape of the electrode pad 12. Therefore, when exposure and development are performed, the resist layer (polyimide layer) in the portion corresponding to the electrode pad 12 is removed as shown in the figure, and the insulating layer 13 having an opening (via hole) reaching the electrode pad 12 is formed. It is formed.

In the present embodiment, photosensitive polyimide is used as the material of the insulating layer 13, but a non-photosensitive resin such as polyimide may be used instead. However, in this case, since photolithography cannot be used, for example, an opening (via hole) is formed by laser processing.
Will be formed. In the next step (see FIG. 1C), the metal thin film 14 is formed on the entire surface by sputtering in a vacuum atmosphere. The metal thin film 14 has a two-layer structure of a chromium (Cr) layer provided to enhance the adhesiveness to the lower insulating layer 13 and a copper (Cu) layer laminated thereon. The metal thin film 14 is formed by depositing Cr on the entire surface by sputtering to form a Cr layer in the lower layer portion, and further depositing Cu thereon by sputtering to form a Cu layer in the upper layer portion. Here, the Cu layer in the upper layer portion is formed with a thickness of several Å.

The metal thin film 14 thus formed
Functions as a power supply layer, that is, a plating base film for an electrolytic plating process required in forming a wiring layer, a coating layer, and a film on the surface of the bonding wire in a later step. In the next step (see FIG. 1D), for example, a dry film is formed as the photosensitive resist 15 on the metal thin film 14, and exposure and development (patterning of the resist layer) are performed using a mask (not shown). )I do. This patterning is performed so as to conform to the shape of the wiring pattern formed in a later step. As a result, the opening P1 is formed in the resist layer 15 in the portion corresponding to the wiring region.

The term "wiring pattern" as used herein means
It refers to a thickened pattern in which a predetermined margin is added to a required wiring pattern corresponding to the final wiring layer. This predetermined margin defines the thickness of the coating layer that will be formed in a later step. In the next step (see FIG. 2A), a Cu plating layer 16 is formed so as to fill the opening P1 (see FIG. 1D) by electrolytic plating by feeding power from the metal thin film (feed layer) 14. To do. The Cu plating layer 16 follows the shape of the wiring pattern.

In the next step (see FIG. 2B), Cu is used in order to secure a space for forming a coating layer in a later step.
Isotropic etching is performed on the plating layer 16 (see FIG. 2A), and the wiring pattern is patterned until it has a desired wiring pattern shape corresponding to the final wiring layer 17 as illustrated. Make the width narrower. By this etching treatment, the surface layer portions (upper surface side and side surface side) of the Cu plating layer 16 are removed, and the spaces S at equal intervals are provided in the removed portions.
P is secured. On the other hand, the remaining portion of the Cu plating layer 16 is defined as the final wiring layer 17. The wiring layer 17 is also called a "rewiring layer". In this embodiment, the thickness of the wiring layer 17 is selected to be about several tens of μm.

Since the etching process also removes the portion of the Cu layer below the Cu plating layer 16 (upper layer portion of the power feeding layer 14), strictly speaking, the space to be secured is as shown in the illustrated example. Are slightly different, but the display is omitted for simplification of the drawing. In the next step (see FIG. 2C), nickel (Ni) plating and gold (Au) plating are similarly performed on the surface of the Cu wiring layer 17 by electrolytic plating by feeding power from the metal thin film (feed layer) 14. Then, a Ni / Au plating layer is formed to a thickness of about 1 μm.
The Ni / Au plated layer serves as the coating layer 18. When forming the coating layer 18, Ni plating and Au were used.
Instead of plating, Ni plating and palladium (Pd) plating may be applied to form a Ni / Pd plating layer. Or, instead of Ni plating and Au plating, Ni plating and P
The Ni / Pd / Au plated layer may be formed by performing d plating and Au plating.

The covering layer 18 formed to cover the surface of the wiring layer 17 protects the wiring layer 17 intended for the present invention (prevents contamination, migration, etc.) and facilitates the workability of wire bonding described later. To help. In the next step (see FIG. 2D), the resist layer 15 (see FIG. 2C) is stripped and removed using a resist stripping solution such as NaOH solution.

In the next step (see FIG. 3A), a dry film, for example, is formed as a photosensitive resist 19 on the metal thin film 14 and the coating layer 18, and exposed using a mask (not shown). And development (patterning of the resist layer). This patterning is performed according to the shape of the terminal forming portion of the wiring layer 17 (covering layer 18), that is, the portion (bonding pad) to which the wire is to be bonded by wire bonding performed in a later step.
As a result, the opening P2 is formed in the resist layer 19 in the portion corresponding to the region of the bonding pad.

Further, by wire bonding, the Au wire 20 as an external connection terminal is bonded to the bonding pad exposed in the opening P2. The wire 20 has a diameter of about 25 μm and is formed in an S shape. In the next step (see FIG. 3 (b)), in order to give the wire 20 an elastic force, nickel alloy plating is applied by electrolytic plating by feeding from the metal thin film (feed layer) 14, and the surface of the wire 20 is applied. The Ni alloy film 21 is formed. As a result, the total diameter of the wire (represented by reference numeral 22) having the Ni alloy film 21 formed on its surface is about 50 μm.
And

At this time, as can be seen from the structure shown in the drawing, the Ni alloy film 21 is also formed on the surface of the bonding pad (exposed terminal forming portion of the coating layer 18). N
As a material for forming the i alloy film 21, for example, nickel-cobalt (Ni-Co), nickel-chromium-molybdenum (Ni-Cr-Mo), or the like can be used.

In the next step (see FIG. 3C), NaO is used.
The resist layer 19 (see FIG. 3B) is peeled and removed using a resist stripping solution such as H solution. In the next step (see FIG. 4A), the exposed power supply layer 14 is removed by etching. That is, the Cu layer in the upper layer portion of the power feeding layer 14 is removed with an etching solution that dissolves Cu, and then the Cr layer in the lower layer portion is removed with an etching solution that dissolves Cr. As a result, the insulating layer (polyimide layer) 13 is exposed as illustrated.

In the next step (see FIG. 4B), in order to facilitate the soldering when the semiconductor chip is mounted on a printed circuit board or the like in the later step, electroless plating is used to form the surface. An Au film 23 having a thickness of about 0.1 μm is formed on the surface of the wire 22 on which the Ni alloy film has been formed. At this time, since the electroless plating is performed by immersing the entire wafer in a plating solution containing a metal salt and a reducing agent as main components,
Actually, as shown in the drawing, the Au film 23 is formed not only on the surface of the wire 22 but also on the surfaces of other metal parts (the coating layer 18 and the power feeding layer 14). Note that, for convenience of illustration, Au is provided on the surface.
The wire on which the coating 23 is formed is designated by the reference numeral 24.

In the final step (see FIG. 4C), the wafer 10 is cut by a dicer or the like to separate individual semiconductor chips CP, and each semiconductor chip is mounted on a mounting board 25 such as a printed board. This is wire 2 as shown
This is performed by applying the tip end of No. 4 to the corresponding electrode pad (not shown) on the mounting substrate 25 and adhering it with solder 26.

As described above, according to the first embodiment, as shown in FIG. 2, the wiring layer 17 made of Cu having excellent electric characteristics but relatively poor environmental resistance.
The surface of the coating layer 18 made of a material having excellent environmental resistance.
Since it is covered with (Ni / Au plated layer or Ni / Pd plated layer), it is possible to realize a structure in which environment resistance is added to required electrical characteristics of the entire wiring.

As a result, it is possible to eliminate the inconveniences such as contamination and migration due to diffusion, which are seen in the conventional wiring. This contributes to the improvement of the reliability of the semiconductor device having the CSP structure in which the wiring is incorporated. Further, since isotropic etching can form spaces SP at equal intervals around the wiring layer 17, the coating layer 1 that should be formed so as to cover the surface of the wiring layer 17.
The thickness of 8 can be made uniform. This is the coating layer 1
From the viewpoint of protecting the wiring layer 17 by means of 8, it further contributes to prevention of contamination, migration and the like.

Further, as described in connection with the step of FIG. 3B, since the S-shaped wire 20 (22, 24) as the external connection terminal of the semiconductor chip is given an elastic force, The semiconductor chip CP is mounted on the mounting substrate 2 in the step of FIG.
The stress generated when mounted on 5 can be relaxed,
As a result, the connection reliability between the two can be improved. Further, since the impedance can be optimized depending on the length and shape of the wire, it is possible to contribute to the improvement of the electrical characteristics of the semiconductor device. Furthermore, since the wire shape has a relatively larger surface area than the electrode structure such as the solder bump, it is advantageous in terms of the heat dissipation effect.

In the above-described first embodiment, the etch back process is used to secure the space for forming the coating layer, which is a feature of the present invention (see FIG. 2B), but the coating layer is formed. Of course, the method for securing the space is not limited to this. One example is shown in FIG. FIG. 5 shows partial steps for explaining the wiring forming method according to the second embodiment of the present invention.

The semiconductor device having a CSP structure to which the wiring forming method according to the present embodiment is applied undergoes the same steps as the steps of FIGS. 1A to 1C in the first embodiment, and further, FIG. After the steps shown in (a) to FIG. 5 (d) are performed, the same steps as the steps of FIG. 2 (c) and the subsequent steps in the first embodiment are performed to manufacture. In this embodiment, two types of resists are used and each patterning is devised as a method for securing the space for forming the coating layer.

First, in the step shown in FIG. 5A, the first resist layer 31 is applied on the metal thin film 14, and the resist layer is patterned so as to follow the shape of the wiring pattern. An opening Q1 is formed in the corresponding portion of the resist layer 31. The "wiring pattern" referred to here is a pattern that is thickened by adding a predetermined margin to the required wiring pattern as described above.

Next, in the step shown in FIG. 5B, the opening Q
The second resist layer 32 is applied so as to cover the first and first resist layers 31, and the resist layer is patterned so as to follow the shape of the required wiring pattern. The opening Q2 thus formed defines the required wiring pattern width. Next, in the step shown in FIG. 5C, the opening Q is formed by electrolytic plating by feeding power from the metal thin film (feeding layer) 14.
A Cu plating layer 33 is formed on the substrate 2. The Cu plating layer 33 constitutes the final wiring layer, and the thickness thereof is selected to be about several tens of μm as in the first embodiment.

Further, in the step shown in FIG. 5D, the second resist layer 32 (see FIG. 5C) is removed. As a result, a uniform space for forming the coating layer is secured around the wiring layer 33 as shown in the figure. After that, a coating layer is formed so as to fill this space (see FIG. 2C), and then the first layer is formed.
The resist layer 31 is removed (see FIG. 2D). When removing each of the resist layers 31 and 32, processing is performed using a chemical solution that can dissolve only the other resist layer without affecting one resist layer.

In each of the above-mentioned embodiments, Cu is used as the wiring material forming the final wiring layer.
Of course, other wiring materials such as Ag may be used instead. Further, in each of the above-described embodiments, the semiconductor device having the CSP structure using the S-shaped wire as the external connection terminal has been described, but it goes without saying that the form of the external connection terminal is not limited to this. May be used.

An example of a semiconductor device using such solder balls as external connection terminals is shown in FIG. 6, and can be manufactured, for example, as follows. First, after the steps similar to the steps of FIGS. 1A to 2D in the first embodiment, the metal thin film 14 and the coating layer 18 are performed.
By patterning a photosensitive resist such as a dry film so as to conform to the shape of the via post on the top, and then electrolytic plating by feeding from the metal thin film (feeding layer) 14,
A Cu via post 41 is formed using the patterned resist layer as a mask, and a barrier metal layer is further formed on the top of the via post if necessary, and then the resist layer is removed to expose the exposed power supply layer. 14 is removed by etching, and the wafer 10 is further sealed with a sealing resin (sealing resin layer 4
After sealing by 2), solder balls 43 as external connection terminals are adhered to the exposed tops of the via posts 41 by reflow. After that, the wafer 10 together with the sealing resin layer 42 is cut into individual semiconductor chips by a dicer or the like, and each semiconductor chip is mounted on a mounting substrate.

Further, the semiconductor device illustrated in FIG. 6 has a structure in which via posts are provided on the wiring layer 17 covered with the coating layer 18, but as a structure of a semiconductor device having no such via posts. Of course, it is also good. An example of such a semiconductor device having no via post is shown in FIG. 7 and can be manufactured, for example, as follows.

First, FIG. 1A in the first embodiment.
After the steps similar to the step of FIG. 2D, the exposed power feeding layer 14 is removed by etching, and then the sealing resin layer 44 is formed so as to cover the exposed insulating layer 13 and the covering layer 18.
Is formed by, for example, potting, and a via hole is formed in the region of the sealing resin layer 44 corresponding to the terminal forming portion of the covering layer 18 (wiring layer 17) by a laser or the like, and then external connection is made in the via hole. The solder balls 45 as terminals are arranged and reflow is performed to bond the solder balls 45 onto the coating layer 18 (wiring layer 17). Thereafter, as in the case of FIG. 6, the semiconductor chips are separated into individual semiconductor chips and mounted on a mounting substrate.

A solder resist layer may be formed instead of the sealing resin layer 44. In this case, the solder resist layer should be applied by screen printing so as to open the solder ball joints, or a photosensitive solder resist should be applied and the resist layer should be patterned by exposure and development. Can be formed by

Further, in each of the above-described embodiments, the case where the present invention is applied to the formation of the redistribution layer in the semiconductor device having the CSP structure has been described. However, as apparent from the gist of the present invention, the application form is Of course, it is not limited to. For example, in order to mount a semiconductor device having a package structure such as a semiconductor device having a CSP structure or a ball grid array (BGA), it has been put into practical use in order to meet the needs for miniaturization and high density of wiring which have recently been required. The present invention can be applied to a wiring board such as a build-up wiring board which has been developed.

Many kinds of build-up wiring boards can be manufactured by combining the material of the interlayer insulating layer and the via hole forming process, and the manufacturing process thereof is generally
The formation of the insulating layer, the formation of the via hole in the insulating layer, and the formation of the conductor pattern (that is, the wiring layer) including the inside of the via hole are sequentially repeated to stack each layer. In this process, when forming the conductor pattern (wiring layer), the wiring forming method according to each of the above-described embodiments can be applied.

FIG. 8 shows an example thereof. In the figure, 50 is a core substrate (insulating material) of the build-up wiring board,
Reference numeral 51 is a second insulating layer of the build-up wiring board, 52 is a solder resist layer for protecting the build-up wiring board,
Reference numerals 53 and 56 are metal thin films corresponding to the metal thin film 14 (see FIG. 4A), 54 and 57 are wiring layers corresponding to the wiring layer 17 (see FIG. 4), and 55 and 58 are covering layers 18 (see FIG. 4). ) Is a coating layer, and 59 is a coating layer 58 (wiring layer 57) exposed from the opening formed in the solder resist layer 52.
The land part of is shown. Electrode terminals of semiconductor elements mounted on the build-up wiring board are connected to the land portions 59.

[0044]

As described above, according to the present invention, it is possible to realize a wiring which is excellent not only in electrical characteristics but also in environmental resistance, whereby a semiconductor device, a wiring board, etc. in which the wiring is embedded can be realized. It is possible to improve the reliability of the.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device having a CSP structure to which a wiring forming method according to a first embodiment of the present invention is applied.

FIG. 2 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process that follows the manufacturing process in FIG.

FIG. 5 is a sectional view showing a partial process for explaining a wiring forming method according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another application example (1) of the wiring forming method according to each embodiment of the present invention.

FIG. 7 is a cross-sectional view showing another application example (2) of the wiring forming method according to each embodiment of the present invention.

FIG. 8 is a sectional view showing another application example (3) of the wiring forming method according to each embodiment of the present invention.

[Explanation of symbols]

CP ... Semiconductor chip 10 ... Wafer 11 ... Protective film (passivation film) 12 ... Conductor layer (Al electrode pad) 13 ... Insulating layer (polyimide layer) 14, 53, 56 ... Metal thin film (feeding layer, plating base film) 15, 19, 31, 32 ... Resist layer 16 ... Conductor layer (Cu plating layer) 17, 33, 54, 57 ... Wiring layer (Cu plating layer) 18, 55, 58 ... Covering layer (Ni / Au plating layer or N
i / Pd plating layer) 20, 22, 24 ... Wire (external connection terminal) 21 ... Ni alloy film 23 ... Au film 25 ... Mounting substrate 26 ... Solder 41 ... Via / post 42, 44 ... Encapsulating resin layer 43, 45 ... Solder balls (external connection terminals) 50 ... Core substrate (insulating material) 51 ... Insulating layer 52 ... Solder resist layer 59 ... Land portion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/88 C (72) Inventor Aiko Nishiguchi 711, Rishida, Kurita character, Nagano City, Nagano Shinko Electric Industry Co., Ltd. (56) References JP-A-3-153077 (JP, A) JP-A-10-261663 (JP, A) JP-A-8-316234 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H01L 21/3205 H01L 21/288 H01L 21/308 H01L 21/3213

Claims (6)

(57) [Claims] 1. A resist layer is formed on an insulating layer in which a via hole is formed, and the resist layer is patterned so as to follow a thickened pattern shape with a predetermined margin added to a required wiring pattern, A step of forming an opening in a resist layer in a portion including a region corresponding to the via hole; a step of forming a conductor layer so as to fill the opening; and a surface layer portion on an upper surface side and a side surface side of the conductor layer. To form a wiring layer by etching until the pattern shape of the conductor layer becomes the shape of the required wiring pattern, and nickel / gold or nickel / palladium is formed on the surface of the wiring layer.
And a step of forming a coating layer made of a material having excellent environment resistance such as um or nickel / palladium / gold . 2. Before the step of forming the opening, a metal thin film is formed by sputtering so as to cover the insulating layer in which the via hole is formed and the lower conductive layer exposed from the via hole. includes the step, claims, characterized in that a conductive layer is formed so as to fill the opening by electrolytic plating using the metal thin film as a power feeding layer
1. The wiring forming method described in 1 . 3. A first resist layer is formed on an insulating layer in which a via hole is formed, and the first resist layer follows a pattern shape in which a desired wiring pattern is thickened in consideration of a predetermined margin. Patterning to form a first opening in a portion of the first resist layer including a region corresponding to the via hole; and the patterned first resist layer and the first resist layer.
Opening to form a second resist layer so as to cover the, patterned to follow a resist layer of the second to the shape of the desired wiring pattern, the said first opening side
By forming a sidewall of the second resist layer
Te, first the second resist layer position of the first opening 2
Forming an opening of the wiring layer, forming a wiring layer in the second opening, removing the patterned second resist layer , nickel / gold on the surface of the wiring layer , Nickel / Paragy
And a step of forming a coating layer made of a material having excellent environment resistance such as um or nickel / palladium / gold . 4. Before the step of forming the first opening,
A step of forming a metal thin film by sputtering so as to cover the insulating layer in which the via hole is formed and the lower conductor layer exposed from the via hole, and by electrolytic plating using the metal thin film as a power feeding layer. The wiring forming method according to claim 3 , wherein a wiring layer is formed in the second opening. 5. The wiring forming method according to claim 3 , wherein the patterned second resist layer is removed by using a chemical solution that does not affect the first resist layer. 6. The wiring forming method according to claim 1 , wherein the predetermined margin defines the thickness of the coating layer to be formed on the surface of the wiring layer.