JP2019062062A - Wiring board, electronic device, and manufacturing method of wiring board - Google Patents

Abstract

To provide a high-reliable wiring board, an electronic device, and manufacturing method of wiring board.SOLUTION: The wiring board includes: a substrate made of an insulation material or a semiconductor material; an adhesion layer formed over the substrate being overlapped therewith; a first seed layer formed of a first metal which may be formed as a the seed layer disposed being overlapped with the adhesion layer; a second seed layer formed of an alloy of a wiring metal and a second metal that has ionization tendency larger than that of the wiring metal, which is disposed being overlapped with the first seed layer; and a wiring layer of the wiring metal disposed being overlapped with the second seed layer. The first metal is a metal the ionization tendency of which is smaller than that of the second metal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board, an electronic device, and a method of manufacturing the wiring board.

  Conventionally, a feeding film made of a reactive ion-etchable material formed on a substrate, an electrolytic plating layer formed on the feeding film, and a feeding film formed between the feeding film and the electrolytic plating layer There is a metal wiring comprising: an adhesion layer for enhancing the adhesion of the electrolytic plating layer. The feed film is characterized in that one or two or more of Mo, W, Pt, or an alloy thereof is used as a main component. A nickel thin film is used as the adhesion layer, a copper plating layer is used as the electrolytic plating layer, and the copper plating layer is used as a portion of the metal wiring (for example, see Patent Document 1).

JP, 2001-028477, A

  By the way, when the copper plating layer is formed on the nickel thin film (adhesion layer), if the oxide film produced on the surface of the nickel thin film (adhesion layer) can not be completely removed, voids are present at the site where the oxide film remains. It may occur.

  Such a void is generated between the nickel thin film (adhesion layer) and the copper plating layer, so that the electrical resistance of the metal wiring is increased, the electrical signal can not be transmitted properly, and the reliability may be reduced.

  Therefore, it is an object of the present invention to provide a highly reliable wiring board, an electronic device, and a method of manufacturing the wiring board.

  The wiring substrate according to the embodiment of the present invention can be formed as a seed layer by being disposed so as to overlap with a substrate made of an insulating material or a semiconductor material, an adhesion layer disposed to overlap the substrate, and the adhesion layer. A second seed layer made of an alloy of a first metal first seed layer and an alloy of a wiring metal and a second metal having a larger ionization tendency than the wiring metal, disposed on the first seed layer. And a wiring layer made of the metal for wiring, which is disposed so as to overlap with the second seed layer, and the first metal is a metal having a smaller ionization tendency than the second metal.

  It is possible to provide a highly reliable wiring board, an electronic device, and a method of manufacturing the wiring board.

It is a figure showing the sectional view of wiring board 100 of an embodiment. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100. FIG. 1 is a view showing an electronic device 200 including a wiring substrate 100. It is a figure which shows the cross-section of the wiring board 100M of the modification of embodiment. FIG. 7 is a view showing a cross-sectional structure in a manufacturing process of wiring substrate 100.

  Hereinafter, an embodiment to which a wiring board, an electronic device, and a method for manufacturing a wiring board of the present invention are applied will be described.

Embodiment
FIG. 1 is a cross-sectional view of a wiring board 100 according to the embodiment. Below, it demonstrates using the XYZ coordinate system which is an example of a rectangular coordinate system. The wiring substrate 100 has a rectangular shape in an XY plan view, and FIG. 1 shows a cross-sectional structure in which the wiring substrate 100 is cut along the XZ plane. In addition, although it demonstrates using XZ cross-section below, YZ cross-section may be the same structure.

  The wiring substrate 100 includes a substrate 110, an adhesion layer 120, a seed layer 130, an alloy layer 140, a wiring layer 150, and a resin layer 160. The wiring layer 150 of such a wiring substrate 100 is manufactured by Semi Additive Process (SAP method). By using the SAP method, it is possible to produce the wiring layer 150 having a line width of several nm or less.

  The substrate 110 is, for example, a substrate made of an insulating material. The substrate 110 may be a wiring substrate of FR-4 (Flame Retardant type 4) standard, or an interposer. Further, the substrate 110 may be a substrate made of a semiconductor material such as Si (silicon). In this case, a circuit may be provided inside the substrate 110. The adhesion layer 120, the seed layer 130, the alloy layer 140, the wiring layer 150, and the resin layer 160 are provided on the surface 111 on the Z-axis positive direction side of the substrate 110.

  The adhesion layer 120 is a layer which is provided on the surface 111 of the substrate 110 and causes the substrate 110 and the seed layer 130 to adhere to each other. As the adhesion layer 120, for example, a metal layer such as Ti (titanium) or Cr (chromium) can be used. Here, as an example, a form in which the adhesion layer 120 is a Ti layer will be described. The adhesion layer 120 is produced by forming a Ti layer on the surface 111 of the substrate 110 by sputtering or the like, and its thickness is, for example, 100 nm or less.

  The seed layer 130 is provided on the adhesion layer 120, and is a seed layer of one of two seed layers used when the wiring layer 150 is formed by electrolytic plating. The seed layer 130 is an example of a first seed layer.

  The seed layer 130 may be a metal layer satisfying the following four conditions. The metal forming the seed layer 130 is, for example, Ni (nickel), Al (aluminum), Nb (niobium), W (tungsten), Ni-P (nickel-phosphorus) layer, or Ni-B (nickel-boron) And the like (a first condition) and a metal that can be used as a seed layer (a second condition).

  Further, the metal forming the seed layer 130 is a metal which can be selectively removed from Cu by wet etching or dry etching (third condition), and is more than the metal of the diffusion metal layer described later. It is necessary that the metal has a small ionization tendency (the fourth condition).

  The seed layer 130 is formed, for example, by sputtering, electroless plating, or electrolytic plating, and has a thickness of, for example, 200 nm or less. Here, as an example, an embodiment in which the seed layer 130 is an Nb layer will be described. The metal of the seed layer 130 is an example of a first metal.

  The alloy layer 140 is provided on the seed layer 130, and is a seed layer of one of the two seed layers used when producing the wiring layer 150 by the electrolytic plating process. The alloy layer 140 is an example of a second seed layer.

  The alloy layer 140 is manufactured by diffusion and alloying of a metal of a diffusion metal layer to be described later and Cu of the wiring layer 150 in the heating step in the manufacturing process of the wiring substrate 100. The diffusion metal layer is in a position where the alloy layer 140 exists before the heating step is performed. The details will be described later with reference to FIGS. 2 to 12.

  As the diffusion metal layer, a metal having an ionization tendency of Cu or more, such as Pt (platinum) or Au (gold), which can be removed by a wet etching process or a dry etching process can be used. Here, as an example, an embodiment using an Au layer as a diffusion metal layer will be described. The metal of the diffusion metal layer is an example of the second metal.

  The wiring layer 150 is a metal layer provided on the alloy layer 140 and functioning as a wiring of the wiring substrate 100. The wiring layer 150 is made of Cu as an example. The wiring layer 150 is manufactured by forming a copper plating layer by an electrolytic plating process using the seed layer 130 and the alloy layer 140 as a seed layer. The metal of the wiring layer 150 is an example of a wiring metal.

  In the wiring layer 150, various electric signals can flow by the wiring substrate 100 being connected to an IC (Integrated Circuit) chip or the like. Note that Ni (nickel) or W (tungsten) may be used as the wiring layer 150 instead of Cu.

  The resin layer 160 is an insulating layer covering the substrate 110, the adhesion layer 120, the seed layer 130, the alloy layer 140, and the wiring layer 150 on the surface 111 of the wiring substrate 100. The resin layer 160 is formed to protect the wiring layer 150 and the like from external corrosion or physical impact, and is provided as a protective layer.

  Next, a method of manufacturing the wiring substrate 100 will be described with reference to FIGS. FIG. 2 to FIG. 12 are views showing the cross-sectional structure in the manufacturing process of the wiring substrate 100. FIG. Hereinafter, the surface on the Z-axis positive direction side is referred to as the upper surface.

  First, as shown in FIG. 2, an adhesion layer 120A is produced by forming a Ti layer on the entire upper surface of the surface 111 of the substrate 110 by sputtering or the like. The thickness of the adhesion layer 120A is, for example, 100 nm or less. The adhesion layer 120A is to be etched later to form the adhesion layer 120 shown in FIG. 1, and is formed on the entire top surface of the surface 111 at this stage.

  Next, as shown in FIG. 3, a seed layer 130A is produced by forming an Nb layer on the entire top surface of the adhesion layer 120A by sputtering. The thickness is, for example, 200 nm or less. The seed layer 130A is formed into the seed layer 130 shown in FIG. 1 by performing an etching process later, and at this stage, the seed layer 130A is formed on the entire top surface of the adhesion layer 120A.

  Here, an embodiment in which the Nb layer is formed by sputtering as the seed layer 130A will be described, but in the case of forming the Ni layer, it can be formed by sputtering, electroless plating, or electrolytic plating. When forming an Al layer or a W layer, it can be formed by sputtering, and when forming a Ni-P layer or a Ni-B layer, form it by electroless plating or electrolytic plating Can.

  Next, as shown in FIG. 4, a diffusion metal layer 140A is formed on the entire top surface of the seed layer 130A. Here, since the Au layer is used as the diffusion metal layer 140A, the diffusion metal layer 140A can be formed by a sputtering method, an evaporation method, or an electroless plating process. When a Pt layer is used as the diffusion metal layer 140A, it may be formed by sputtering.

  Next, as shown in FIG. 5, a photoresist 50 is formed on the diffusion metal layer 140A. The photoresist 50 applies a photoresist material on the diffusion metal layer 140A, and forms a wiring pattern by an exposure process and a development process. The photoresist 50 is used as a mask when producing the wiring layer 150, and the portion where the photoresist 50 is left is a portion where the wiring layer 150 is not formed.

  Next, as shown in FIG. 6, by performing an electrolytic plating process, the wiring layer 150 is produced in the portion (the portion of the wiring pattern) where the photoresist 50 is not produced on the diffusion metal layer 140A. Although a Cu plating layer is mainly used as the wiring layer 150, a Ni plating layer or a W plating layer may be used instead of the Cu plating layer.

  Next, as shown in FIG. 7, the photoresist 50 is removed. The removal of the photoresist 50 may be performed by a wet etching process using a dedicated etching solution.

  Next, as shown in FIG. 8, Cu of the wiring layer 150 and Au of the diffusion metal layer 140 A are diffused by heat treatment (annealing), and the alloy layer 140 is formed only immediately below the wiring layer 150. By performing the heat treatment in a low oxygen atmosphere at a heating temperature of 150 ° C. or higher, the wiring layer 150 is not oxidized, and metal diffusion can be rapidly realized. As Cu of the wiring layer 150 and Au of the diffusion metal layer 140A are diffused by the heat treatment, different metals are mixed, and voids at the interface as in the prior art are not generated.

  Note that the temperature of the heat treatment may be set as appropriate in accordance with the combination of the metals to be diffused, or the like. In addition, when diffusion occurs at normal temperature, it may be normal temperature.

  Next, as shown in FIG. 9, the remaining diffusion metal layer 140A is removed using a dedicated etching solution. The remaining diffusion metal layer 140A is a portion of the diffusion metal layer 140A produced in the step shown in FIG. 4 that is not located immediately below the wiring layer 150. When the diffusion metal layer 140A is an Au layer, an etching solution dedicated to Au may be used.

  Next, as shown in FIG. 10, the seed layer 130 is obtained by etching except for the portion of the seed layer 130A located immediately below the alloy layer 140. Here, since the Nb layer is used as the seed layer 130A, the seed layer 130 can be formed by performing the dry etching process. Even if the seed layer 130 is miniaturized, the wiring strength can be maintained, and further reliability can be ensured.

  The dry etching process is also possible when using an Al layer or a W layer as the seed layer 130A. In the case of using a Ni layer, a Ni-P layer, or a Ni-B layer, a wet etching process may be performed.

  Next, as shown in FIG. 11, the adhesion layer 120 is formed by performing an etching process while leaving the portions of the adhesion layer 120A directly under the wiring layer 150, the alloy layer 140, and the seed layer 130. Here, since a Ti layer is used as the adhesion layer 120A, a wet etching process may be performed using a dedicated etching solution of Ti.

  Finally, as shown in FIG. 12, a resin layer 160 covering the adhesion layer 120, the seed layer 130, the alloy layer 140, and the wiring layer 150 is formed on the surface of the substrate 110, thereby the cross section shown in FIG. The same wiring substrate 100 as the structure can be manufactured.

  The wiring substrate 100 as described above can be used in an electronic device 200 as shown in FIG. FIG. 13 is a view showing the cross-sectional structure of the electronic device 200. As shown in FIG.

  The electronic device 200 includes a circuit board 210, bumps 220, an interposer 230, bumps 240, and an IC (Integrated Circuit) chip 250.

  The circuit board 210 is, for example, a multilayer wiring board of the FR-4 standard, and here, as an example, a multilayer wiring board having six wiring layers is shown. The circuit board 210 is a multilayer board in which six wiring layers and five insulating layers (for example, a core layer or a prepreg layer) are alternately stacked and thermocompression bonded.

  The circuit board 210 has a terminal 211 disposed on the surface on the Z-axis positive direction side. The terminal 211 is a wiring layer that is formed by copper plating and located on the top layer of the circuit board 210. The description of the configuration below the uppermost layer of the circuit board 210 is omitted. Alternatively, the circuit board 210 may be regarded as a wiring board.

  The bumps 220 are solder bumps for connecting the terminals 211 of the circuit board 210 and the terminals 232 of the interposer 230, and are, for example, C4 bumps.

  The interposer 230 has a circuit or the like formed inside a semiconductor substrate 231 made of silicon, glass, resin or the like, and has a terminal 232 disposed on the surface in the negative Z-axis direction and a surface on the positive Z-axis direction. And a terminal 233 disposed. Circuits and the like inside the semiconductor substrate 231 are connected to the terminals 232 and 233.

  The bumps 240 are Cu pillar bumps, and connect the terminals 233 of the interposer 230 and the terminals 251 provided on the surface of the IC chip 250 in the negative Z-axis direction.

  The IC chip 250 has a terminal 251 provided on the surface on the Z axis negative direction side. The terminal 251 is connected to an integrated circuit provided inside the IC chip 250. The IC chip 250 is an example of a semiconductor element. Here, although the IC chip 250 as an example of a semiconductor device is described as being included in the electronic device 200, for example, a semiconductor device larger than a semiconductor device such as a semiconductor device including a plurality of IC chips 250 is described. May be included in the electronic device 200.

  In such an electronic device 200, for example, the wiring substrate 100 can be regarded as using the interposer 230 as the substrate 110 and using the wiring connected to the terminal 233 as the wiring layer 150. In this case, the adhesion layer 120, the seed layer 130, the alloy layer 140, and the wiring layer 150 are provided on the surface of the semiconductor substrate 231 used as the substrate 110 in the positive Z-axis direction. It is provided at the end.

  The wiring substrate 100 can be used, for example, in a portion where miniaturization between the interposer 230 and the IC chip 250 is required.

  In recent years, various functions are required of semiconductor devices, and there is a tendency to mount a plurality of semiconductor elements (IC chips 250) in one semiconductor device. For this reason, a technology for closely bonding and densely mounting semiconductor elements (IC chip 250) on a single circuit board 210 via a plurality of semiconductor elements (IC chip 250) via fine wiring layers (wiring layer 150 etc.) Is being developed.

  The semiconductor elements (IC chips 250) are mounted at high density by bonding between the semiconductor elements (IC chips 250) and the circuit substrate 210 via the interposer 230 having fine wiring. By forming a fine wiring layer in the interposer 230 and bonding it to a plurality of semiconductor elements (IC chips 250), high-density mounting can be achieved, and high functionality of the semiconductor device can be realized.

  As described above, wiring substrate 100 according to the present embodiment is a metal or alloy other than Cu such as Nb as the seed layer 130 (first condition), and is a metal that can be used as the seed layer, Cu is a metal which can be selectively removed by etching, and a metal which has a smaller ionization tendency than the metal of the diffusion metal layer 140A is used.

  Further, as the diffusion metal layer 140A, a metal having a larger ionization tendency than that of the metal (wiring metal) of the wiring layer 150 is used.

  For this reason, in the heat treatment in the manufacturing stage, the seed layer 130 is hardly alloyed and remains almost unchanged, and the alloy layer 140 made of the alloy of the metal of the diffusion metal layer 140A and the metal of the wiring layer 150 It is produced between the layer 150.

  Therefore, after heat treatment, generation of a void between the wiring layer 150 and the alloy layer 140 can be suppressed, and deterioration of the electrical signal transmitted by the wiring layer 150 can be suppressed, and the correct content can be obtained. Can transmit electrical signals.

  As described above, according to the embodiment, it is possible to provide a highly reliable wiring substrate 100, an electronic device 200, and a method of manufacturing the wiring substrate 100. In the wiring substrate 100, even in the case of fine wiring of L & S = 1 μm / 1 μm, side etching does not occur and wiring strength can be maintained.

  In the above, the embodiment has been described in which the seed layer 130 is an Nb layer, the diffusion metal layer 140A is an Au layer, the wiring layer 150 is made of Cu, and the alloy layer 140 is an Au-Cu layer. However, as described above, metals other than these may be used as the seed layer 130, the alloy layer 140, the diffusion metal layer 140A, and the wiring layer 150.

  At that time, it is sufficient to have the following relationship of ionization tendency. The metal (second metal) of the diffusion metal layer 140A may have a larger ionization tendency than the metal (wiring metal) of the wiring layer 150. Further, the metal (first metal) of the seed layer 130 may be a metal having a smaller ionization tendency than the metal (second metal) of the diffusion metal layer 140A.

  In the above description, the adhesion layer 120 is formed directly on the top surface of the substrate 110. However, an insulation layer may be formed on the top surface of the substrate 110, and the adhesion layer 120 may be formed on the insulation layer. Also in this case, the adhesion layer 120 is disposed so as to overlap the substrate 110.

  Further, a metal cap layer may be provided on the wiring layer 150. FIG. 14 is a view showing a cross-sectional structure of a wiring board 100M according to a modification of the embodiment. FIG. 15 is a view showing a cross-sectional structure in the manufacturing process of wiring substrate 100. Referring to FIG.

  A metal cap layer 170 may be provided to cover both side surfaces and the upper surface of the wiring layer 150 as in the wiring substrate 100M shown in FIG. The metal cap layer 170 is made of a metal such as Ni, Co (cobalt) or Sn (tin) or an alloy such as Ni-P, and is provided to protect the wiring layer 150.

  Such a metal cap layer 170 is, as shown in FIG. 15, an Ni—P plated film by electrolytic plating so as to cover the wiring layer 150 after the adhesion layer 120 is produced (of the manufacturing process shown in FIG. 11). Can be made by forming Such a metal cap layer 170 may be handled as a barrier metal layer. The thickness of the metal cap layer 170 is, for example, 50 nm.

Although the wiring substrate, the electronic device, and the method for manufacturing the wiring substrate of the exemplary embodiment of the present invention have been described above, the present invention is not limited to the specifically disclosed embodiments. Various modifications and variations are possible without departing from the scope of the claims.
Further, the following appendices will be disclosed regarding the above embodiment.
(Supplementary Note 1)
A substrate made of insulating material or semiconductor material,
An adhesion layer disposed over the substrate;
A first metal first seed layer disposed on the adhesion layer and capable of being formed as a seed layer;
A second seed layer made of an alloy of a wiring metal and a second metal having a larger ionization tendency than the wiring metal, disposed on the first seed layer;
A wiring layer made of the metal for wiring, which is disposed to overlap the second seed layer;
The wiring substrate, wherein the first metal is a metal having a smaller ionization tendency than the second metal.
(Supplementary Note 2)
The wiring substrate according to claim 1, wherein the first metal is a metal selectively etchable with the wiring metal.
(Supplementary Note 3)
The wiring substrate according to any one of Appendices 1 or 2, wherein the first metal is nickel, niobium, aluminum, tungsten, an alloy of nickel and chromium, or niobium nitride.
(Supplementary Note 4)
The above-mentioned second metal is gold, the above-mentioned alloy is an alloy of the above-mentioned wiring metal and gold, or the above-mentioned second metal is platinum, and the above-mentioned alloy is an alloy of the above-mentioned wiring metal and platinum. 3. The wiring board according to any one of 1 to 3.
(Supplementary Note 5)
The wiring substrate according to any one of claims 1 to 4, further comprising a protective layer covering the adhesion layer, the first seed layer, the second seed layer, and the wiring layer on the substrate.
(Supplementary Note 6)
The wiring substrate according to any one of the above 1 to 5, further comprising a metal cap layer covering the side surface and the top surface of the wiring layer.
(Appendix 7)
A wiring board,
A semiconductor element connected to the wiring substrate;
An electronic device comprising: a bump electrically connecting the wiring substrate and the semiconductor element;
The wiring board is
A substrate made of insulating material or semiconductor material,
An adhesion layer disposed over the substrate;
A first metal first seed layer disposed on the adhesion layer and capable of being formed as a seed layer;
A second seed layer made of an alloy of a wiring metal and a second metal having a larger ionization tendency than the wiring metal, disposed on the first seed layer;
A wiring layer made of the metal for wiring, which is disposed to overlap the second seed layer;
The electronic device, wherein the first metal is a metal having a smaller ionization tendency than the second metal.
(Supplementary Note 8)
Forming an adhesive layer on a substrate made of an insulating material or a semiconductor material,
Forming a first metal first seed layer which can be formed as a seed layer on the adhesion layer;
Forming a second metal diffusion layer having a larger ionization tendency than the wiring metal on the first seed layer;
Forming the wiring layer made of the metal for wiring over the diffusion layer;
Forming a second seed layer made of an alloy of the metal for wiring and the second metal in a portion of the diffusion layer below the wiring layer by performing a heat treatment;
Removing the diffusion layer, the first seed layer, and the adhesion layer, which are not located under the wiring layer,
The method for manufacturing a wiring board, wherein the first metal is a metal having a smaller ionization tendency than the second metal.

100, 100M wiring substrate 110 substrate 111 surface 120, 120A adhesion layer 130, 130A seed layer 140 alloy layer 140A diffusion metal layer 150 wiring layer 160 resin layer 170 metal cap layer 200 electronic device 210 circuit substrate 220 bump 230 interposer 240 bump 250 IC Chip

Claims (6)

A substrate made of insulating material or semiconductor material,
An adhesion layer disposed over the substrate;
A first metal first seed layer disposed on the adhesion layer and capable of being formed as a seed layer;
A second seed layer made of an alloy of a wiring metal and a second metal having a larger ionization tendency than the wiring metal, disposed on the first seed layer;
A wiring layer made of the metal for wiring, which is disposed to overlap the second seed layer;
The wiring substrate, wherein the first metal is a metal having a smaller ionization tendency than the second metal.   The wiring substrate according to claim 1, wherein the first metal is a metal selectively etchable with the wiring metal.   The wiring substrate according to claim 1, wherein the first metal is nickel, niobium, aluminum, tungsten, an alloy of nickel and chromium, or niobium nitride.   The second metal is gold, the alloy is an alloy of the wiring metal and gold, or the second metal is platinum, and the alloy is an alloy of the wiring metal and platinum. The wiring board according to any one of 1 to 3. A wiring board,
A chip component connected to the wiring substrate;
An electronic device comprising: a bump electrically connecting the wiring board and the chip component;
The wiring board is
A substrate made of insulating material or semiconductor material,
An adhesion layer disposed over the substrate;
A first metal first seed layer disposed on the adhesion layer and capable of being formed as a seed layer;
A second seed layer made of an alloy of a wiring metal and a second metal having a larger ionization tendency than the wiring metal, disposed on the first seed layer;
A wiring layer made of the metal for wiring, which is disposed to overlap the second seed layer;
The electronic device, wherein the first metal is a metal having a smaller ionization tendency than the second metal. Forming an adhesive layer on a substrate made of an insulating material or a semiconductor material,
Forming a first metal first seed layer which can be formed as a seed layer on the adhesion layer;
Forming a second metal diffusion layer having a larger ionization tendency than the wiring metal on the first seed layer;
Forming the wiring layer made of the metal for wiring over the diffusion layer;
Forming a second seed layer made of an alloy of the metal for wiring and the second metal in a portion of the diffusion layer below the wiring layer by performing a heat treatment;
Removing the diffusion layer, the first seed layer, and the adhesion layer, which are not located under the wiring layer,
The method for manufacturing a wiring board, wherein the first metal is a metal having a smaller ionization tendency than the second metal.

Images