JP2007258354A - Process for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for manufacturing a semiconductor device in which a plating layer can be formed suitably even at the corner of a resist layer and the wafer surface when the plating layer is formed. <P>SOLUTION: The process for manufacturing a semiconductor device sequentially comprises A1 step for forming an insulating resin layer having a first opening at a position corresponding to an electrode provided on one side of a semiconductor substrate on which the insulating resin layer is formed, A2 step for forming a seed layer on the insulating resin layer, A3 step for forming a resist layer having a tapered second opening on the seed layer, A4 step for forming a plating layer on the seed layer, and A5 step for removing the resist layer and the exposed seed layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a structure of a semiconductor package that has been rapidly spread in recent years, for example, a so-called ball grid array (BGA) technique called a chip size package (CSP), in which electrodes are arranged in a plane on a flat surface of the package. Has developed a package structure that enables high-density mounting of semiconductor chips with the same number of electrode terminals and the same projected area on an electronic circuit board in a smaller area than before, greatly contributing to the reduction in size and weight of electronic devices. ing.

  In a manufacturing method generally called “wafer level CSP”, an insulating layer, a rewiring layer, and a sealing resin layer are formed on a silicon wafer to form solder bumps. Then, by cutting the wafer into a predetermined chip size in the final process, a semiconductor chip having a package structure can be obtained. Since these circuits are stacked on the entire surface of the wafer and the wafer is diced in the final process, the size of the cut chip itself becomes a packaged semiconductor chip, which has a minimum projected area with respect to the mounting substrate. (For example, refer to Patent Document 1).

  As described above, the “wafer level CSP” is a semiconductor package having an excellent feature that high-density mounting can be realized, but in a state where the semiconductor package is mounted on the mounting substrate, it is compared with the conventional package substrate. Connection life is inferior. As means for solving this problem, a metal or resin column called a post is formed between a solder bump and a semiconductor device (for example, see Patent Document 2), and a thick resin layer is formed (for example, a patent). (Refer to Document 3).

  A semiconductor chip manufactured by a manufacturing method called “wafer level CSP” has a structure in which an insulating layer, a rewiring layer, a sealing layer, and the like are formed on silicon.

  Of these, the rewiring layer is formed by forming an insulating layer on the wafer, forming a thin seed layer on the entire surface or in a necessary region, and forming a resist layer on the seed layer. This resist layer has an opening. Thereafter, a plating layer is formed, for example, by electrolytic copper plating on the exposed seed layer using the resist layer as a mask. Through the above steps, a wiring path (circuit pattern) made of a Cu plating layer is formed on the Si wafer. Subsequently, the resist layer is peeled off, and an unnecessary seed layer exposed on the surface of the wafer is removed by etching to expose the insulating layer in portions other than the wiring layer.

  At this time, since the opening portion of the resist layer is not tapered, the plating solution may not be able to go around the corner portion formed by the resist layer and the wafer surface, resulting in poor plating. Due to the poor plating, the finished semiconductor package has problems such as wire breakage and partial resistance increase, and subsequent reliability tests such as peeling.

  In addition, by directly forming the seed layer on the insulating layer, the seed layer formed outside the pattern may remain on the insulating layer. In this case, since there is a residue of the seed layer between the insulating layer and the sealing layer formed on the insulating layer, the adhesion between the two layers decreases, and peeling occurs in a subsequent reliability test or the like. There was also a problem.

In order to solve these problems, a first resist layer is provided on the insulating layer, a seed layer is formed thereon, a second resist layer is provided, and a rewiring layer is formed by plating or the like. Has been proposed (see, for example, Patent Document 4). This method eliminates the problem of separation between the two layers because there is no residue of the seed layer between the insulating layer and the sealing layer. However, when the seed layer is formed, the angle between the resist layer and the wafer surface is reduced. Since the seed layer is not formed up to the portion, there is a problem that, even in the subsequent plating method, the resist layer and the wafer surface cannot be plated to the corner, resulting in poor plating. .
JP 2003-124244 A International Publication No. 00/77843 JP 2001-223292 A JP 2005-129882 A

  The present invention has been devised in view of such a conventional situation, and manufacture of a semiconductor device capable of suitably forming a plating layer also at a corner portion formed by a resist layer and a wafer surface when forming the plating layer. It aims to provide a method.

According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming an insulating resin layer having a first opening at a position corresponding to an electrode on a semiconductor substrate having an electrode on one surface side. A1 step to form, A2 step to form a seed layer on the insulating resin layer, A3 step to form a resist layer having a tapered second opening on the seed layer, and the seed layer An A4 step of forming a plating layer thereon and an A5 step of removing the resist layer and the exposed seed layer are sequentially provided.
According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, in the step A3, the tapered inclined surface is within a range of 45 to 85 ° with respect to another flat surface. It is characterized by controlling as follows.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming an insulating resin layer having a first opening at a position corresponding to an electrode on a semiconductor substrate having an electrode provided on one side. B1 step to form, B2 step to form a first resist layer provided with a tapered second opening on the insulating resin layer, and a seed layer on the insulating resin layer and the first resist layer B3 step to be formed, B4 step of forming a second resist layer on the seed layer at a position corresponding to the first resist layer, B5 step of forming a plating layer on the seed layer, B6 process of removing a 1st resist layer and said 2nd resist layer in order is provided, It is characterized by the above-mentioned.
According to a fourth aspect of the present invention, in the semiconductor device manufacturing method according to the third aspect, in the step B2, the tapered inclined surface is within a range of 45 to 85 ° with respect to the other flat surface. It is characterized by controlling as follows.

  In both of the semiconductor device manufacturing methods according to the first and third aspects of the present invention, when the plating layer is formed, the opening provided in the resist layer formed in the preceding step has a taper. By adopting the form, it is possible to provide a method of manufacturing a semiconductor device capable of reducing plating defects that occur at the corners of the resist layer and the wafer surface and thus forming a good plating layer.

<First embodiment>
Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured according to the present invention.
In this semiconductor device 10, an electrode 2 of an integrated circuit (IC, not shown) is formed on the surface of a semiconductor substrate 1 on which an integrated circuit (not shown) is formed.
Further, the semiconductor device 10 is provided so as to cover the insulating resin layer 11 provided on the passivation film 3 of the semiconductor substrate 1, the wiring layer 12 provided on the insulating resin layer 11, and the wiring layer 12. And a sealing resin layer 13.

The semiconductor substrate 1 is provided with, for example, an Al pad as an electrode 2 on at least one surface of a base material 1a whose surface layer forms an insulating portion (not shown), and further a passivation film 3 (passivation) such as SiN or SiO ₂ on the surface. Insulating film) is formed. The passivation film 3 is provided with an opening 4 at a position aligned with the electrode 2, and the electrode 2 is exposed through the opening 4. The passivation film 3 can be formed by, for example, the LP-CVD method, and the film thickness is, for example, 0.1 to 0.5 μm.

  The semiconductor substrate 1 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 1 is a semiconductor chip, first, a plurality of semiconductor elements, ICs, induction elements, etc. are formed on a semiconductor wafer and then cut into chip dimensions to obtain a plurality of semiconductor chips. Can do.

The insulating resin layer 11 has an opening (first opening) 11 a formed at a position aligned with each electrode 2. The insulating resin layer 11 is made of, for example, polyimide resin, epoxy resin, silicone resin, etc., and the thickness thereof is, for example, 5 to 50 μm.
The insulating resin layer 11 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening 11a can be formed, for example, by patterning using a photolithography technique.

The wiring layer 12 penetrates the insulating resin layer 11 through the opening 11 a and is electrically connected to the electrode 2.
As a material of the wiring layer 12, for example, Cu or the like is used, and its thickness is, for example, 1 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The wiring layer 12 can be formed by a plating method such as an electrolytic copper plating method.

  The sealing resin layer 13 is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and the thickness thereof is, for example, 10 to 150 μm. The sealing resin layer 13 is provided with an opening (not shown) for outputting a terminal to the outside.

  And in this semiconductor device 10, when the wiring layer 12 is formed by plating, an opening (second opening) provided in the resist layer 14 formed in the previous step when the wiring layer 12 is formed by plating, as will be described later. 15 has a taper. As a result, the corners formed by the resist layer 14 and the wafer surface are widened at the time of plating, so that the plating solution easily enters the corners formed by the resist layer 14 and the wafer surface, and plating defects can be reduced. As a result, the disconnection failure in the vicinity of the opening 15 of the wiring layer 12 is improved, and the electrical stability of the wiring layer 12 can be improved.

Next, a method for manufacturing the semiconductor device 10 shown in FIG. 1 will be described.
In the method for manufacturing a semiconductor device of the present invention, an insulating resin layer 11 having a first opening 11a provided at a position corresponding to the electrode 2 is formed on a semiconductor substrate 1 provided with an electrode on one side. A1 step, A2 step of forming a seed layer 12a on the insulating resin layer 11, and A3 step of forming a resist layer 14 provided with a second opening 15 having a taper 15a on the seed layer 12a. A4 step of forming a plating layer (wiring layer 12) on the seed layer 12a and A5 step of removing the resist layer 14 and the exposed seed layer 12a are sequentially provided.

  In the present invention, when the wiring layer 12 (plating layer) is formed by plating, the opening 15 provided in the resist layer 14 formed in the previous step has a taper 15a. Thereby, since the corner part by the resist layer 14 and the wafer surface becomes wide at the time of plating, it becomes easy for a plating solution to enter, and plating defects can be reduced. As a result, the disconnection failure in the vicinity of the opening 15 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

A method for manufacturing a semiconductor device according to the present invention (first embodiment) will be described with reference to FIGS.
First, as shown in FIG. 2A, a semiconductor substrate 1 having an integrated circuit (not shown), an electrode 2 and a passivation film 3 is prepared. As described above, in this semiconductor substrate 1, the electrode 2 and the passivation film 3 are formed on one surface of the base material 1 a, and the opening 4 is provided in the passivation film 3 at a position aligned with the electrode 2. It is a semiconductor wafer. The passivation film 3 is formed by, for example, LP-CVD, and the film thickness is, for example, 0.1 to 0.5 μm.

  Next, as shown in FIG. 2B, an insulating resin layer 11 having an opening (first opening) 11a is formed on the passivation film 3 of the semiconductor substrate 1 [Step A1]. The thickness is, for example, 5 to 50 μm.

  Such an insulating resin layer 11 is formed by, for example, forming a film made of the above resin on the entire surface of the passivation film 3 by, for example, a spin coating method, a printing method, or a laminating method, and then performing patterning using, for example, a photolithography technique. It can be formed by forming the opening 11a at a position aligned with the electrode 2.

  Next, as shown in FIG. 2C, a thin seed layer 12a for electrolytic plating is formed on the entire surface of the insulating resin layer 11 or a necessary region by a sputtering method or the like [Step A2]. The seed layer 12a is, for example, a laminated body made of a Cu layer and a Cr layer formed by a sputtering method, or a laminated body made of a Cu layer and a Ti layer. Further, it may be an electroless Cu plating layer, a metal thin film layer formed by a vapor deposition method, a coating method, a chemical vapor deposition method (CVD), or the like, or a combination of the above metal layer forming methods. Good.

  Next, as shown in FIG. 2D, a resist layer 14 for electrolytic plating is formed on the seed layer 12a [Step A3]. The resist layer 14 is provided with an opening (second opening) 15 in a region where the wiring layer 12 is to be formed (position aligned with the electrode 2 on the semiconductor substrate 1). In the opening 15, the seed layer 12a is formed. Leave exposed. The resist layer 14 can be formed by, for example, patterning using a photolithography technique, a method of laminating a film resist, a method of spin-coating a liquid resist, or the like.

  Here, in the present invention, the opening 15 provided in the resist layer 14 has a taper 15a. As a result, in step A4 described later, the corners formed by the resist layer 14 and the wafer surface are widened during plating, so that the plating solution can easily enter the corners formed by the resist layer 14 and the wafer surface, thereby reducing plating defects. . As a result, the disconnection failure in the vicinity of the opening 15 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

  In addition, it is preferable to control so that angle (theta) which the inclined surface which makes the said taper 15a, and another flat surface makes becomes 45 degrees or more and 85 degrees or less. If the angle θ is smaller than 45 °, the wiring layer 12 formed by plating has a large constriction, and the sealing resin layer 13 formed in a subsequent process becomes difficult to enter. Therefore, the sealing resin layer 13 There is a risk of forming defects. Or the intensity | strength of the wiring layer 12 falls by the constriction. On the other hand, when the angle θ is larger than 85 °, the plating solution is difficult to enter, so that there is a possibility of causing a plating failure.

  Next, as shown in FIG. 3A, a Cu plating layer as the wiring layer 12 is formed by electrolytic copper plating on the exposed seed layer 12a using the resist layer 14 as a mask [Step A4]. Through the above steps, a wiring path (circuit pattern) made of a Cu plating layer is formed on the Si wafer. The thickness of the Cu plating layer is, for example, 5 to 50 μm. Thereafter, for example, a Ni plating layer and an Au plating layer may be formed on the Cu plating layer in order to improve the wettability of solder bumps to be formed thereafter.

  At this time, since the opening 15 of the resist layer 14 has a taper 15a, the corner portion formed by the resist layer 14 and the wafer surface becomes wide, so that the plating solution can easily enter the corner portion formed by the resist layer 14 and the wafer surface. Thus, plating defects can be reduced. As a result, the disconnection failure in the vicinity of the opening 15 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

  Next, as shown in FIG. 3B, after the wiring layer 12 is formed in a desired region, the unnecessary resist layer 14 and seed layer 12a are removed by etching, and the region other than the region where the wiring layer 12 is formed. The insulating resin layer 11 is exposed at the portion [Step A5].

Next, as shown in FIG. 3C, an insulating sealing resin layer 13 having an opening (not shown) for outputting a terminal to the outside is formed on the wiring layer 12. The thickness is, for example, 10 to 150 μm.
Such a sealing resin layer 13 can form the sealing resin layer 13 having an opening at a desired position, for example, by patterning a photosensitive resin such as a photosensitive polyimide resin by a photolithography technique. . In addition, the formation method of the sealing resin layer 13 is not limited to this method.

  Thereafter, for example, solder bumps may be formed in the openings of the sealing resin layer 13 as necessary. Examples of the solder bump forming method include a plating method, a printing method, a metal jet method, and a method of placing a solder ball.

  In the semiconductor device 10 formed as described above, when the wiring layer 12 is formed by plating, the opening 15 provided in the resist layer 14 formed in the preceding process has a taper 15a. As a result, the corners formed by the resist layer 14 and the wafer surface are widened at the time of plating, so that the plating solution easily enters the corners formed by the resist layer 14 and the wafer surface, and plating defects can be reduced. As a result, the disconnection failure in the vicinity of the opening 15 of the wiring layer 12 is improved, and the electrical stability of the wiring layer 12 can be improved.

  Here, the angle θ formed between the tapered inclined surface and the other flat surface in the opening of the resist layer is set to 45 °, and the semiconductor device is manufactured by the above-described method. It was confirmed by measurement. As a result, no plating failure was confirmed, and when a moisture absorption reflow test was performed under the conditions of 85 ° C. and RH 85%, no peeling was observed.

  Further, an angle θ formed by the tapered inclined surface and the other flat surface in the opening of the resist layer is set to 85 °, and a semiconductor device is similarly manufactured. By observing the cross section of the semiconductor device and measuring a resistance value, confirmed. As a result, no plating failure was confirmed, and when a moisture absorption reflow test was performed under the conditions of 85 ° C. and RH 85%, no peeling was observed.

Thus, in the resist layer for forming the wiring layer by plating, the opening has a tapered shape, and the angle θ between the inclined surface and the other flat surface is 45 ° or more and 85 ° or less. Thus, the wiring layer can be formed without causing plating defects. Further, the problem that the seed layer residue remains is eliminated, and adhesion between the wiring layer, the insulating resin layer, and the sealing resin layer can be obtained, and no problem occurs in the subsequent reliability test.
<Second embodiment>

    Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a cross-sectional view showing an example of a semiconductor device manufactured according to the present invention.
In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description of common parts is omitted.
The semiconductor device 30 is provided so as to cover the insulating resin layer 11 provided on the passivation film 3 of the semiconductor substrate 1, the wiring layer 12 provided on the insulating resin layer 11, and the wiring layer 12. And a sealing resin layer 13.

  And in this semiconductor device 30, when the wiring layer 12 is formed by plating, the opening 21 provided in the first resist layer 20 formed in the previous step is tapered, as will be described later with respect to the manufacturing method thereof. 21a. Thereby, since the corner part by the 1st resist layer 20 and the wafer surface becomes wide at the time of plating, it becomes easy for a plating solution to enter into the corner part by the 1st resist layer 20 and the wafer surface, and plating defects can be reduced. As a result, a disconnection failure in the vicinity of the opening 21 of the wiring layer 12 is improved, and the electrical stability of the wiring layer 12 can be improved.

Next, a method for manufacturing the semiconductor device 30 shown in FIG. 4 will be described.
In the method of manufacturing a semiconductor device according to the present invention, an insulating resin layer 11 having a first opening 11a provided at a position corresponding to an electrode 2 is formed on a semiconductor substrate 1 provided with an electrode 2 on one surface side. B1 step, B2 step of forming the first resist layer 20 provided with the second opening 21 having the taper 21a on the insulating resin layer 11, and the insulating resin layer 11 and the first resist layer 20 B3 step of forming the seed layer 12a on the surface, B4 step of forming the second resist layer 22 on the seed layer 12a at a position corresponding to the first resist layer 20, and plating on the seed layer 12a A B5 step of forming a layer (wiring layer 12) and a B6 step of removing the first resist layer 20 and the second resist layer 22 are sequentially provided.

  In this invention, when forming the said wiring layer 12 (plating layer) by plating, the opening part 21 provided in the 1st resist layer 20 formed in the front process shall have the taper 21a. Thereby, since the corner | angular part by the 1st resist layer 20 and a wafer surface becomes wide at the time of metal plating, it becomes easy to enter a plating solution and can reduce a plating defect. As a result, the disconnection failure in the vicinity of the opening 21 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

A method for manufacturing a semiconductor device according to the present invention (second embodiment) will be described with reference to FIGS.
First, as shown in FIG. 5A, a semiconductor substrate 1 having an integrated circuit (not shown), an electrode 2 and a passivation film 3 is prepared.

  Next, as shown in FIG. 5B, an insulating resin layer 11 having an opening (first opening) 11a is formed on the passivation film 3 of the semiconductor substrate 1 [Step B1].

  Next, as shown in FIG. 5C, the first resist layer 20 is formed on the insulating resin layer 11 [Step B2]. The first resist layer 20 is provided with an opening (second opening) 21 in a region where the wiring layer 12 is to be formed (position aligned with the electrode 2 on the semiconductor substrate 1).

  Here, in the present invention, the opening 21 provided in the first resist layer 20 has a taper 21a. As a result, in step B5, which will be described later, the corners formed by the first resist layer 20 and the wafer surface are widened during plating, so that the plating solution can easily enter the corners formed by the first resist layer 20 and the wafer surface, thereby reducing plating defects. can do. As a result, a disconnection failure in the vicinity of the opening 21 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

  In addition, it is preferable to control so that angle (theta) which the inclined surface which makes the said taper 21a, and another flat surface makes may be 45 degrees or more and 85 degrees or less. If the angle θ is smaller than 45 °, the wiring layer 12 formed by plating has a large constriction, and the sealing resin layer 13 formed in a subsequent process becomes difficult to enter. Therefore, the sealing resin layer 13 There is a risk of forming defects. Or the intensity | strength of the wiring layer 12 falls by the constriction. On the other hand, when the angle θ is larger than 85 °, the plating solution is difficult to enter, so that there is a possibility of causing a plating failure.

  Next, as shown in FIG. 5D, a thin seed layer 12a for electrolytic plating is formed on the entire surface of the first resist layer 20 or in a necessary region by sputtering or the like [Step B3].

  Next, as shown in FIG. 6A, a second resist layer 22 is formed on the seed layer 12a [Step B4]. The second resist layer 22 is provided with an opening 23 in a region where the wiring layer 12 is to be formed (position aligned with the electrode 2 on the semiconductor substrate 1), and the seed layer 12a is exposed in the opening 23. deep.

  Here, it is preferable that the opening 23 provided in the second resist layer 22 has a taper 23 a similarly to the opening 21 in the first resist layer 20.

  Next, as shown in FIG. 6B, a Cu plating layer, which is the wiring layer 12, is formed by electrolytic copper plating on the exposed seed layer 12a using the second resist layer 22 as a mask [Step B5].

  At this time, since the opening 21 of the first resist layer 20 has the taper 21a, the corners of the first resist layer 20 and the wafer surface are widened. It becomes easy for the plating solution to enter the substrate, and plating defects can be reduced. As a result, the disconnection failure in the vicinity of the opening 21 of the wiring layer 12 is improved, and the wiring layer 12 having excellent electrical stability can be formed.

  Next, as shown in FIG. 6C, after the wiring layer 12 is formed in a desired region, unnecessary first resist layer 20, second resist layer 22 and seed layer 12a are removed by etching, and the wiring layer The insulating resin layer 11 is exposed in a portion other than the region where 12 is formed [Step B6].

  Next, as shown in FIG. 6D, an insulating sealing resin layer 13 having an opening (not shown) for outputting a terminal to the outside is formed on the wiring layer 12.

  Thereafter, for example, solder bumps may be formed in the openings of the sealing resin layer 13 as necessary.

  In the semiconductor device 20 formed as described above, when the wiring layer 12 is formed by plating, the opening 21 provided in the first resist layer 20 formed in the preceding process has a taper 21a. Yes. Thereby, since the corner part by the 1st resist layer 20 and the wafer surface becomes wide at the time of plating, it becomes easy for a plating solution to enter into the corner part by the 1st resist layer 20 and the wafer surface, and a plating defect can be reduced. As a result, a disconnection failure in the vicinity of the opening 21 of the wiring layer 12 is improved, and the electrical stability of the wiring layer 12 can be improved.

  Here, the angle θ formed between the tapered inclined surface and the other flat surface in the opening of the resist layer is set to 45 °, and the semiconductor device is manufactured by the above-described method. It was confirmed by measurement. As a result, no plating failure was confirmed, and when a moisture absorption reflow test was performed under the conditions of 85 ° C. and RH 85%, no peeling was observed.

  Further, an angle θ formed by the tapered inclined surface and the other flat surface in the opening of the resist layer is set to 85 °, and a semiconductor device is similarly manufactured. By observing the cross section of the semiconductor device and measuring a resistance value, confirmed. As a result, no plating failure was confirmed, and when a moisture absorption reflow test was performed under the conditions of 85 ° C. and RH 85%, no peeling was observed.

  Thus, in the resist layer for forming the wiring layer by plating, the opening has a tapered shape, and the angle θ between the inclined surface and the other flat surface is 45 ° or more and 85 ° or less. Thus, the wiring layer can be formed without causing plating defects. Further, the problem that the seed layer residue remains is eliminated, and adhesion between the wiring layer, the insulating resin layer, and the sealing resin layer can be obtained, and no problem occurs in the subsequent reliability test.

  In particular, in this embodiment, the resist layer has a two-layer structure with the seed layer interposed therebetween, so that the seed layer is not formed on the insulating resin layer other than the pattern. Thereby, the seed layer residue is not left between the insulating resin layer and the sealing resin layer formed thereon, and the adhesiveness between the two layers is maintained. Further, plating defects can be reduced. In addition, by tapering the opening of the first resist layer, when the seed layer is formed by sputtering or the like, the seed layer is formed up to the corner by the first resist layer and the wafer surface. The problem that a defect is caused by the formation of a later wiring layer is eliminated. As a result, the electrical stability of the wiring layer can be further improved.

  The semiconductor device manufacturing method of the present invention has been described above. However, the present invention is not limited to the above-described example, and can be appropriately changed as necessary.

  The present invention can be applied to a method for manufacturing a semiconductor device including a wiring layer formed by plating.

It is sectional drawing which shows an example of the semiconductor device which concerns on this invention. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view sequentially illustrating processes following FIG. 2. It is sectional drawing which shows another example of the semiconductor device which concerns on this invention. FIG. 5 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 4 in order of steps. FIG. 6 is a cross-sectional view sequentially illustrating processes subsequent to FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Electrode, 3 Passivation film, 4 Opening part, 10, 30 Semiconductor device, 11 Insulating resin layer, 11a Opening part, 12 Wiring layer, 12a Seed layer, 13 Sealing resin layer, 14 Resist layer, 15 Opening Part, 15a taper, 20 first resist layer, 21 opening part, 21a taper, 22 second resist layer, 23 opening part, 23a taper.

Claims (4)

Forming an insulating resin layer provided with a first opening at a position corresponding to the electrode on a semiconductor substrate provided with an electrode on one side;
A2 step of forming a seed layer on the insulating resin layer;
Forming a resist layer provided with a second opening having a taper on the seed layer; and
A4 step of forming a plating layer on the seed layer;
A method of manufacturing a semiconductor device comprising: an A5 step of removing the resist layer and the exposed seed layer in order.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step A <b> 3, the tapered inclined surface is controlled to be within a range of 45 to 85 ° with respect to another flat surface. B1 step of forming an insulating resin layer provided with a first opening at a position corresponding to the electrode on a semiconductor substrate provided with an electrode on one surface side;
B2 step of forming a first resist layer provided with a tapered second opening on the insulating resin layer;
B3 step of forming a seed layer on the insulating resin layer and the first resist layer;
B4 step of forming a second resist layer on the seed layer at a position corresponding to the first resist layer;
B5 step of forming a plating layer on the seed layer;
B6 process of removing said 1st resist layer and said 2nd resist layer in order, The manufacturing method of the semiconductor device characterized by the above-mentioned. 4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the step B <b> 2, the tapered inclined surface is controlled to be within a range of 45 to 85 ° with respect to another flat surface.

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