JP2006303036A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress interlayer peeling in a boundary between a rewiring layer and an insulating resin layer and/or a sealing resin layer without changing the material quality of the rewiring layer in WLCSP or the like. <P>SOLUTION: The semiconductor device 2 is provided with an electrode 20 on a semiconductor substrate 10, an external terminal 50 which is electrically connected with the electrode 20 by means of a rewiring layer 40, and a sealing resin layer 60 packaging a side where the electrode 20 of the semiconductor substrate 10 and the rewiring layer 40 are formed. The rewiring layer 40 is provided with a terminal base 41 as the base of the external terminal 50, and a routing wiring 42 which is routed from the electrode 20 to connect the electrode 20 with the terminal base 41. The routing wiring 42 is partly formed just above the electrode 20, the remaining part is insulated from the electrode 20 by means of an insulating resin layer 30, and the sealing resin layer 60 is formed of such a pattern that absorbs stress generating between the layers due to the expansion of the rewiring layer 40. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a wafer level (WL) CSP (Chip Size / Scale Package) that does not use a wiring board (interposer).

Conventionally, in the semiconductor package, peripheral terminal placement type with metal leads arranged on the side and periphery of the resin package such as Dual Inline Package and Quad Flat Package has been the mainstream. there were.
On the other hand, a chip size / scale package (CSP) capable of high-density mounting has been proposed and put into practical use. The CSP is an application of so-called ball grid array (BGA) technology, and is a leadless semiconductor package having a structure (BGA structure) in which a plurality of electrodes are arranged in a square shape or a lattice shape on the surface of the package. In the CSP having such a structure, the occupied area of the package can be reduced even if the number of electrode terminals is the same.

In recent years, a wafer level (WL) CSP has been proposed as a semiconductor package in which the CSP is further developed in order to achieve higher density mounting (see, for example, Patent Documents 1 and 2). An outline of a conventional WLCSP will be briefly described with reference to FIG. FIG. 8 is a cross-sectional view in the thickness direction.
In the illustrated WLCSP 100, an electrode 102, an insulating resin layer 103, a rewiring layer 104, and a sealing resin layer 105 are formed on a silicon wafer 101 that is a semiconductor substrate, and solder bumps 106 that are external terminals are connected to a rewiring layer. It is electrically connected to the electrode 102 through 104.
JP 2003-124244 A International Publication No. 00/77843 Japanese Patent Laid-Open No. 2001-210751

  In the above-described conventional WLCSP, in a so-called reflow process when attaching a solder bump as an external terminal, an environmental test (for example, a moisture absorption reflow test or a temperature cycle test) more severe than actual reflow process or actual use conditions, When exposed to moisture, a slight peeling portion may occur at the interface between the insulating resin layer and the rewiring layer or the interface between the rewiring layer and the sealing resin layer.

Most of the metal rewiring layer is sandwiched between two resin layers (an insulating resin layer and a sealing resin layer). Therefore, when heat is applied to the WLCSP, the interface between the insulating resin layer and the rewiring layer or the interface between the rewiring layer and the sealing resin layer, which are made of different materials, receives stress due to the difference in thermal expansion coefficient between these layers. When this stress increases, it is considered that a peeled portion is generated between the layers. Further, when moisture in the air enters the peeled portion, the penetrated moisture is vaporized and expanded by heat, so that the peeled portion is likely to spread.
When a peeled portion occurs at the interface between the insulating resin layer and the rewiring layer or the interface between the rewiring layer and the sealing resin layer, moisture enters the peeled portion, and the metal rewiring layer is oxidized, There is a risk of increased electrical resistance.

Patent Document 3 describes that the above-described delamination can be suppressed by forming the rewiring layer of a Cu / CuO ₂ composite alloy and reducing the linear expansion coefficient and elastic modulus of the rewiring layer. However, the Cu / CuO ₂ composite alloy has a larger electric resistance than Cu that is normally used, and when this is used, it is necessary to increase the wiring width of the rewiring layer. With the recent miniaturization of electronic devices, the semiconductor packages mounted thereon are also increasingly required to be miniaturized, and the use of Cu / CuO ₂ composite alloys that require an increase in the wiring width of the rewiring layer is Is not realistic.

  The present invention has been made in view of the above circumstances, and in a semiconductor device such as a WLCSP having an electrode, an insulating resin layer, a rewiring layer, an external terminal, and a sealing resin layer, the material of the rewiring layer is changed. It is another object of the present invention to provide a structure of a semiconductor device that suppresses delamination at an interface between a rewiring layer and an insulating resin layer and / or a sealing resin layer.

The inventor has intensively studied to solve the above-mentioned problems and invented the following semiconductor devices.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: an electrode; an external terminal electrically connected to the electrode through a rewiring layer; the electrode of the semiconductor substrate; and the rewiring layer. And the re-wiring layer is routed from the electrode, the terminal base being the base of the external terminal, and the electrode and the terminal base. In a semiconductor device in which a part of the routing wiring is formed immediately above the electrode and the rest is insulated from the electrode through an insulating resin layer.
The insulating resin layer and / or the sealing resin layer is a resin (A) that absorbs stress generated between layers due to expansion of the rewiring layer, or resin that suppresses stress generated between layers due to expansion of the rewiring layer. It is characterized by comprising (B).

  In the semiconductor device according to the first aspect of the present invention, the insulating resin layer and / or the sealing resin layer in contact with the rewiring layer is suppressed by the resin (A) that absorbs stress generated between the layers, or the generation of stress itself. Since the resin (B) is used, the stress generated between the rewiring layer and the insulating resin layer and / or the sealing resin layer is relieved, and the rewiring layer, the insulating resin layer and / or the sealing resin is relieved. Delamination at the interface with the layer can be suppressed.

A semiconductor device according to a second aspect of the present invention is characterized in that, in the first aspect, the resin (A) is a resin having a Young's modulus of 3 GPa or less.
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the resin (B) is a resin having a linear expansion coefficient equal to or less than that of the rewiring layer.
By using such a resin as the resin (A) or the resin (B), the semiconductor device according to the first aspect of the present invention can be suitably implemented.
In the present invention, “Young's modulus” is measured under the conditions of ASTM D882. The “linear expansion coefficient” is measured under the conditions of JIS K 7197.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising: an electrode; an external terminal electrically connected to the electrode through a rewiring layer; the electrode of the semiconductor substrate; and the rewiring layer. And the re-wiring layer is routed from the electrode, the terminal base being the base of the external terminal, and the electrode and the terminal base. In a semiconductor device in which a part of the routing wiring is formed immediately above the electrode and the rest is insulated from the electrode through an insulating resin layer.
The sealing resin layer is formed in a pattern that absorbs stress generated between layers due to expansion of the rewiring layer.

  In the semiconductor device according to claim 4 of the present invention, since the sealing resin layer is formed in a pattern that absorbs stress generated between the layers due to expansion of the rewiring layer, the rewiring layer and the sealing resin layer The stress generated between the two is relaxed, and delamination at the interface between the rewiring layer and the sealing resin layer can be suppressed.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the sealing resin layer is formed in a pattern having a hole portion that absorbs the stress in a non-formation region of the rewiring layer. It is characterized by.
By setting the sealing resin layer to such a configuration, the semiconductor device according to the fourth aspect of the present invention can be preferably implemented.

  According to the semiconductor device of the present invention, the insulating resin layer and / or the sealing resin layer in contact with the rewiring layer is made of resin (A) that absorbs stress generated between the layers, or resin (B) that suppresses generation of stress itself. Or the sealing resin layer is formed with a pattern that absorbs stress generated between the layers due to expansion of the rewiring layer. Therefore, the rewiring layer, the insulating resin layer, and / or the sealing resin layer Can be prevented from delamination at the interface.

  The present invention can be preferably applied to a semiconductor device such as a wafer level chip size / scale package (WLCSP). Therefore, an embodiment according to the present invention will be described using a WLCSP type semiconductor device as an example. The embodiments described below are specifically described so that the gist of the present invention can be easily understood, and the present invention is not limited to these embodiments. Further, the wiring pattern and the like are simplified from the actual ones for easy visual recognition.

“First Embodiment”
The first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing only a rewiring layer and external terminals, and FIG. 2 is a cross-sectional view of the semiconductor device (a cross-sectional view along the line AA ′ in FIG. 1).

As shown in FIG. 2, the WLCSP type semiconductor device 1 of the present embodiment has an integrated circuit (not shown) and a plurality of electrodes 20 electrically connected thereto on a semiconductor substrate 10 and overlaps the electrodes 20. An insulating resin layer 30 having a portion opened and formed on the entire surface of the semiconductor substrate 10, an external terminal 50 formed on the insulating resin layer 30 and electrically connected via the rewiring layer 40, and the semiconductor substrate 10 And a sealing resin layer 60 for resin-sealing the side on which the electrode 20 and the rewiring layer 40 are formed.
A configuration in which a passivation film (not shown) made of SiN or the like and having a pattern similar to that of the insulating resin layer 30 is provided between the semiconductor substrate 10 and the insulating resin layer 30 is preferable.

As the semiconductor substrate 10, a semiconductor wafer such as a silicon wafer is preferably used. The electrode 20 is made of a conductive material such as aluminum, copper, chromium, titanium, gold, or an alloy thereof. The thickness of the electrode 20 is, for example, about 0.3 to 1.5 [μm].
The insulating resin layer 30 is formed on substantially the entire surface of the semiconductor substrate 10 except just above the electrode 20. The thickness of the insulating resin layer 30 is, for example, about 5 to 50 μm.

   The redistribution layer 40 is made of a conductive material such as copper, chromium, aluminum, titanium, titanium-tungsten alloy, gold, and the like, as shown in FIG. 1 and FIG. A terminal base 41 having a shape and a routing wire 42 which is routed from the electrode 20 and connects the electrode 20 and the terminal base 41 are configured. As shown in FIG. 2, a part of the routing wiring 42 is formed immediately above the electrode 20, and the remaining part is insulated from the electrode 20 through the insulating resin layer 30. The thickness of the rewiring layer 40 is preferably 3 to 50 μm, and more preferably 5 to 30 [μm].

The external terminal 50 is made of a solder bump or the like, and a part thereof protrudes from the surface of the sealing resin layer 60. In the case of solder bumps, a high-density solder ball having a very small number of voids (for example, the number of voids per unit volume: about 1 × 10 ⁻⁷ to 2 × 10 ⁻⁷ [piece / μm ³ ]) is preferably used. Also, solder balls made of eutectic solder, high-temperature solder not containing lead, etc. are preferably used.
The sealing resin layer 60 protects the rewiring layer 40 and the like, and is formed over substantially the entire surface of the semiconductor substrate 10 excluding the region where the external terminals 50 are formed. The sealing resin layer 60 is made of an insulating resin, and the thickness is preferably 3 to 150 [μm].

In the present embodiment, the insulating resin layer 30 and / or the sealing resin layer 60 is made of a resin (A) that absorbs stress generated between the layers due to expansion of the rewiring layer 40.
Examples of the resin (A) include resins having a Young's modulus of 3 [GPa] or less. Conventionally, a resin having a Young's modulus of about 40 [GPa] is used, but in this embodiment, the insulating resin layer 30 and / or the sealing resin layer 60 are made of a resin having a lower Young's modulus than the conventional one.
The inventor has such a configuration, so that the insulating resin layer 30 and / or the sealing resin layer 60 absorb the stress generated between the layers due to the expansion of the rewiring layer 40, so that the rewiring layer 40 and the insulating resin It has been found that the stress generated between the layer 30 and / or the sealing resin layer 60 is relaxed and delamination can be suppressed.

  The lower limit of the Young's modulus of the resin (A) is not particularly limited. Although the kind of resin (A) is not restrict | limited, a polyimide resin etc. are preferable from a heat resistant point. Moreover, since the patterning of the insulating resin layer 30 is easy, a photosensitive resin is preferably used.

In the present embodiment, the insulating resin layer 30 and / or the sealing resin layer 60 are made of a resin (B) that suppresses stress generated between the layers due to expansion of the rewiring layer 40, instead of the resin (A). May be.
Examples of the resin (B) include resins having a linear expansion coefficient of the rewiring layer 40 or less. Since the linear expansion coefficient of the rewiring layer 40 is usually about 1.7 × 10 ⁻⁵ [1 / ° C.], the linear expansion coefficient of the resin (B) is 1.7 × 10 ⁻⁵ [1 / ° C.] or less. Is preferred.
In the case of such a configuration, the present inventor expands the insulating resin layer 30 and / or the sealing resin layer 60 only as much as or smaller than the rewiring layer 40 even if the rewiring layer 40 is thermally expanded. Therefore, it has been found that the generation of stress itself between the rewiring layer 40 and the insulating resin layer 30 and / or the sealing resin layer 60 is suppressed, and delamination can be suppressed.

  The lower limit of the linear expansion coefficient of the resin (B) is not particularly limited. The type of the resin (B) is not limited, but a polyimide resin or the like is preferable from the viewpoint of heat resistance. Moreover, since the patterning of the insulating resin layer 30 is easy, a photosensitive resin is preferably used.

In the present embodiment, the insulating resin layer 30 and / or the sealing resin layer 60 is generated between the resin (A) that absorbs stress generated between the layers due to the expansion of the rewiring layer 40 or between the layers due to the expansion of the rewiring layer 40. The stress generated between the rewiring layer 40 and the insulating resin layer 30 and / or the sealing resin layer 60 without changing the material of the rewiring layer 40 because the resin (B) suppresses the stress to be generated. Is relaxed, and delamination can be suppressed.
In the semiconductor device 1 of the present embodiment, for example, even if the moisture absorption reflow test is performed under the condition of temperature 85 [° C.] / Relative humidity 85 [%], the rewiring layer 40 and the insulating resin layer 30 and / or the sealing are performed. The delamination with the resin layer 60 is suppressed to a high level.

(Production method)
An example of the manufacturing method of the semiconductor device 1 of the first embodiment will be described.
First, an electrode material is formed on a substantially entire surface of the semiconductor substrate 10 by a vacuum deposition method, a sputtering method, or the like, and then patterned by a known photolithography method, so that an integrated circuit (illustrated) is formed at a predetermined position on the semiconductor substrate 10. And a plurality of electrodes 20 are formed.

Next, after depositing SiN or the like on substantially the entire surface of the semiconductor substrate 10 on which the electrode 20 is formed, a portion immediately above the electrode 20 is opened to form a passivation film (not shown).
Next, a photosensitive insulating resin is applied to substantially the entire surface of the semiconductor substrate 10 on which the electrode 20 is formed by spin coating, casting, dispensing, or the like, and this is exposed and developed, so that the portion directly above the electrode 20 is exposed. The opened insulating resin layer 30 is formed.
The insulating resin layer 30 can also be formed by screen printing or resin sheet lamination. In this case, patterning is not necessary.

Next, substantially the entire surface of the semiconductor substrate 10 on which the electrode 20 and the insulating resin layer 30 are formed becomes a seed for plating by vapor deposition, sputtering, CVD (chemical vapor deposition), electroless plating, or the like. A seed layer is formed. The seed layer preferably has a laminated structure such as Cu / Cr or Cu / Ti. A resist having a predetermined pattern is formed on the seed layer by photolithography, and electrolytic plating or electroless plating is performed using the resist as a mask to form a rewiring layer 40 having a predetermined pattern made of Cu or the like. . Thereafter, the resist is peeled off, and the seed layer remaining in the region where the rewiring layer 40 is not formed is etched away.
In forming the rewiring layer 40, for the purpose of improving the wettability of the external terminal 50 formed in a later step, Cu plating is performed, and then Ni plating and / or Au plating is further applied thereon, and the rewiring layer 40 is recycled. The wiring layer 40 can also be used.

Next, similarly to the insulating resin layer 30, a sealing resin layer 60 having a predetermined pattern is formed.
Finally, the external terminals 50 are formed by a solder ball mounting method, a solder plating method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, etc., and the semiconductor device 1 of the above embodiment is completed.

“Second Embodiment”
Next, a second embodiment will be described based on FIGS. FIG. 3 is a plan view showing only the rewiring layer and the external terminals, and FIG. 4 is a cross-sectional view of the semiconductor device (cross-sectional view taken along the line BB ′ in FIG. 3). The case where the structure which forms the multiple through-holes 61 along the periphery of is employ | adopted is shown. That is, in the semiconductor device 2 according to the second embodiment, as is apparent from FIG. 4, the through hole 61 is provided in a region (40α to 40α ′, 40β to 40β ′) where the rewiring layer 40 is arranged. It is an example arrange | positioned around this area | region.
Since the basic configuration of this embodiment is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted. 3 and 4 correspond to FIGS. 1 and 2 of the first embodiment, respectively. FIG. 3 also shows a pattern of through holes to be described later formed in the sealing resin layer.

  Unlike the first embodiment, the WLCSP type semiconductor device 2 of the present embodiment is not limited to the constituent resins of the insulating resin layer 30 and the sealing resin layer 60, and any resin can be used. The present embodiment is different from the first embodiment in that the sealing resin layer 60 is formed in a pattern that absorbs stress generated between layers due to expansion of the rewiring layer 40.

Specifically, as in the first embodiment, the sealing resin layer 60 is formed over substantially the entire surface of the semiconductor substrate 10 excluding the region where the external terminals 50 are formed. As shown in FIG. 4, the sealing resin layer 60 is formed in a pattern having a through hole (hole) 61 that penetrates the layer in the thickness direction in the non-formed region 43 of the rewiring layer. The lower end of the through hole 61 is connected to the insulating resin layer 30, and the upper end of the through hole 61 is open on the surface of the sealing resin layer 60.
As shown in the figure, a large number of the through holes 61 are formed in the sealing resin layer 60 over the entire non-formed region 43 of the rewiring layer. That is, the through-hole 61 is formed not only in the vicinity of each rewiring layer 40 but also between the adjacent rewiring layer 40 and the rewiring layer 40 in the rewiring layer non-formation region 43. Yes.

The through hole 61 can be formed by forming, for example, etching after forming a sealing resin layer similar to the conventional one without the through hole 61 (corresponding to the sealing resin layer of the first embodiment). .
The size of the through hole 61 is not particularly limited. However, the stress relaxation effect tends to increase as the size of the through hole 61 increases. Considering the ease of formation and the stress relaxation effect, the inner diameter of the through hole 61 is preferably 5 to 10 [μm], for example.

As described above, the inventor forms a large number of through holes (holes) 61 in the non-formation region 43 of the rewiring layer of the sealing resin layer 60, so that the through holes 61 are formed in the rewiring layer 40. It has been found that the stress generated between the rewiring layer 40 and the sealing resin layer 60 is absorbed by the expansion, the stress generated between the layers is relaxed, and delamination can be suppressed.
In the semiconductor device 2 of the present embodiment, for example, even if a moisture absorption reflow test is performed under the conditions of temperature 85 [° C.] / Relative humidity 85 [%], delamination between the rewiring layer 40 and the sealing resin layer 60 is performed. Is suppressed to a high level.

  The formation pattern of the through holes 61 is not limited to that described above, and the above effect can be obtained if at least one through hole 61 is formed in the vicinity of at least each rewiring layer 40. However, in order to effectively relieve the stress generated between the rewiring layer 40 and the sealing resin layer 60, the modification shown in FIGS. 5 and 6 may be used. FIG. 5 is a plan view showing only the rewiring layer and the external terminals, and FIG. 6 is a cross-sectional view of the semiconductor device (cross-sectional view taken along the line CC ′ of FIG. 5). The case where the structure which forms the multiple through-holes 61 along the periphery of is employ | adopted is shown. That is, as is apparent from FIG. 6, the semiconductor device 3 according to this modification is provided with through holes 61 in regions (40α to 40α ′, 40β to 40β ′) where the rewiring layer 40 is arranged. It is an example arrange | positioned around this area | region.

“Third Embodiment”
Next, a third embodiment will be described based on FIG. Since the basic configuration of this embodiment is the same as that of the second embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted.
FIG. 7 is a cross-sectional view of the semiconductor device according to the third embodiment corresponding to FIG. 4 of the second embodiment, and has a configuration in which a plurality of through holes 61 are formed along at least the periphery of each rewiring layer 40. The point of adopting is common. That is, in the semiconductor devices 4 and 5 according to the third embodiment, as is clear from FIG. 7, the through holes 61 are in regions (40α to 40α ′, 40β to 40β ′) where the rewiring layer 40 is arranged. Is an example of being arranged around this region.

  In the WLCSP type semiconductor device 3 of the present embodiment, as in the second embodiment, the constituent resins of the insulating resin layer 30 and the sealing resin layer 60 are not limited, and any resin can be used. In the present embodiment, similarly to the second embodiment, the sealing resin layer 60 is formed in a pattern that absorbs the stress generated between the layers due to the expansion of the rewiring layer 40. However, the pattern is different from that of the second embodiment.

Specifically, in the semiconductor devices 4 and 5 according to the present embodiment, as shown in FIG. 7, the sealing resin layer 60 is a substantially minimum region (the rewiring layer of the rewiring layer) that covers the surface and side surfaces of the rewiring layer 40. In the sealing resin layer 60, the rewiring layer non-formation region 43 is formed with an opening (hole) 62 over substantially the entire region. Yes.
The semiconductor device 4 shown in FIG. 7A is an example in which the wall surface of the opening 62 is inclined with respect to the surface of the semiconductor substrate 10, and the semiconductor device 5 shown in FIG. In this example, the wall surface 62 is substantially perpendicular to the surface of the semiconductor substrate 10, but the wall shape of the opening 62 may be arbitrary.
The patterning of the sealing resin layer 60 having the opening 62 can be performed, for example, by depositing a photosensitive resin on substantially the entire surface of the semiconductor substrate 10 and then exposing and developing in accordance with the pattern to be formed.

  The inventor forms the sealing resin layer 60 only in a substantially minimum region that covers the surface and side surfaces of the rewiring layer 40, and performs the second implementation in the non-forming region 43 of the rewiring layer of the sealing resin layer 60. Even in the configuration in which the opening (hole) 62 larger than the through-hole 61 of the embodiment is provided, the rewiring layer 40 and the sealing resin layer 60 are formed by the expansion of the rewiring layer 40 in the opening 62 as in the second embodiment. It is found that the stress generated between the layers is absorbed, the stress generated between the layers is relaxed, and delamination can be suppressed.

The formation pattern of the opening 62 is not limited to the above, and the opening 62 may be formed so that the remaining sealing resin layer 60 covers at least the surface and the side surface of the rewiring layer 40. Therefore, the formation area of the openings 62 may be smaller than that shown in the present embodiment, and a plurality of openings 62 may be provided between adjacent rewiring layers 40. However, the stress relaxation effect increases as the formation area of the opening 62 increases.
Since the insulating resin layer 30 is only exposed on the surface of the portion where the opening 62 is provided, the electrode 20 and the rewiring layer 40 are not exposed. Therefore, the semiconductor provided by the sealing resin layer 60 is provided by providing the opening 62. The protection function of the device 3 is not impaired.

  In the second and third embodiments, only the case where the through hole 61 or the opening 62 penetrating the sealing resin layer 60 is described, but a hole that does not penetrate the layer instead of the through hole 61 or the opening 62 is described. It is good also as a structure which provides. Also in this case, the hole portion absorbs stress, and the same effect as in the above embodiment can be obtained. However, considering the manufacturing process, the through hole 61 or the opening 62 of the above embodiment is preferable.

  According to the present invention, since delamination between the rewiring layer and the insulating resin layer and / or the sealing resin layer is suppressed, oxidation of the rewiring layer due to moisture penetrating the peeled portion, and the rewiring layer formed thereby An increase in electrical resistance or the like is suppressed, and a high-quality WLCSP type semiconductor device is provided.

  The present invention can be preferably applied to a WLCSP type semiconductor device, a high-density chip size semiconductor device with a narrower pitch than the WLCSP type, and the like.

1 is a partial plan view of a WLCSP type semiconductor device according to a first embodiment of the present invention. It is sectional drawing which follows the A-A 'line | wire of the WLCSP type semiconductor device shown in FIG. It is a fragmentary top view of the WLCSP type semiconductor device of a 2nd embodiment concerning the present invention. FIG. 4 is a cross-sectional view taken along line B-B ′ of the WLCSP type semiconductor device shown in FIG. 3. It is a fragmentary top view which shows the modification of the WLCSP type semiconductor device of 2nd Embodiment which concerns on this invention. FIG. 6 is a cross-sectional view taken along line C-C ′ of the WLCSP type semiconductor device shown in FIG. 5. It is sectional drawing of the WLCSP type semiconductor device of 3rd Embodiment which concerns on this invention. It is sectional drawing of the conventional WLCSP type semiconductor device.

Explanation of symbols

  1, 2, 3, 4, 5 Semiconductor device, 10 Semiconductor substrate, 20 Electrode, 30 Insulating resin layer, 40 Rewiring layer, 41 Terminal base (electrode pad), 42 Lead-out wiring, 43 Non-wiring area of rewiring layer 50 external terminals, 60 sealing resin layers, 61 through holes (holes), 62 openings (holes).

Claims (5)

On the semiconductor substrate, an electrode, an external terminal electrically connected to the electrode through a redistribution layer, and a resin-sealed side of the semiconductor substrate on which the electrode and the redistribution layer are formed A stop resin layer,
The redistribution layer includes a terminal base that is a base of the external terminal, and a routing wiring that is routed from the electrode and connects the electrode and the terminal base. Is formed immediately above the electrode, and the rest is insulated from the electrode through an insulating resin layer,
The insulating resin layer and / or the sealing resin layer is a resin (A) that absorbs stress generated between layers due to expansion of the rewiring layer, or resin that suppresses stress generated between layers due to expansion of the rewiring layer. A semiconductor device comprising (B). The semiconductor device according to claim 1, wherein the resin (A) is a resin having a Young's modulus of 3 GPa or less. The semiconductor device according to claim 1, wherein the resin (B) is a resin having a linear expansion coefficient equal to or less than that of the rewiring layer. On the semiconductor substrate, an electrode, an external terminal electrically connected to the electrode through a redistribution layer, and a resin-sealed side of the semiconductor substrate on which the electrode and the redistribution layer are formed A stop resin layer,
The redistribution layer includes a terminal base that is a base of the external terminal, and a routing wiring that is routed from the electrode and connects the electrode and the terminal base. Is formed immediately above the electrode, and the rest is insulated from the electrode through an insulating resin layer,
The semiconductor device, wherein the sealing resin layer is formed in a pattern that absorbs stress generated between layers due to expansion of the rewiring layer. The semiconductor device according to claim 4, wherein the sealing resin layer is formed in a pattern having a hole portion that absorbs the stress in a non-formation region of the rewiring layer.

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