JP2000323628A - Semiconductor device, manufacture thereof and electronic device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously satisfy stress alleviating and process matching and surely alleviate stress generated by thermal expansion coefficient difference from that of the mounting substrate, by introducing a function separating multilayer film structure including a stress alleviating resin layer having the stress alleviating function and a heat resistance resin layer having heat resistance. SOLUTION: A semiconductor device is electrically connected with a mounting substrate via a package electrode 7. The package electrode 7 is also electrically connected with an electrode 2 of the semiconductor element via a wiring 6. Under the wiring 6, a first resin layer 4 is provided and a second resin layer 5 is formed on the wiring 6. Between the first resin layer 4 and a semiconductor element 1, a passivation film 3 is provided. As the first resin layer 4, the photosensitive polyimide is used and, as the second resin layer 5, the denaturated epoxy resin is used. As a result, stress generated by expansion coefficient difference in the case where the semiconductor device is mounted on the mounting substrate can be alleviated with deformation of wiring 6, first resin layer 4 and second resin layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a wiring board (circuit board) and a method of manufacturing the same for electronic equipment in which an LSI is mounted on a substrate and functions. In particular, the present invention relates to a structure of a semiconductor element suitable for high-density mounting, a chip-size package with improved connection reliability, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a method of directly connecting an LSI to a wiring board, a method such as a wire bond (WB) or a tape automated bond (TAB) has been mainly used. In these systems, Au is flexible and easily deformed plastically.
It is characterized in that a thin wire or the like is used to connect between an external connection terminal of the LSI and a connection electrode on a wiring board. By having such a connection portion that is easily plastically deformed, a difference in thermal expansion between the LSI and the wiring board in a heating step at the time of connection and after the connection is absorbed by the deformation of the connection portion, and high connection reliability can be ensured. 1 prior art).

However, in the first prior art,
Due to the connection method itself, there is a problem that the external connection terminals of the LSI have no other option than to be arranged on the four sides of the LSI, and it is difficult to cope with an increase in the number of connection terminals of the LSI.

In order to solve the problem of the first prior art, the external connection terminals of the LSI are arranged in an area array, and a solder ball is provided between the external connection terminals of the LSI and the connection electrodes on the wiring board. A connection method has been proposed (second prior art).

In the second prior art, since the LSI and the wiring board are directly connected only by minute solder balls in an area array arrangement, there is an advantage that the mounting area does not need to be increased even if the number of connection terminals is increased. is there.

However, in the second prior art, L
Since the structure has a structure in which the difference in thermal expansion between the SI and the wiring board is absorbed only by the fine solder balls, the reliability of the connection portion is not always high. When the difference in thermal expansion between the LSI and the wiring board is large, the connection portion is broken due to displacement exceeding the plastic deformation limit of the solder ball, or the deformation is repeated even if the displacement is small even below the plastic deformation limit. This may cause fatigue destruction.

As a technique for improving the reliability of the connection portion by improving the disadvantages of the second conventional technique, a resin called an underfill resin is injected and cured into a space between the LSI and the wiring board to mount the LSI on the LSI. There is a method of fixing a substrate (hereinafter referred to as an LSI substrate fixed body). According to this technology, LSI
By fixing the substrate and the mounting substrate, the thermal stress is dispersed throughout the fixed body of the LSI substrate, the amount of distortion generated in the solder joint is averaged, and the destruction of the joint can be prevented (third conventional technique).

However, in the third prior art, since the underfill is filled from a small gap between the LSI and the substrate, it takes a long time to fill the underfill, the filling is not uniform over the whole, or the void is filled. (Underfill filling failure) (first problem in the third conventional technique).

In addition, as a result of the thermal stress in the creepage direction, which has been released in the form of plastic deformation of the solder joint, acting on the entire fixed body of the LSI substrate, the fixed body of the LSI substrate is also deformed in the thickness direction. Then, a phenomenon occurs in which the entire fixing body is warped. This deformation may cause a problem that the wiring in the substrate is easily broken or the element characteristics in the LSI fluctuate (second problem in the third conventional technique).

Further, in order to reduce the underfill filling defect (first problem in the third prior art), the filling operation is performed under different conditions depending on the shape and size of each LSI chip. When a large number of LSIs are mounted, there is also a problem that the operation becomes complicated (third problem in the third conventional technique).

In order to solve the problem of the third prior art, Japanese Patent Laid-Open No. 10-125705 proposes a technique of filling a sealing resin by a compression molding method (fourth prior art).

In this technique, since the LSI and the mounting board are mounted in a mold and the resin is compression-molded, underfill filling failure (the first problem in the third conventional technique) does not occur.

[0013] However, by fixing with a rigid resin so as to enclose the solder joint, the thermal stress is reduced by the LSI.
This is the same as the third prior art from the viewpoint of dispersing the solder over the entire substrate fixed body. Although the power of the semiconductor device according to any one of the above-described third prior arts is reduced, the solder balls according to the third prior art are reduced. There is no solution to the second problem.

As another technique for solving the problems of the second and third prior arts, JP-A-10-092865 discloses L.
After forming a thin film wiring composed of a resin layer, a wiring layer, and a resin layer on a passivation film of an SI, it is proposed to connect a connection electrode (package electrode) provided on the thin film wiring to a connection electrode on a mounting board. (Fifth prior art).

The first feature of the fifth prior art is that the joint between the LSI and the mounting board is composed of solder balls and thin film wiring, and a resin layer is arranged around the thin film wiring. It has become. By adopting such a structure, the difference in thermal expansion between the LSI and the wiring board is dispersed between the solder ball and the thin-film wiring, and the resin layer absorbs stress and impact. Problem) can be prevented. Further, since the LSI and the mounting board are not fixedly bonded, deformation of the LSI and the mounting board (a second problem in the third conventional technique) can be suppressed.

A second feature of the fifth prior art is that a thin film wiring composed of a first resin layer, a wiring layer and a second resin layer is formed on the passivation film before cutting the LSI into individual pieces. is there. Through such a manufacturing process, a plurality of LSI chips can be collectively processed on a wafer, and after separating the LSI chips into individual pieces, each LSI chip is filled with an underfill (in the third conventional technique). Third problem) There is no need.

From the foregoing, it has been found that the fifth prior art can substantially solve the problems of the first to fourth prior arts.

[0018]

SUMMARY OF THE INVENTION The present inventors have fundamentally solved the problem of connection reliability between a chip and a substrate, and have developed a chip and a chip manufacturing technology capable of high-density mounting with high connection reliability at a low cost. As a result of an independent study for the purpose of providing, it has been found that the fifth prior art has the following problems (1) to (7) and requires further contrivance.

(1) The step of forming an opening for exposing the semiconductor element electrode portion in the first resin layer formed on the passivation film is etching. JP 10-092865
In the publication, the first resin layer is described as being any one of a polyimide resin, an epoxy resin, and a silicone resin. However, since these are all thermosetting resins and have high chemical resistance, they are etched. Removal is not easy.

(2) An etching resist generally used does not have resistance to the conditions under which the first resin layer can be removed by etching. Therefore, in order to form a first resin layer having a desired opening, a resist is formed to be considerably thicker than the first resin layer, a multilayer resist method is used, or an etching resist of a special material is used. Such,
It is complicated and requires a long time and high cost.

(3) Since the first insulating layer is formed by etching, it is inevitable that the cross section of the opening has a wide upper end. When the upper end of the opening is widened, the distance between the opening and the adjacent opening becomes narrower, and insulation failure and short-circuiting easily occur.
There is also a problem that the positional accuracy requirement in the photolithography process of the etching resist becomes severe.

(4) In order to suppress the above problems (1) to (3), it is necessary to make the thickness of the first resin layer extremely small. However, making the first resin layer thin is an initial object of the invention. The stress relaxation function of the thin film wiring layer (and the resin layer) cannot be expected.

(5) JP-A-10-092865 states that stress is relieved by the first resin layer, the second resin layer, and the polyimide resin layer. However, LSI
The elastic modulus of (Si) or wiring (Cu) is about 100 times larger than that of the resin material. Therefore, even if these resin layers are present, the influence on the thermal expansion amount in the creeping direction of the LSI or wiring is negligible.
The difference in thermal expansion between the SI and the mounting board does not shrink.

(6) Conversely, since the first resin layer is formed below the thin film wiring layer, the first resin layer having a linear expansion coefficient several times larger than that of the wiring layer pushes up the package electrode in the thickness direction. This causes a new problem that the wiring layer is easily broken.

(7) As is clear from the above (1) to (6), in order to achieve the initial object of the invention, the first resin layer and the second resin layer used for the thin film wiring layer have a specific thickness. , Linear expansion coefficient, and cross-sectional shape, and have to have physical property values (heat resistance, workability) in a specific range compatible with the process.

An object of the present invention is to provide a low-cost semiconductor device which solves the problem of the fifth prior art and reliably reduces stress caused by a difference in thermal expansion with a mounting substrate, and a method of manufacturing the same. .

[0027]

In order to achieve the above object, according to the present invention, at least one resin layer is provided on a passivation film on a surface of a semiconductor element, and the inside of the resin layer and / or the surface of the resin layer are provided. In a semiconductor device having a conductor layer of a desired shape connected to the semiconductor element electrode portion, the resin layer is composed of at least two or more layers, and various components required as a thin film wiring structure are provided. It is proposed that the characteristics be shared by each layer. The functions required for the thin film wiring structure are various, but by devising a function-separating multilayer film structure including at least a stress relaxation resin layer having a stress relaxation function and a heat resistant resin layer having heat resistance. Thus, both the stress relaxation function and the process consistency can be achieved.

At this time, the stress relaxation resin layer included in the resin layer provided on the passivation film on the surface of the semiconductor element has an elastic modulus Er (Young's modulus; unit = Gpa) at 25 ° C. of a film thickness tr at 25 ° C. It is desirable that the resin be obtained such that Er / tr obtained by dividing by (unit = μm) is less than 3.0, and more desirably, Er / tr is 1.
It is less than 0. The reason that Er / tr increases beyond 3.0 is that at least the Young's modulus is large, the film thickness is small,
Is satisfied, but in any case, the ability to alleviate the stress on the wiring layer cannot be expected. Conversely, any resin capable of forming a stress relaxation layer having Er / tr of less than 1.0 does not cause any particular problem in the present invention, but has a Young's modulus E at room temperature (25 ° C.).
It is desirable that r be a resin having a range of 0.2 to 15.0 GPa. When a material having a Young's modulus at room temperature of less than 0.2 GPa is used, when using an electronic device including the semiconductor device as a component, even if a slight impact is applied to the housing, the resin portion causes vibration and the wiring position is reduced. Is displaced, and it becomes difficult to stabilize the electrical characteristics.
Conversely, a resin having a Young's modulus exceeding 15.0 GPa has a very small displacement following the stress and cannot be said to have a high stress relaxation function.

In the present invention, it is desirable that the thickness of the entire resin layer (total thickness t) is in the range of 6 to 250 μm. If the total thickness is less than 6 μm, the upper surface of the wiring layer may be exposed and corrosion may proceed. Conversely, if the film thickness exceeds 250 μm, it takes a long time to form the film and the uniformity of the film thickness cannot be maintained.

Further, in the present invention, the elongation at break of the resin layer of the above-mentioned function-separated multilayer structure is at least 5%
It is desirable that the content be at least 8%. If the elongation at break is less than 5%, there is a high risk of breaking when thermal stress is released due to deformation of the stress relaxation layer, or breaking due to impact during handling.

On the other hand, since the heat-resistant resin layer included in the resin layer provided on the passivation film needs to withstand at least heat during soldering, the glass transition temperature (T
g) or the melting point (mp) is desirably 100 ° C. or higher. The higher the Tg or mp, the less the denaturation during the process, but conversely, the processing becomes difficult or it becomes difficult to obtain, so Tg or mp
mp is desirably 400 ° C. or lower. Also, Tg
When a resin having a high temperature is used, the temperature difference between the stress-free point (Tg) and room temperature (about 25 ° C.) increases,
Conversely, thermal stress may increase, so that Tg or mp should not exceed 400 ° C. as much as possible.

In the present invention, the plurality of resin layers provided on the passivation film on the surface of the semiconductor element include an average Young's modulus Eave (unit: GPa; 25 ° C.) of the plurality of layers and an average linear expansion coefficient αave in the thickness direction. The product Eave × αave of (average value in the range of −55 to 150 ° C .; unit = ppm / ° C.) is 20.
The range is desirably from 400 to 400, and more desirably from 30 to 250. When the product of the Young's modulus and the coefficient of linear expansion exceeds 400, for example, when a resin having a Young's modulus of 4 Gpa and a coefficient of linear expansion of 150 ppm / ° C. is used, the resin itself has a large elongation in the creeping direction and the thin film Since the wiring is pushed from the side, the risk of disconnection increases. On the other hand, it is difficult to obtain a resin having a product of the Young's modulus and the coefficient of linear expansion of less than 20, so that a material having such physical properties causes an increase in cost.

In the present invention, the resin layer composed of a plurality of layers provided on the passivation film on the surface of the semiconductor element has a thickness of 25%.
And the average linear expansion coefficient αave in the film thickness direction (average value in the range of -55 to 150 ° C; unit =
(ppm / ° C) is preferably in the range of 200 to 40,000. Since the product of the film thickness and the coefficient of linear expansion is an index of the amount of thermal expansion of the resin layer in the non-wiring region, when this value exceeds the above range, the amount of deformation of the resin layer in the thickness direction increases, and the wiring increases. Is extended in the thickness direction, so that disconnection of the wiring is likely to occur. Conversely, a material having a value below the above range cannot be expected to have any stress relaxation function, and the original object of the present invention cannot be achieved.

In the present invention, at least one of the plurality of resin layers provided on the passivation film on the surface of the semiconductor element has photosensitivity and a thermal decomposition temperature (5% weight loss temperature) of 250. It is desirable that the temperature is not less than ° C. . By having photosensitivity, an opening can be formed at a desired position. If the pyrolysis temperature is 2
When a resin layer having a temperature lower than 50 ° C. is used, a step of forming an outer layer of the resin layer is limited.

In the present invention, the resin layer in contact with the passivation film among the plurality of resin layers provided on the passivation film on the surface of the semiconductor element is formed by a photolithography process in which an opening is formed at a desired position. Polyimide, the bottom of the opening completely covers the end of the semiconductor element electrode, and the angle between the bottom of the opening and the semiconductor element electrode is in the range of 100 to 150 degrees. Is desirable. Polyimide has a proven track record as a resin formed on a passivation film. Furthermore, by using polyimide having photosensitivity, a desired opening can be formed in the semiconductor element electrode portion with high accuracy and at low cost. However, when the required number of openings is small and strict positional accuracy is required, the openings may be formed by laser processing in the present invention.

In addition, since the bottom of the opening completely covers the end of the electrode, a highly reliable connection with the wiring layer can be achieved.

Further, the opening has a forward taper, and the bottom formed by the opening has an angle of 10 degrees with the semiconductor element electrode.
By being within the range of 0 to 150 degrees, reliable wiring connection can be ensured in a wiring forming process such as sputtering, vapor deposition, and plating. If the angle is less than 100 degrees, the wiring reliability tends to be low when wiring is formed in the process of sputtering, vapor deposition, and plating. Conversely, if it is larger than 150 degrees, the opening diameter at the upper portion of the resin layer becomes too large, and it is difficult to cope with high-density mounting as the object of the present invention.

The technique of the present invention is suitable for a semiconductor device, particularly a chip size package, and a manufacturing method thereof, but is not limited thereto, and may be applied to a ball grid array or the like. In addition, the above-described semiconductor device is a component for being incorporated into an electronic device by being connected to another wiring board,
Alternatively, it can be used as an electronic device itself.

According to the present invention, an inexpensive semiconductor device having high connection reliability, excellent electrical characteristics, and suitable for high-density mounting is obtained by forming a resin layer having the above-described characteristics on a semiconductor device. A high-performance electronic device can be provided by appropriately connecting such a semiconductor device to another wiring board by soldering.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 1 shows a part of a cross section of a semiconductor device according to an embodiment of the present invention, in which a semiconductor element electrode part, a wiring drawn out therefrom, a package electrode part, and the periphery thereof are shown. 3 shows a cross-sectional structure. Hereinafter, the structure of the present embodiment will be described with reference to the drawings.

The semiconductor device of this embodiment is electrically connected to the mounting substrate through the package electrode 7. The package electrode 7 is electrically connected to the semiconductor element electrode section 2 by the wiring 6. A first resin layer is provided below the wiring 6,
A second resin layer is formed on the wiring 6. A passivation film 3 exists between the first resin layer and the semiconductor element.

In this embodiment, the first resin layer has a photosensitive polyimide (elastic modulus at room temperature = 3.0 GPa, −55 to 15
Average linear expansion coefficient in 0 ° C. range = 40 ppm / ° C., glass transition temperature> 300 ° C., elongation at break = 20%, film thickness 12 μ
m), a modified epoxy resin (modulus of elasticity at room temperature = 2.2 Gpa, average linear expansion coefficient in the range of −55 to 150 ° C. = 120 ppm / ° C.), glass transition point = 120 ° C., elongation at break = 9 %, Thickness 3 μm), the total thickness of the resin layer is about 15 μm, and the average elastic modulus is about 2.8 GP.
a, The linear expansion coefficient is about 60 ppm / ° C.

An opening 8 is formed in the first resin layer by a photolithography process, and an angle 9 formed by the opening 8 and the semiconductor element electrode is 110 degrees.

When the semiconductor device of this embodiment is mounted on a mounting board, the stress generated by the difference in expansion between the board and the semiconductor device can be reduced by deforming the wiring, the first resin layer, and the second resin layer.

[0046]

According to the present invention, an inexpensive semiconductor device having high connection reliability and excellent electrical characteristics and suitable for high-density mounting can be obtained. By connecting with a solder, high-performance electronic equipment can be provided.

[Brief description of the drawings]

FIG. 1 is a part of a schematic sectional view of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

1. Semiconductor element 2. 2. Semiconductor element electrode part 3. Passivation film First resin layer 5. Second resin layer 6. Wiring 7. 7. Package electrode 8. Opening in first resin layer Angle formed by the opening in the first resin layer and the semiconductor element electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuko Ito 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. 4M109 AA02 BA03 ED03 EE02 EE03

Claims (11)

[Claims] A resin layer is provided on a passivation film on a surface of a semiconductor element, and a conductor layer of a desired shape connected to the semiconductor element electrode portion is provided inside the resin layer and / or on the surface of the resin layer. 2. A semiconductor device according to claim 1, wherein the resin layer is composed of two or more layers including at least a stress relaxation resin layer having a stress relaxation function and a heat resistant resin layer having heat resistance. 2. The semiconductor device according to claim 1, wherein the stress relaxation resin layer included in the resin layer provided on the passivation film on the surface of the semiconductor element has an elastic coefficient Er (Young's modulus; unit = GPa) at 25 ° C. =) Divided by the film thickness tr (unit = μm) at 25 ° C.
Is a resin whose is less than 1.0. 3. The semiconductor device according to claim 1, wherein the heat-resistant resin layer included in the resin layer provided on the passivation film on the surface of the semiconductor element has a glass transition temperature (Tg) or a melting point (mp) of 100 to 100. A semiconductor device comprising a resin in a temperature range of 400 ° C. 4. The semiconductor device according to claim 1, wherein the resin layer comprising a plurality of layers including a stress relaxation resin layer and a heat resistant resin layer provided on the passivation film on the surface of the semiconductor element further comprises a resin layer at 25 ° C. Elongation at break of at least 6%
A semiconductor device comprising the above resin layer. 5. The semiconductor device according to claim 1, wherein the resin layer comprising a plurality of layers provided on the passivation film on the surface of the semiconductor element has a total thickness t at 25 ° C. of 6 to 250 μm. A semiconductor device characterized by being in a range. 6. The semiconductor device according to claim 1, wherein the plurality of resin layers provided on the passivation film on the surface of the semiconductor element comprise an average Young's modulus Eave (unit) in the thickness direction of the plurality of layers. = Gpa; 25 ° C) and the average linear expansion coefficient αave in the film thickness direction (average value in the range of -55 to 150 ° C; unit = ppm / ° C) Eave x αave is 20 to 4
A semiconductor device having a range of 00. 7. The semiconductor device according to claim 1, wherein the plurality of resin layers provided on the passivation film on the surface of the semiconductor element have a total film thickness t (unit: μm) at 25 ° C. And average coefficient of linear expansion αave in the film thickness direction
(Average value in the range of −55 to 150 ° C .; unit = ppm / ° C.)
And the product t × αave in the range of 200 to 40,000. 8. The semiconductor device according to claim 1, wherein at least one of a plurality of resin layers provided on the passivation film on the surface of the semiconductor element has photosensitivity and heat. A semiconductor device having a decomposable temperature (5% weight loss temperature) of 250 ° C. or higher. 9. The semiconductor device according to claim 1, wherein a resin layer in contact with the passivation film among a plurality of resin layers provided on the passivation film on the surface of the semiconductor element is formed by photolithography. A photosensitive polyimide in which an opening is formed at a desired position by a process, wherein the bottom of the opening completely covers the end of the semiconductor element electrode, and the bottom of the opening is located between the semiconductor element electrode and the semiconductor element electrode. A semiconductor device, wherein the angle formed by the angle is in the range of 100 to 150 degrees. 10. A chip size package having the configuration according to claim 1. 11. An electronic apparatus, wherein the semiconductor device according to claim 1 or the chip size package according to claim 10 is connected to another wiring board.