JP4844216B2 - Multilayer circuit wiring board and semiconductor device - Google Patents

Multilayer circuit wiring board and semiconductor device Download PDF

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JP4844216B2
JP4844216B2 JP2006121841A JP2006121841A JP4844216B2 JP 4844216 B2 JP4844216 B2 JP 4844216B2 JP 2006121841 A JP2006121841 A JP 2006121841A JP 2006121841 A JP2006121841 A JP 2006121841A JP 4844216 B2 JP4844216 B2 JP 4844216B2
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wiring board
multilayer circuit
reinforcing
circuit wiring
semiconductor element
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JP2007294724A (en
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正孝 前原
清智 中村
美保 生稲
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Toppan Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

本発明は、半導体集積回路素子を搭載する多層回路配線基板、多層回路配線基板に半導体集積回路素子を搭載した半導体装置に関する。   The present invention relates to a multilayer circuit wiring board on which a semiconductor integrated circuit element is mounted, and a semiconductor device in which the semiconductor integrated circuit element is mounted on the multilayer circuit wiring board.

半導体大規模集積回路（ＬＳＩ）等の素子（以降、半導体素子とする）には、近年、動作速度がクロック周波数で１ＧＨｚに達するものが出現している。このような高周波数に対応する半導体子では、トランジスタの集積度が高く、入出力用の端子数が１０００個を越えることもある。ここで、多数の端子の半導体素子をプリント配線基板に実装する際には、半導体素子とプリント基板の間に多層回路配線基板を配置して、両者の電気的な接合を中継させることが知られている。多層回路配線基板は、プリント配線基板よりも非常に薄い層構造と、微細な配線ピッチからなる配線パターンとを有する。半導体素子との接合部には、半田バンプが設けられている。現在広く実用化されている多層回路配線基板としては、例えばＢＧＡ（Ball Grid Array）やＣＳＰ（Chip Size Package）等が挙げられる。   In recent years, elements such as semiconductor large-scale integrated circuits (LSIs) (hereinafter referred to as semiconductor elements) whose operating speed reaches 1 GHz in terms of clock frequency have appeared. In the semiconductor element corresponding to such a high frequency, the degree of integration of transistors is high, and the number of input / output terminals may exceed 1000. Here, when mounting a semiconductor element with a large number of terminals on a printed wiring board, it is known to arrange a multilayer circuit wiring board between the semiconductor element and the printed board and relay the electrical connection between them. ing. The multilayer circuit wiring board has a layer structure much thinner than the printed wiring board and a wiring pattern having a fine wiring pitch. Solder bumps are provided at the junction with the semiconductor element. Examples of multilayer circuit wiring boards that are currently in wide use include BGA (Ball Grid Array) and CSP (Chip Size Package).

多層回路配線基板に半導体素子を搭載する方法としては、半田リフロー装置を用いた方法が知られている。半田リフロー装置では、半導体素子と多層回路配線基板を精密に位置合わせした状態で装置内を搬送させる。装置内では、温度を２６０℃近辺まで昇温した後、常温に戻す。接合用に設けられた半田バンプは、高温で融解して多層回路配線基板と半導体素子の各々の所定の端子間を接合させる。そして、温度低下と共に溶融した半田バンプが固化して接合部が固定される。   As a method for mounting a semiconductor element on a multilayer circuit wiring board, a method using a solder reflow apparatus is known. In the solder reflow apparatus, the semiconductor element and the multilayer circuit wiring board are transported through the apparatus in a state where they are precisely aligned. In the apparatus, the temperature is raised to around 260 ° C. and then returned to room temperature. Solder bumps provided for bonding are melted at a high temperature and bonded between predetermined terminals of the multilayer circuit wiring board and the semiconductor element. Then, the molten solder bumps solidify with a decrease in temperature, and the joint portion is fixed.

ここで、最近では、更なる高密度実装や、高動作周波数化のため、ポリイミド樹脂フィルムなどのフレキシブルなフィルム状絶縁体に配線パターンを形成したものを積層して多層回路配線基板全体の厚さを薄くすると共に、層間接続長を短くすることにより高動作周波数化に対応させたものが開発されてきている。フィルム状絶縁体などを積層して配線パターンを形成した多層回路配線基板は、厚みが薄くて撓み易いので、スティフナーと呼ばれる金属板を接着して平坦化させている。スティフナーは、多層回路配線基板の外縁と略同等の外形を有し、半導体素子搭載箇所を連続して取り囲む矩形の枠形状を有する（例えば、特許文献１参照）。多層回路配線基板にポリイミド樹脂フィルムを用いた場合、スティフナーは、銅で製造することが多い。これは、銅の熱膨張係数がポリイミド樹脂の熱膨張係数と略等しく、半田リフロー工程で温度変化させたときの銅とポリイミド樹脂のそれぞれの変形量の不一致を抑制できるからである。
特開平８‐３１６３００号公報 Recently, for further high-density mounting and higher operating frequency, the thickness of the entire multilayer circuit wiring board is laminated by laminating a flexible film-like insulator such as a polyimide resin film with a wiring pattern. In order to cope with a higher operating frequency by reducing the thickness of the layer and shortening the interlayer connection length, a device has been developed. Since a multilayer circuit wiring board in which a wiring pattern is formed by laminating film-like insulators is thin and easily bent, a metal plate called a stiffener is bonded and flattened. The stiffener has an outer shape that is substantially the same as the outer edge of the multilayer circuit wiring board, and has a rectangular frame shape that continuously surrounds the semiconductor element mounting locations (see, for example, Patent Document 1). When a polyimide resin film is used for the multilayer circuit wiring board, the stiffener is often made of copper. This is because the thermal expansion coefficient of copper is substantially equal to the thermal expansion coefficient of the polyimide resin, and it is possible to suppress the mismatch between the deformation amounts of the copper and the polyimide resin when the temperature is changed in the solder reflow process.
JP-A-8-316300

ここで、半導体素子を配線基板に実装した際に生じる変形について、線膨張係数に着目して詳細に説明する。図８に半田リフロー中の変形挙動を示す。半導体素子の線膨張係数を約３ｐｐｍ／℃、有機材料で構成される配線基板の線膨張係数を約２１ｐｐｍ／℃とすると、一般的によく使われている鉛フリー半田の融点である２５℃から２２１℃までの温度差では、（２１−３）×（２２１−２５）＝３，５００ｐｐｍ以上の伸縮差が生じることになる。具体的には、２０ｍｍ角の半導体素子の接合領域では７０μｍの伸縮差となる。これらの事象が実際のリフロー工程中においてどのようにして多層回路配線基板の高さ方向の変形を引き起こすか、次に順を追って説明する。   Here, the deformation that occurs when the semiconductor element is mounted on the wiring board will be described in detail focusing on the linear expansion coefficient. FIG. 8 shows the deformation behavior during solder reflow. If the linear expansion coefficient of a semiconductor element is about 3 ppm / ° C., and the linear expansion coefficient of a wiring board made of an organic material is about 21 ppm / ° C., the melting point of a commonly used lead-free solder is 25 ° C. With a temperature difference up to 221 ° C., an expansion / contraction difference of (21-3) × (221-25) = 3,500 ppm or more occurs. Specifically, the expansion / contraction difference is 70 μm in the bonding region of the 20 mm square semiconductor element. How these events cause the deformation of the multilayer circuit wiring board in the height direction during the actual reflow process will be described step by step.

多層回路配線基板上に半導体素子を対応する端子同士の位置が合うように位置合わせ作業を行って載置する。半田の融点を越えるまでは接合は起こらないので、相互に干渉することなくそれぞれの線膨張係数に応じて膨張が起こる。半田の融点を越えると、多層回路配線基板と半導体素子のそれぞれ対応した端子が半田で接続される。半田は溶融状態になるので、図９の（ａ）に矢印で示すように、多層回路配線基板１００と半導体素子１０１の間に機械的干渉は発生していない。この状態から温度を低下させていき、半田１０２の融点を下回らせると、半田１０２が固化し始め、多層回路配線基板１００と半導体素子１０１の機械的干渉が生じ始める。特に、多層回路配線基板１００の厚さが薄くて半導体素子１０１と比べて弾性が小さい場合、端子が接合している領域の収縮性は、半導体素子１０１の収縮に拘束されて鈍化する。しかし、半導体素子１０１を実装していない面は、このような拘束を受けないので、多層回路配線基板１００の線膨張係数に応じて収縮が進む。その結果、図９の（ｂ）に矢印で示すように、多層回路配線基板１００の表側と裏側とで収縮差が発生する。このような収縮差を緩和するように、多層回路配線基板１００が半導体素子１０１の実装された表側がすり鉢状に凸になるように変形する。半導体素子１０１の変形量よりも多層回路配線基板１００の変形量の方が大きくなると、図９の（ｃ）に示すように半田１０２による接合部分に不良が生じる。   The semiconductor element is placed on the multilayer circuit wiring board by performing an alignment operation so that the corresponding terminals are aligned with each other. Since bonding does not occur until the melting point of the solder is exceeded, expansion occurs according to the respective linear expansion coefficients without interfering with each other. When the melting point of the solder is exceeded, the corresponding terminals of the multilayer circuit wiring board and the semiconductor element are connected by solder. Since the solder is in a molten state, no mechanical interference occurs between the multilayer circuit wiring board 100 and the semiconductor element 101 as indicated by an arrow in FIG. When the temperature is lowered from this state and the melting point of the solder 102 is lowered, the solder 102 begins to solidify and mechanical interference between the multilayer circuit wiring board 100 and the semiconductor element 101 begins to occur. In particular, when the multilayer circuit wiring board 100 is thin and less elastic than the semiconductor element 101, the shrinkage of the region where the terminals are joined is restrained by the shrinkage of the semiconductor element 101 and slows down. However, since the surface on which the semiconductor element 101 is not mounted is not subjected to such a restriction, the shrinkage proceeds according to the linear expansion coefficient of the multilayer circuit wiring board 100. As a result, as shown by arrows in FIG. 9B, a shrinkage difference occurs between the front side and the back side of the multilayer circuit wiring board 100. In order to reduce such a shrinkage difference, the multilayer circuit wiring board 100 is deformed so that the front side on which the semiconductor element 101 is mounted is convex in a mortar shape. If the deformation amount of the multilayer circuit wiring board 100 is larger than the deformation amount of the semiconductor element 101, a defect occurs in the joint portion by the solder 102 as shown in FIG.

このような変形は、多層回路配線基板と半導体素子の線膨張係数を一致させれば発生しない。しかしながら、線膨張係数は材料特有の物性値であるため、線膨張係数を合わせることは材料選択の幅を狭めることになるので好ましくない。
また、線膨張係数が異なる状態で、半導体素子の実装領域の平面度を確保する方法としては、特許文献１に開示されているように、矩形の枠状又はリング状の一体形の補強部材でひずみを集めることがあげられるが、ひずみが中央の半導体素子の実装領域に集中し易いので、十分な平面度を確保できなかった。 Such deformation does not occur if the linear expansion coefficients of the multilayer circuit wiring board and the semiconductor element are matched. However, since the linear expansion coefficient is a physical property value peculiar to the material, it is not preferable to match the linear expansion coefficient because the range of material selection is narrowed.
Further, as a method for ensuring the flatness of the mounting region of the semiconductor element in a state where the linear expansion coefficients are different, as disclosed in Patent Document 1, a rectangular frame-shaped or ring-shaped integrated reinforcing member is used. Although it is possible to collect strain, it is difficult to secure sufficient flatness because the strain tends to concentrate on the central semiconductor element mounting region.

さらに、半導体素子の端子数の増加と動作クロック周波数を向上させると、半導体デバイス側でのリーク電流を考慮する必要が生じる。このため、近年の半導体素子では、絶縁層に従来から用いられていたシリコン酸化膜（ｋ＝４．１）に代って、低誘電率材料（Ｌｏｗ−ｋ材料）が使用されるようになっている。
しかしながら、低誘電率材料を用いた絶縁膜は脆いので、半導体素子を多層回路配線基板したときに多層回路配線基板が大きく変形すると、絶縁膜が破壊されてしまうという可能性があった。多層回路配線基板が内層コアを有しない、フレキシブルなフィルム状絶縁体を絶縁層に用いたいわゆる薄型のコアレス基板である場合、熱履歴による変形が従来のプリント配線基板よりも大きくなる。このため、多層回路配線基板の変形によって半導体素子の端部が折れ曲がると多層回路配線基板の変形を追従できなくなって絶縁膜が破壊してしまい、その絶縁膜上の配線が断線してしまうことがある。このように、フィルム状絶縁体を絶縁層に用いた多層回路配線基板に低誘電率材料を絶縁層に用いた半導体素子を実装することは、困難であった。 Furthermore, when the number of terminals of the semiconductor element is increased and the operation clock frequency is improved, it is necessary to consider the leakage current on the semiconductor device side. For this reason, in recent semiconductor elements, a low dielectric constant material (Low-k material) has been used in place of the silicon oxide film (k = 4.1) conventionally used for the insulating layer. ing.
However, since the insulating film using the low dielectric constant material is fragile, there is a possibility that the insulating film is destroyed when the multilayer circuit wiring board is greatly deformed when the semiconductor element is formed into the multilayer circuit wiring board. When the multilayer circuit wiring board is a so-called thin coreless board that does not have an inner layer core and uses a flexible film-like insulator as an insulating layer, deformation due to thermal history becomes larger than that of a conventional printed wiring board. For this reason, if the end portion of the semiconductor element is bent due to the deformation of the multilayer circuit wiring board, the deformation of the multilayer circuit wiring board cannot be followed and the insulating film is destroyed, and the wiring on the insulating film may be disconnected. is there. Thus, it has been difficult to mount a semiconductor element using a low dielectric constant material as an insulating layer on a multilayer circuit wiring board using a film-like insulator as an insulating layer.

この発明は、このような事情に鑑みてなされたものであり、フレキシブルな多層配線回路基板に半導体素子を実装する際に、半導体素子側の絶縁膜の破壊を確実に防止できるようにすることである。   The present invention has been made in view of such circumstances, and is capable of reliably preventing the breakdown of the insulating film on the semiconductor element side when the semiconductor element is mounted on the flexible multilayer wiring circuit board. is there.

上記課題を解決するために、この発明は以下の手段を提案している。
本発明の多層回路配線基板は、フィルム状の絶縁層と配線層とを少なくとも１層ずつ備え、略矩形の半導体集積回路素子を搭載可能な多層回路配線基板であって、前記半導体集積回路素子を搭載する搭載領域として前記半導体集積回路素子と略同じ外形を有する矩形の領域を有し、前記搭載領域を区画する辺で平行な２辺の延長線の間であって前記搭載領域を挟む４つの位置のそれぞれに、補強部が独立して配置され、前記搭載領域の対角線の延長線上には前記補強部材を有しないことを特徴としている。 In order to solve the above problems, the present invention proposes the following means.
The multilayer circuit wiring board of the present invention is a multilayer circuit wiring board having at least one film-like insulating layer and a wiring layer, and capable of mounting a substantially rectangular semiconductor integrated circuit element. A mounting area to be mounted has a rectangular area having substantially the same outer shape as the semiconductor integrated circuit element, and is between four extension lines parallel to the side defining the mounting area and sandwiches the mounting area. A reinforcing portion is independently arranged at each position, and the reinforcing member is not provided on a diagonal extension of the mounting region .

また、上記の多層回路配線基板において、前記補強部は、前記搭載領域を区画する辺で平行な２辺の延長線の間に配置され、前記延長線と、前記延長線側の前記補強部の端部との間の距離は、前記延長線間の距離の０〜２５％の範囲内であることがより好ましい。
この多層回路配線基板では、補強部が搭載領域を区画する平行な２辺の延長線からはみ出すことなく配置される。延長線間の距離の０〜２５％の範囲であれば、搭載領域の変形を好適に抑制できる。 In the multilayer circuit wiring board, the reinforcing portion is disposed between two extension lines parallel to the side defining the mounting region, and the extension line and the reinforcement portion on the extension line side are arranged. The distance between the end portions is more preferably within a range of 0 to 25% of the distance between the extension lines .
In this multilayer circuit wiring board, the reinforcing portion is arranged without protruding from the extension lines of two parallel sides that define the mounting area. If it is in the range of 0 to 25% of the distance between the extension lines, deformation of the mounting area can be suitably suppressed.

また、上記の多層回路配線基板において、前記補強部において前記搭載領域に向かう端部から前記搭載領域までの距離は、１ｍｍから６ｍｍの範囲内であることがより好ましい。
この多層回路配線基板では、補強部が搭載領域に近接して配置される。搭載領域からの距離が１ｍｍから６ｍｍの範囲内であれば、搭載領域の変形を好適に抑制できる。 In the multilayer circuit wiring board, it is more preferable that the distance from the end portion toward the mounting region to the mounting region in the reinforcing portion is in the range of 1 mm to 6 mm .
In this multilayer circuit wiring board, the reinforcing portion is disposed close to the mounting area. If the distance from the mounting area is within the range of 1 mm to 6 mm, deformation of the mounting area can be suitably suppressed.

また、上記の多層回路配線基板において、前記補強部において前記搭載領域に向かう端部は直線状に形成され、前記端部は、前記搭載領域における前記端部に対向する辺に対する傾きが±２０°以内に設定されていることがより好ましい。
この多層回路配線基板では、補強部が搭載領域に対して略平行に配置される。補強部が搭載領域に対して傾斜して配置された場合でも、±２０°の範囲内であれば、搭載領域の変形を好適に抑制できる。 Further, in the multilayer circuit wiring board, an end portion of the reinforcing portion facing the mounting region is formed in a straight line, and the end portion has an inclination of ± 20 ° with respect to a side facing the end portion in the mounting region. More preferably, it is set within the range .
In this multilayer circuit wiring board, the reinforcing portion is arranged substantially parallel to the mounting area. Even when the reinforcing portion is disposed to be inclined with respect to the mounting area, the deformation of the mounting area can be suitably suppressed as long as it is within a range of ± 20 °.

また、上記の多層回路配線基板において、前記補強部として金属製の部材を有することがより好ましい。
この多層回路配線基板は、金属材料からなる補強部を有することで弾性を確実に高めることができる。このように金属材料からなる補強部は、検査用の電極などとして使用することも可能である。 Moreover, in the above multilayer circuit wiring board, it is more preferable to have a metal member as the reinforcing portion .
This multi-layer circuit wiring board has a reinforcing portion made of a metal material, so that the elasticity can be reliably increased. Thus, the reinforcement part which consists of metal materials can also be used as an electrode for a test | inspection.

また、上記の多層回路配線基板において、前記補強部として受動素子を有することがより好ましい。
この多層回路配線基板では、半導体集積回路素子と協働するような受動素子を補強部として使用する。受動素子のみで補強部を構成しても良いし、金属材料からなる補強部材と組み合わせて使用しても良い。 In the multilayer circuit wiring board, it is more preferable to have a passive element as the reinforcing portion .
In this multilayer circuit wiring board, a passive element that cooperates with a semiconductor integrated circuit element is used as a reinforcing portion. The reinforcing part may be constituted by only passive elements, or may be used in combination with a reinforcing member made of a metal material.

また、本発明の半導体装置は、上記のいずれか一項に記載の多層回路配線基板の前記搭載領域に、絶縁層が低誘電率材料からなる前記半導体集積回路素子を搭載して構成されることを特徴としている。
この半導体装置では、半導体集積回路素子を搭載したときの多層回路配線基板の変形が抑えられるので、実装性が向上する。特に、絶縁層として強度の低い低誘電率材料を使用している場合に、絶縁層の破壊が防止される。 Further, the semiconductor device of the present invention, the mounting area of the multilayer circuit wiring board according to any one of the above, it constructed by mounting the semiconductor integrated circuit device having an insulating layer made of a low dielectric constant material It is characterized by.
In this semiconductor device, since the deformation of the multilayer circuit wiring board when the semiconductor integrated circuit element is mounted can be suppressed, the mountability is improved. In particular, when the low dielectric constant material having low strength is used as the insulating layer, the insulating layer is prevented from being broken.

本発明によれば、半導体素子との線膨張係数差が大きくても、多層配線基板上で半導体素子を実装する領域の平面度を確保できる。したがって、半導体素子の実装性が向上すると共に、応力による半導体素子の機能不全を防止できる。また、配線基板と半導体素子の端子接続に使用する半田に作用する応力を小さくできるので、長期的な信頼性をさらに向上させることができる。   According to the present invention, even when the difference in coefficient of linear expansion from the semiconductor element is large, the flatness of the region where the semiconductor element is mounted on the multilayer wiring board can be ensured. Therefore, the mountability of the semiconductor element is improved and the malfunction of the semiconductor element due to stress can be prevented. Further, since the stress acting on the solder used for terminal connection between the wiring board and the semiconductor element can be reduced, long-term reliability can be further improved.

発明を実施するための最良の形態について図面を参照しながら詳細に説明する。
図１に、半導体集積回路素子搭載用配線基板に半導体集積回路素子を実装した半導体装置の一例を示す。
半導体装置１は、配線基板２に半導体素子３を実装した構成を有する。
半導体素子３は、高周波フィルタや、高周波スイッチ、ダイオードやＦＥＴなどの能動素子を有する。絶縁層には、高周波で動作させたときのリーク電流を抑制する観点から誘電率の低い材料、いわゆる低誘電率材料が用いられている。低誘電率材料としては、ポリイミドや、ブラックダイヤモンドなどのシングルカーボンの組成を用いた材料、ベンゾシクロブテンなどの低誘電率有機材料が用いられている。 The best mode for carrying out the invention will be described in detail with reference to the drawings.
FIG. 1 shows an example of a semiconductor device in which a semiconductor integrated circuit element is mounted on a wiring board for mounting a semiconductor integrated circuit element.
The semiconductor device 1 has a configuration in which a semiconductor element 3 is mounted on a wiring board 2.
The semiconductor element 3 has an active element such as a high-frequency filter, a high-frequency switch, a diode, or an FET. For the insulating layer, a material having a low dielectric constant, that is, a so-called low dielectric constant material is used from the viewpoint of suppressing a leakage current when operating at a high frequency. As the low dielectric constant material, a material using a single carbon composition such as polyimide or black diamond, or a low dielectric constant organic material such as benzocyclobutene is used.

配線基板２は、フィルム状の配線層と絶縁層を少なくとも１層ずつ積層した積層体からなる主基板部４と、主基板部４の弾性を高める補強部５とを有する。
主基板部４の絶縁層は、エポキシ系、ポリイミド系、ポリアミド系、含フッ素系、ベンゾシクロブテン系、ポリフェニレンエーテル系、ポリエステル系、アクリル系などの樹脂に、無機フィラー又は有機フィラー、あるいはガラス繊維を含ませた有機系材料が用いられる。配線層は、フレキシブルなフィルム状の絶縁層上に形成されており、銅や金等の導電率が高い材料から構成されている。したがって、主基板部４は、全体として可撓性を有し、その厚さは０．５ｍｍ以下、例えば０．２ｍｍや０．３ｍｍである。
図１及び図２に示すように、配線基板２の略中央部分には、半導体素子３を搭載する搭載領域７を有する。搭載領域７は、半導体素子３の外形に略等しい矩形を有し、搭載領域７内に半導体素子３を固定する接合部８が形成されている。接合部８は、配線基板２に形成した導電性の端子（不図示）と半導体素子３に形成した導電性の端子（不図示）とを接続する半田バンプからなる。 The wiring board 2 has a main board part 4 made of a laminate in which at least one film-like wiring layer and an insulating layer are laminated, and a reinforcing part 5 that increases the elasticity of the main board part 4.
The insulating layer of the main substrate 4 is made of an epoxy, polyimide, polyamide, fluorine-containing, benzocyclobutene, polyphenylene ether, polyester, acrylic resin, inorganic filler, organic filler, or glass fiber. An organic material containing is used. The wiring layer is formed on a flexible film-like insulating layer and is made of a material having high conductivity such as copper or gold. Therefore, the main board part 4 has flexibility as a whole, and its thickness is 0.5 mm or less, for example, 0.2 mm or 0.3 mm.
As shown in FIGS. 1 and 2, the wiring substrate 2 has a mounting region 7 in which the semiconductor element 3 is mounted at a substantially central portion. The mounting region 7 has a rectangular shape that is substantially equal to the outer shape of the semiconductor element 3, and a bonding portion 8 that fixes the semiconductor element 3 is formed in the mounting region 7. The joint portion 8 is composed of a solder bump that connects a conductive terminal (not shown) formed on the wiring board 2 and a conductive terminal (not shown) formed on the semiconductor element 3.

補強部５は、主基板部４の弾性を高める材料、例えば、銅、銅合金、アルミニウム、アルミニウム合金、少なくともニッケルとクロムのいずれかを含む鉄系合金、あるいはこれらに炭素又は酸素を混合させた材料が用いられる。これらの材料は、エッチングやパンチングによる加工が容易で、かつ主基板部４より弾性率が大きいため、主基板部４上に配置したときに、その部分の弾性を高めることができる。   The reinforcing portion 5 is a material that enhances the elasticity of the main substrate portion 4, for example, copper, copper alloy, aluminum, aluminum alloy, iron-based alloy containing at least one of nickel and chromium, or carbon or oxygen mixed therein. Material is used. Since these materials are easily processed by etching or punching and have a higher elastic modulus than that of the main substrate portion 4, when placed on the main substrate portion 4, the elasticity of that portion can be increased.

ここで、補強部５は、金属材料にメッキなどの表面処理を施した板状部材である。板状部材を構成する材料の弾性率が、主基板部４以下の場合、例えば主基板部４の絶縁材料と同じ厚さで同じ材質の補強部材であっても、主基板部４上に補強部５として配置すれば、主基板部４の他の部分よりも２倍の厚さになるから２倍の弾性を示すことになる。すなわち、金属材料でなくても補強効果は発揮される。補強部５を配置するための接着材６は、エポキシ系熱硬化樹脂が一般に使用されるが、リフローや封止樹脂硬化工程等の加熱工程において過剰に熱分解や収縮を起こさない耐熱性を有していれば良く、エポキシ系熱硬化樹脂に限定されない。   Here, the reinforcing portion 5 is a plate-like member obtained by performing a surface treatment such as plating on a metal material. When the elastic modulus of the material constituting the plate-like member is equal to or lower than that of the main substrate portion 4, for example, even if it is a reinforcing member having the same thickness and the same material as the insulating material of the main substrate portion 4, reinforcement is performed on the main substrate portion 4. If the portion 5 is disposed, the thickness is twice that of the other portions of the main substrate portion 4, and therefore the elasticity is doubled. That is, even if it is not a metal material, the reinforcing effect is exhibited. An epoxy thermosetting resin is generally used as the adhesive 6 for arranging the reinforcing portion 5, but has heat resistance that does not cause excessive thermal decomposition or shrinkage in a heating process such as a reflow process or a sealing resin curing process. However, it is not limited to the epoxy thermosetting resin.

次に、補強部５の形状と配置について説明する。補強部５は、半導体素子３の矩形の各辺、すなわち搭載領域７の各辺に対応した位置に、独立して４つ配置されている。補強部５は、半導体素子３の対角線を対称軸として線対称な位置に配置されている。   Next, the shape and arrangement of the reinforcing portion 5 will be described. Four reinforcing portions 5 are independently arranged at positions corresponding to the rectangular sides of the semiconductor element 3, that is, the sides of the mounting region 7. The reinforcing portion 5 is arranged at a line-symmetrical position with the diagonal line of the semiconductor element 3 as the symmetry axis.

図３に示すように、各々の補強部５は、半導体素子３の一辺３Ａに近接する端部５１が直線形状を有している。補強部５の端部５１は、相対する半導体素子３の辺３Ａと略平行となるように配置され、その距離ｄ１は１ｍｍから６ｍｍの間になるように配置されている。さらに、補強部５の端部５１は、半導体素子３の辺３Ａに平行に配置されているが、半導体素子３の辺３Ａを基準にして所定角度傾斜しても良い。例えば、半導体素子３の対向する辺３Ａに対する端部５１の傾斜角度θは、部分５１を通って辺３Ａに平行な仮想線Ｌｉに対して±２０°とする。
さらに、補強部５の直線形状の一端は、相対している半導体素子３の辺を挟む別の辺から補強部５の方向に仮想延長した線から、相対している半導体素子３の辺長の０％から２５％の間の長さだけ離れた位置に配置される。例えば、補強部５Ａでは、半導体素子３の辺３Ａを挟む別の辺３Ｂ，３Ｃについては、辺３Ｂの仮想延長線ＬＳ１から補強部５Ａまでの距離ｄ２が半導体素子３の辺３Ａの長さの０％から２５％の間の長さである。また、辺３Ｃの仮想延長線ＬＳ２から補強部５Ａまでの距離ｄ３は、半導体素子３の辺３Ａの長さの０％から２５％の間の長さである。 As shown in FIG. 3, each reinforcing portion 5 has an end portion 51 close to one side 3 </ b> A of the semiconductor element 3 having a linear shape. The end portion 51 of the reinforcing portion 5 is disposed so as to be substantially parallel to the side 3 </ b> A of the opposing semiconductor element 3, and the distance d <b> 1 is disposed between 1 mm and 6 mm. Further, the end 51 of the reinforcing portion 5 is arranged in parallel to the side 3A of the semiconductor element 3, but may be inclined at a predetermined angle with respect to the side 3A of the semiconductor element 3. For example, the inclination angle θ of the end 51 with respect to the opposite side 3A of the semiconductor element 3 is set to ± 20 ° with respect to the virtual line Li passing through the portion 51 and parallel to the side 3A.
Further, one end of the linear shape of the reinforcing portion 5 is equal to the side length of the semiconductor element 3 facing from a line virtually extending in the direction of the reinforcing portion 5 from another side that sandwiches the side of the semiconductor element 3 facing the reinforcing portion 5. They are arranged at positions separated by a length between 0% and 25%. For example, in the reinforcing portion 5A, the distance d2 from the virtual extension line LS1 of the side 3B to the reinforcing portion 5A is the length of the side 3A of the semiconductor element 3 for the other sides 3B and 3C sandwiching the side 3A of the semiconductor element 3. Length between 0% and 25%. The distance d3 from the virtual extension line LS2 of the side 3C to the reinforcing portion 5A is a length between 0% and 25% of the length of the side 3A of the semiconductor element 3.

ここで、半導体素子３が各辺３Ａ〜３Ｄの長さが１５ｍｍの正方形であった場合、ひとつの補強部５の直線状の端部５１の長さは、１５ｍｍから７．５ｍｍの間になる。補強部５の端部５１が１５ｍｍとは、仮想延長線ＬＳ１，ＬＳ２からの距離ｄ２，ｄ３が共に０％であり、直線部分が７．５ｍｍとは、仮想延長線ＬＳ１，ＬＳ２からの距離ｄ２，ｄ３が共に２５％のときである。そして、他の３つの補強部５は、補強部５Ａと同様の形状及び配置を有する。補強部５を前記した距離や角度、長さを越えて配置すると、半導体素子３が実装されたときの搭載領域７の変形を抑制する効果が減少するので好ましくない。   Here, when the length of each side 3A to 3D of the semiconductor element 3 is a square of 15 mm, the length of the linear end portion 51 of one reinforcing portion 5 is between 15 mm and 7.5 mm. . When the end 51 of the reinforcing portion 5 is 15 mm, the distances d2 and d3 from the virtual extension lines LS1 and LS2 are both 0%, and when the straight portion is 7.5 mm, the distance d2 from the virtual extension lines LS1 and LS2 , D3 are both 25%. The other three reinforcing portions 5 have the same shape and arrangement as the reinforcing portion 5A. If the reinforcing portion 5 is disposed beyond the above-mentioned distance, angle, and length, the effect of suppressing deformation of the mounting region 7 when the semiconductor element 3 is mounted is not preferable.

なお、搭載領域７の対角線の延長線上で、仮想延長線ＬＳ１と仮想延長線ＬＳ３とで区画されるコーナー部２Ａには補強部５は位置されない。同様に、搭載領域７の対角線の延長線上で、仮想延長線ＬＳ１と仮想延長線ＬＳ４とで区画されるコーナー部２Ａ、仮想延長線ＬＳ２と仮想延長線ＬＳ３とで区画されるコーナー部２Ａ、仮想延長線ＬＳ２と仮想延長線ＬＳ４とで区画されるコーナー部２Ａには補強部５は配置されない。   Note that the reinforcing portion 5 is not positioned in the corner portion 2A defined by the virtual extension line LS1 and the virtual extension line LS3 on the diagonal extension line of the mounting region 7. Similarly, on the diagonal extension line of the mounting area 7, a corner portion 2A defined by a virtual extension line LS1 and a virtual extension line LS4, a corner portion 2A defined by a virtual extension line LS2 and a virtual extension line LS3, a virtual The reinforcing portion 5 is not disposed at the corner portion 2A defined by the extension line LS2 and the virtual extension line LS4.

半導体装置１を製造するときには、配線基板２の所定位置に補強部５を接着材６で固定する。補強部５は、半導体素子３の辺３Ａ〜３Ｄと平行で変形しない背骨となる。その後、半田リフロー工程で半導体素子３を固定する。図２に示すように、補強部５の存在によって配線基板２における搭載領域７が大きく変形することがなくなる。配線基板２のコーナー部２Ａは、補強部５が配置されていないので変形するが、この部分は機能的に重要でない部分であるので半導体装置１の品質に影響を与えることはない。   When the semiconductor device 1 is manufactured, the reinforcing portion 5 is fixed to a predetermined position of the wiring board 2 with the adhesive material 6. The reinforcing portion 5 is a spine that is parallel to the sides 3A to 3D of the semiconductor element 3 and does not deform. Thereafter, the semiconductor element 3 is fixed by a solder reflow process. As shown in FIG. 2, the mounting region 7 on the wiring board 2 is not greatly deformed by the presence of the reinforcing portion 5. The corner portion 2A of the wiring board 2 is deformed because the reinforcing portion 5 is not disposed. However, since this portion is a functionally unimportant portion, the quality of the semiconductor device 1 is not affected.

この実施の形態によれば、補強部５を配置することで半導体素子３を実装する搭載領域７の変形を大幅に抑制したので、接合部８に無理な負担が作用せず、半導体装置１及び半導体素子３の長寿命化が図れる。半導体素子３に作用する応力が絶縁層を破壊する大きさ以下になるので、半導体素子３の破壊を防止でき、信頼性や歩留まりを向上できる。特に、半導体素子３の絶縁層が低誘電率材料である場合に、絶縁層の破壊を防止できる。
補強部５は、前記した寸法や角度で、半導体素子３を囲むように４つ配置したので、矩形状の半導体素子３の領域の変形を効果的に防止することができる。特に、仮想延長線ＬＳ１〜ＬＳ２と半導体素子３（搭載領域７）の各辺３Ａ〜３Ｄとが形成するコーナー領域に金属製の補強部５を設けたので、搭載領域７の変形を好適に抑制することができる。 According to this embodiment, since the deformation of the mounting region 7 on which the semiconductor element 3 is mounted is greatly suppressed by arranging the reinforcing portion 5, an unreasonable burden does not act on the joint portion 8, and the semiconductor device 1 and The lifetime of the semiconductor element 3 can be extended. Since the stress acting on the semiconductor element 3 is less than the magnitude that destroys the insulating layer, the semiconductor element 3 can be prevented from being broken, and the reliability and yield can be improved. In particular, when the insulating layer of the semiconductor element 3 is made of a low dielectric constant material, the insulating layer can be prevented from being broken.
Since the four reinforcing portions 5 are arranged so as to surround the semiconductor element 3 with the dimensions and angles described above, deformation of the region of the rectangular semiconductor element 3 can be effectively prevented. In particular, since the metal reinforcing portion 5 is provided in the corner region formed by the virtual extension lines LS1 to LS2 and the sides 3A to 3D of the semiconductor element 3 (mounting region 7), deformation of the mounting region 7 is suitably suppressed. can do.

ここで、この実施の形態の変形例について以下に説明する。
図４に示す半導体装置１０のように、補強部１１は略棒状であっても良い。補強部１１の位置が、前記と同様に仮想延長線ＬＳ１〜ＬＳ４及び搭載領域７の各辺を基準にして所定の範囲にあれば、同様の効果が得られる。
図５に示す半導体装置２０のような補強部２１でも良い。補強部２１は、半導体素子３（搭載領域７）を四方から囲むように配置され、補強部材２２と、補強部材２２の凹部２２Ａ内に配置された受動素子３３とを有する。補強部材２２は、半導体素子３に向けて凹形状を有し、配置位置及び材質は前記した補強部５と同じである。受動素子３３としては、コンデンサや、抵抗、コイルなどがあげられる。このように凹形状を有する補強部２１では回路のレイアウトの自由度を向上できる。半導体素子３になるべく近い位置に受動素子２３を配置することで、集積率が向上し、かつ半導体素子３の特性を最大限に高めることが可能になる。この場合、受動素子３３も補強部として機能するので、補強部材２２２の凹部２２Ａからなる部品搭載領域において、補強部材２２の両端の直線部分を結ぶ仮想直線ＬＳ５より内側に配置される。 Here, a modification of this embodiment will be described below.
As in the semiconductor device 10 illustrated in FIG. 4, the reinforcing portion 11 may have a substantially rod shape. If the position of the reinforcing portion 11 is in a predetermined range with reference to the sides of the virtual extension lines LS1 to LS4 and the mounting area 7 as described above, the same effect can be obtained.
A reinforcing portion 21 such as the semiconductor device 20 shown in FIG. The reinforcing portion 21 is disposed so as to surround the semiconductor element 3 (mounting region 7) from four directions, and includes a reinforcing member 22 and a passive element 33 disposed in the recess 22A of the reinforcing member 22. The reinforcing member 22 has a concave shape toward the semiconductor element 3, and the arrangement position and the material are the same as those of the reinforcing portion 5 described above. Examples of the passive element 33 include a capacitor, a resistor, and a coil. In this way, the reinforcing portion 21 having a concave shape can improve the degree of freedom of circuit layout. By disposing the passive element 23 as close to the semiconductor element 3 as possible, the integration rate can be improved and the characteristics of the semiconductor element 3 can be maximized. In this case, since the passive element 33 also functions as a reinforcing part, the passive element 33 is disposed on the inner side of the virtual straight line LS5 that connects the linear portions at both ends of the reinforcing member 22 in the component mounting region formed of the concave portion 22A of the reinforcing member 222.

図６に示す半導体装置３０の補強部３１のように、補強部材３２は４つに限定されない。すなわち、補強部材３２は、受動素子３３を挟み込むように２つずつ合計８つ配置されている。この場合、補強部３１は、全体として前記した補強部５と同じ配置になることが望ましい。すなわち、補強部材３２の側部３２Ａ，３２Ｂは、対応する仮想延長線ＬＳ１〜ＬＳ４からそれぞれ０〜２５％の間に配置される。半導体素子３（及び搭載領域７）の各辺３Ａ〜３Ｄに近接する各補強部材３２の端部３２Ｃは、１〜６ｍｍの範囲に配置され、これら各端部３２Ｃは、対向する辺３Ａ〜３Ｄに対する傾斜角度が±２０°以内になっている。受動素子３３は、補強部として機能するので、両隣りの補強部材３２の端部３２Ｃを結ぶ仮想線よりも半導体素子３側にはみ出さないように配置される。   Like the reinforcement part 31 of the semiconductor device 30 shown in FIG. 6, the reinforcement member 32 is not limited to four. That is, a total of eight reinforcing members 32 are arranged two by two so as to sandwich the passive element 33 therebetween. In this case, it is desirable that the reinforcing portion 31 has the same arrangement as the above-described reinforcing portion 5 as a whole. That is, the side portions 32A and 32B of the reinforcing member 32 are disposed between 0 to 25% from the corresponding virtual extension lines LS1 to LS4. The end portions 32C of the reinforcing members 32 adjacent to the sides 3A to 3D of the semiconductor element 3 (and the mounting region 7) are disposed in a range of 1 to 6 mm, and the end portions 32C are opposite sides 3A to 3D. The inclination angle with respect to is within ± 20 °. Since the passive element 33 functions as a reinforcing portion, the passive element 33 is disposed so as not to protrude from the imaginary line connecting the end portions 32C of the adjacent reinforcing members 32 to the semiconductor element 3 side.

図７に示す半導体装置４０は、主基板部４に半導体素子５０が実装されている。半導体素子５０は、外形が長方形状を有する他は前記した半導体素子３と同じである。半導体素子５０を四方から囲むように補強部４１，４２，４３，４４が配設されている。補強部４１は、補強部材４５と、電気検査のための電極４６からなる。補強部４２は、凹形状の補強部材４７と凹部４７Ａに収容された２つの受動素子３３とからなる。補強部４３は、半導体素子３に向かって凹形状を有する補強部材４７と、凹部４７Ａに収容された２つの受動素子３３とからなる。補強部４４は、半導体素子３の逆方向に向けて凹形状を有する補強部材４８と、凹部４８Ａに収容された２つの受動素子３３とからなる。   In the semiconductor device 40 shown in FIG. 7, the semiconductor element 50 is mounted on the main substrate portion 4. The semiconductor element 50 is the same as the semiconductor element 3 described above except that the outer shape is rectangular. Reinforcing portions 41, 42, 43, and 44 are disposed so as to surround the semiconductor element 50 from four directions. The reinforcing part 41 includes a reinforcing member 45 and an electrode 46 for electrical inspection. The reinforcing part 42 includes a concave reinforcing member 47 and two passive elements 33 accommodated in the concave part 47A. The reinforcing portion 43 includes a reinforcing member 47 having a concave shape toward the semiconductor element 3 and two passive elements 33 accommodated in the concave portion 47A. The reinforcing portion 44 includes a reinforcing member 48 having a concave shape in the opposite direction of the semiconductor element 3 and two passive elements 33 accommodated in the concave portion 48A.

なお、本発明は、前記の実施の形態に限定されずに広く応用することができる。
例えば、補強部５を配置すべき場所に、他の部品搭載領域や電気検査用電極領域が非対称に配置されている場合はその限りではなく、補強部を非対称形に配置してもよい。
半導体素子３の絶縁層は、低誘電率材料でなくても良い。半田による接合部に作用する応力を小さくできるので、長期的な信頼性を向上できる。
補強部は、受動素子２３のみから構成しても良い。受動素子２３を配置することで配線基板の弾性が高まるので、金属材料からなる補強部と同様の効果が得られる。また、受動素子２３を固定するために使用する半田が金属製の補強部材と同様の作用を有するので、配線基板の弾性を高めることができる。このため、補強部は、受動素子２３で補強部材を挟み込む配置であっても良い。 Note that the present invention can be widely applied without being limited to the above-described embodiment.
For example, when other component mounting regions and electrical inspection electrode regions are disposed asymmetrically at the place where the reinforcing portion 5 is to be disposed, the present invention is not limited thereto, and the reinforcing portions may be disposed asymmetrically.
The insulating layer of the semiconductor element 3 may not be a low dielectric constant material. Since the stress acting on the solder joint can be reduced, long-term reliability can be improved.
The reinforcing part may be composed of only the passive element 23. Since the elasticity of the wiring board is increased by arranging the passive element 23, the same effect as that of the reinforcing portion made of a metal material can be obtained. In addition, since the solder used for fixing the passive element 23 has the same function as the metal reinforcing member, the elasticity of the wiring board can be increased. For this reason, the reinforcement part may be arranged to sandwich the reinforcement member between the passive elements 23.

本発明の実施の形態に係る多層回路配線基板及び半導体装置の構成を示す斜視図である。It is a perspective view which shows the structure of the multilayer circuit wiring board and semiconductor device which concern on embodiment of this invention. 図１のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 補強部の配置を説明するための平面図である。It is a top view for demonstrating arrangement | positioning of a reinforcement part. 補強部が細長形状である場合を示す平面図である。It is a top view which shows the case where a reinforcement part is an elongate shape. 補強部が補強部材と受動素子とからなる場合を示す平面図である。It is a top view which shows the case where a reinforcement part consists of a reinforcement member and a passive element. 補強部が受動素子と、受動素子を挟むように配置される補強部材とからなる場合を示す平面図である。It is a top view which shows the case where a reinforcement part consists of a passive element and the reinforcement member arrange | positioned so that a passive element may be pinched | interposed. 補強部のその他の形態の一例を示す平面図である。It is a top view which shows an example of the other form of a reinforcement part. 従来の多層回路配線基板におけるリフロー工程を説明する図である。It is a figure explaining the reflow process in the conventional multilayer circuit wiring board.

符号の説明Explanation of symbols

１ 半導体装置
２ 配線基板（多層回路配線基板）
３，５０ 半導体素子（半導体集積回路素子）
３Ａ，３Ｂ，３Ｃ，３Ｄ 辺
４ 主基板部
５，１１，２１，３１，４１，４２，４３，４４ 補強部
７ 搭載領域
２２，３２，４７，４８ 補強部材（補強部）
２３ 受動素子（補強部）
３２Ａ，３２Ｂ 側部
３２Ｃ，５１ 端部
４６ 電極（補強部）
ｄ１，ｄ２，ｄ３ 距離
ＬＳ１，ＬＳ２，ＬＳ３，ＬＳ４ 仮想延長線（延長線）
θ 傾斜角度

1 Semiconductor Device 2 Wiring Board (Multilayer Circuit Wiring Board)
3,50 Semiconductor device (semiconductor integrated circuit device)
3A, 3B, 3C, 3D Side 4 Main board part 5, 11, 21, 31, 41, 42, 43, 44 Reinforcing part 7 Mounting area 22, 32, 47, 48 Reinforcing member (reinforcing part)
23 Passive element (reinforcement part)
32A, 32B side part 32C, 51 end part 46 electrode (reinforcement part)
d1, d2, d3 Distance LS1, LS2, LS3, LS4 Virtual extension line (extension line)
θ Inclination angle

Claims (7)

フィルム状の絶縁層と配線層とを少なくとも１層ずつ備え、略矩形の半導体集積回路素子を搭載可能な多層回路配線基板であって、
前記半導体集積回路素子を搭載する搭載領域として前記半導体集積回路素子と略同じ外形を有する矩形の領域を有し、
前記搭載領域を区画する辺で平行な２辺の延長線の間であって前記搭載領域を挟む４つの位置のそれぞれに、補強部が独立して配置され、
前記搭載領域の対角線の延長線上には前記補強部材を有しないことを特徴とする多層回路配線基板。 A multilayer circuit wiring board comprising at least one film-like insulating layer and a wiring layer, and capable of mounting a substantially rectangular semiconductor integrated circuit element,
The mounting region for mounting the semiconductor integrated circuit element has a rectangular region having substantially the same outer shape as the semiconductor integrated circuit element,
Reinforcing portions are independently arranged at each of four positions between two extended lines parallel to the side defining the mounting region and sandwiching the mounting region ,
A multilayer circuit wiring board, wherein the reinforcing member is not provided on a diagonal extension of the mounting area . 前記補強部は、前記搭載領域を区画する辺で平行な２辺の延長線の間に配置され、前記延長線と、前記延長線側の前記補強部の端部との間の距離は、前記延長線間の距離の０〜２５％の範囲内であることを特徴とする請求項１に記載の多層回路配線基板。 The reinforcing part is disposed between two extended lines parallel to the side defining the mounting area, and the distance between the extended line and the end of the reinforcing part on the extended line side is 2. The multilayer circuit wiring board according to claim 1 , wherein the distance is between 0 and 25% of the distance between the extension lines. 前記補強部において前記搭載領域に向かう端部から前記搭載領域までの距離は、１ｍｍから６ｍｍの範囲内であることを特徴とする請求項１又は請求項２に記載の多層回路配線基板。 3. The multilayer circuit wiring board according to claim 1, wherein a distance from an end of the reinforcing portion toward the mounting region to the mounting region is in a range of 1 mm to 6 mm. 前記補強部において前記搭載領域に向かう端部は直線状に形成され、
前記端部は、前記搭載領域における前記端部に対向する辺に対する傾きが±２０°以内に設定されていることを特徴とする請求項１から請求項３のいずれか一項に記載の多層回路配線基板。 In the reinforcing part, an end part toward the mounting region is formed in a straight line,
4. The multilayer circuit according to claim 1 , wherein the end portion is set to have an inclination with respect to a side opposite to the end portion in the mounting region within ± 20 °. 5. Wiring board. 前記補強部として金属製の部材を有することを特徴とする請求項１から請求項４のいずれか一項に記載の多層回路配線基板。 The multilayer circuit wiring board according to claim 1, further comprising a metal member as the reinforcing portion. 前記補強部として受動素子を有することを特徴とする請求項１から請求項４のいずれか一項に記載の多層回路配線基板。 The multilayer circuit wiring board according to claim 1, further comprising a passive element as the reinforcing portion. 請求項１乃至請求項６のいずれか一項に記載の多層回路配線基板の前記搭載領域に、絶縁層が低誘電率材料からなる前記半導体集積回路素子を搭載して構成される半導体装置。 A semiconductor device configured by mounting the semiconductor integrated circuit element whose insulating layer is made of a low dielectric constant material on the mounting region of the multilayer circuit wiring board according to claim 1 .
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