JP4507424B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4507424B2
JP4507424B2 JP2001055841A JP2001055841A JP4507424B2 JP 4507424 B2 JP4507424 B2 JP 4507424B2 JP 2001055841 A JP2001055841 A JP 2001055841A JP 2001055841 A JP2001055841 A JP 2001055841A JP 4507424 B2 JP4507424 B2 JP 4507424B2
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Japan
Prior art keywords
metal plate
bump
insulating resin
semiconductor device
electrode
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Expired - Fee Related
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JP2001055841A
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Japanese (ja)
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JP2002261182A (en
Inventor
良隆 奥川
宏之 沢井
仁 青木
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Sumitomo Bakelite Co Ltd
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Sumitomo Bakelite Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子をフリップチップ接続してなる半導体装置の製造方法に関するものである。
【0002】
【従来の技術】
近年の電子機器の高機能化、並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできており、これらの電子機器に使用される半導体パッケージは、従来にも増して、益々、小型化且つ多ピン化が進んでいる。
【0003】
これらの小型化したパッケージを電気的に接続する方法として、絶縁樹脂層に整列された導体端子電極を埋め込んだ接続用の部材を用いて、電気接続を行う方法が知られている。このような電気接続部材として、特開昭63−86322号公報には、柱状導電体が所定の配列で埋め込まれた導電異方性接着剤シートが提案されている。柱状導電体が所定の配列で予め絶縁層に埋め込まれているので、目的とする電極同士を正確に接続することが出来る。
【0004】
特開昭63−86322号公報では、このような接続用部材の製造方法として、ステンレスや銅などの金属板上に、めっきによって柱状電極を所定の位置に形成し、その後に接着剤層をコーティングして形成し、最後に金属板を剥離する方法が紹介されている。
【0005】
しかし、このような方法では、多数の柱状電極が形成された金属板の表面に、絶縁層となる接着剤樹脂をコーティングによって形成しなければならず、均一な厚みを得ることが困難であった。また、柱状電極の先端にも接着剤樹脂が塗布されてしまうので、導通を得るためには、表面に付着した接着剤樹脂を研磨などの方法で取り除く必要がある。
【0006】
また、特開平2−49385号公報には、金属シート上に感光性ポリイミドをスピンコートして、フォトエッチングによって、貫通孔を形成した後、電解金めっきを行って導電部材を形成し、最後に金属シートをエッチングして除去することによって、ポリイミド樹脂層に導電部材が埋め込まれた異方導電性接続部材を得る方法が提案されている。こうして得られた異方導電性接続部材を用いれば、フォトエッチングによって、微細な導電部材が形成されているので、目的とする電極同士を正確に接続することが出来る。また、絶縁層となる感光性ポリイミドが、予め形成されているので、導電部材の先端に塗布された樹脂を、後から除去する必要も生じない。さらに、接続する電極のピッチよりも細かなピッチで導電部材を形成することによって、接続する電極と異方導電性接続部材の相対的な位置合わせをしなくても接続することが出来る。
【0007】
しかし、この方法では感光性ポリイミドの形成をスピンコートで行っており、厚い塗膜を得ることが難しいため、層間の絶縁性を確保することが難しい。
【0008】
また、このような半導体装置では、高密度化のため半導体素子搭載部分の周辺にも回路が配置されるので、半導体装置全体が大きくなり、充分な強度を保つことが出来なくなって平坦性を保つことが困難になっている。そこで、半導体素子が搭載されていない部分に補強板を貼りつけて、反りを低減する対策が行われている。
【0009】
補強板には、銅板や合金などの金属板が用いられており、通常熱圧着タイプの接着剤や、常温接着型の接着剤を用いて、接着されている。しかし、熱圧着タイプの接着剤を用いた場合には、接着時に高温に加熱する為、基板が反ってしまう。また、常温接着型の接着剤は、耐熱性が良くないため、半導体装置を基板に搭載する際の半田リフロー時に補強板がはがれてしまうという問題点があった。
【0010】
【発明が解決しようとする課題】
本発明は、半導体装置における、上記のような現状の問題点に鑑み、微細配線が形成でき、半導体素子搭載部分の周辺に補強板を搭載することによって装置全体が平坦になり、外部との接続が容易に形成できる半導体装置の製造方法を提供することを目的とする。
【0011】
【課題を解決するための手段】
本発明は、所定の位置に整列したバンプ状の金属電極が表裏を貫通するように埋め込まれている絶縁樹脂基板上に、複数の層からなる配線層が積層されており、半導体素子搭載部分の周辺に金属板が残されていることを特徴とする半導体装置に関する製造方法である。
【0012】
即ち、半導体素子の電極位置に対応する金属板上の所定の位置に整列したバンプ状の金属電極を、前記金属電極の頂部が露出するように、インジェクション成形又はトランスファー成形により絶縁樹脂で埋め込む工程と、該露出した金属電極と電気的に接続されてなる複数層からなる配線層を該絶縁樹脂上に形成する工程と、該金属板の半導体素子搭載部分のみを除去する工程を含んでなることを特徴とする半導体装置の製造方法である。
【0013】
所定の位置に整列したバンプ状の金属電極が表裏を貫通するように埋め込まれている絶縁樹脂基板を得る方法としては、金属板上に整列されたバンプ状の金属電極を、前記金属電極の頂部が露出するように、インジェクション成形又はトランスファー成形により絶縁樹脂で埋め込んだ後、金属板の一部又は全部を除去する方法が使用できる。
【0014】
バンプ状の金属電極を金属板上に整列する方法としては、金線ワイヤーを用いて、金属板上にワイヤーボンディング装置を使用してスタッドバンプを作製する方法、金属板をハーフエッチングしてメサバンプと呼ばれるバンプを作製する方法、金属板上にめっきレジストを形成して、バンプ位置をパターニングし、金属板をめっき電極として電気めっきによって金属めっきバンプを形成する方法などが使用できる。
【0015】
金属板上に整列されたバンプ状の金属電極の頂部が、露出するように、インジェクション成形法又はトランスファー成形で絶縁樹脂を成形する方法としては、成形後に金属電極の頂部に付着した絶縁樹脂を、化学エッチングやプラズマ照射、物理研磨などの方法で除去しても良いが、すべてのバンプ状の金属電極の頂部を覆うように、板状治具、例えば、プラスチックフィルムや金属板などを配置して、次に板状治具が、バンプ状の金属電極の頂部に密着するように成形用金型をセットして、成形を行い、成形後に板状治具を除去することによって、金属電極の頂部に絶縁樹脂が付着しないように金属電極を絶縁樹脂で埋め込むことが出来る。また、金型で精密に樹脂の厚みや形状をコントロールすることができ、液状の樹脂を使用する塗布方式や印刷方式に比べて、乾燥などの工程が不要であり、シートを形成する方法のように、金属板上に整列したバンプに圧力をかける必要がなく、この方法によれば、成形と金属電極の頂部の露出が、ひとつの工程で実現でき、本発明の半導体装置に使用する絶縁樹脂基板の製造方法に好適である。
【0016】
本発明の電気接続部材の製造方法に使用するプラスチックフィルムとしては、成形時の熱に耐えうる樹脂で作られたフィルムが広く使用できる。ポリエステル、ポリプロピレン、ポリエーテルサルフォン、ポリイミド、ポリアミドイミド、ポリエーテルエーテルケトン、ポリエーテルイミドなどのフィルムを使用することができる。
【0017】
本発明の電気接続部材の製造方法に使用する絶縁樹脂としては、熱可塑性樹脂でも熱硬化性樹脂でも、この製造方法に適するものであればどのようなものでも使用できる。熱可塑性樹脂としては、ポリアミド、ポリイミド、ポリアミドイミド、ポリエーテルイミド、ポリエステルイミド、ポリエーテルエーテルケトン、ポリフェニレンサルフィド、ポリキノリン、ポリノルボルネン、液晶ポリマーなどが広く使用できる。熱硬化性樹脂としては、フェノール樹脂、エポキシ樹脂、ビスマレイミド、ビスマレイミド・トリアジン、トリアゾール、シアネート、イソシアネート、ポリシアヌレート、ポリイソシアヌレート、ベンゾシクロブテン、それらの変性品などが使用できる。
【0018】
本発明の電気接続部材の製造方法に使用する金属板には、銅、アルミニウム、鉄、ニッケル、銅合金、42合金、ステンレス、などが使用できる。
金属板は、フレーム形状に加工された枚葉のものを用いても良く、フープ状の連続形状のものを用いてもよい。特に、フープ状の金属板を用いた場合、連続的に成形することが出来、効率的に生産が可能であり好ましい。
【0019】
金属板の半導体素子搭載部分のみを除去する方法としては、酸やアルカリを用いて化学的にエッチング除去する方法が、好適に用いることが出来る。このとき、金属板にレジストでパターンを形成してもよく、例えば、格子状のパターンを形成することが出来る。格子状のパターンを形成する事により、金属板による補強を行うと共に、樹脂層を部分的に露出させることが出来るので、半導体装置の実装時にリフロー工程で急激に加熱された時に樹脂層に吸湿した水分が格子部分から容易に脱湿され、半導体装置の耐湿性が向上する。
【0020】
【発明の実施の形態】
以下、図面を参照して本発明の実施形態について説明するが、本発明はこれによって何ら限定されるものではない。図1〜図2は、本発明の実施形態である半導体装置の製造方法の一例を説明するための図であり、図3は、本発明の半導体装置の断面構造を説明するための図である。
【0021】
図1(a)は、本発明の半導体装置に使用する絶縁樹脂基板の製造で使用する金属板1である。まず、この金属板上にワイヤーボンディング装置で、金めっき線を用いて金属電極2をスタッドバンプ形状に半導体素子の電極位置に対応するように整列形成する(図1(b))。この時、スタッドバンプは、通常、高さが一定にならないので、スタッドバンプを形成した後に、全バンプの先端を一括してプレスして高さを揃えることが好ましい。
【0022】
次に、金属板に形成したスタッドバンプ上に、絶縁樹脂の成形時にバンプ頂部に絶縁樹脂が付着しないように保護するためのフィルム4を、予めセットし、その上からインジェクション成形金型3をセットする(図1(c))。
フィルムには、樹脂フィルムや金属薄膜などが使用できるが、樹脂フィルムはバンプ状の金属電極の表面を汚染することが無く、後の工程でのフィルム除去も容易で好ましい。フィルムの除去を容易にするため、フィルム表面に、予め離型処理をしておいても良い。また、フィルム厚みや金型の掘り込みは、バンプ状の金属電極の高さとともに予め設計された所定値に作製されている。
【0023】
次いで、インジェクション成形機の加熱筒内で加熱溶融した絶縁樹脂5を、フィルム4と金属板1との間の金型内に注入して、金型内に、予めセットしてあったフィルムとともに、バンプ状の金属電極を樹脂成形する(図1(d))。
【0024】
成形後に金型を取り外して、金属板上に整列されたバンプ状の金属電極の頂部にフィルムが付いた状態の成形物6が得られる(図1(e))。
【0025】
得られた成形物6から、フィルム4を除去する(図1(f))。
フィルムを除去する方法は、物理的に引き剥がす方法、プラズマ照射、レーザーアブレーション、化学エッチングなどの方法が使用できる。フィルムを除去したあとのバンプ状の金属電極の頂部は、絶縁樹脂の付着が無ければ、そのまま使用することが出来る。金属電極の頂部に絶縁樹脂が付着した場合には、物理的研磨や、化学的エッチングによって、除去する方法が使用される。
【0026】
このようにして得られた絶縁樹脂基板上に複数の層からなる配線層を形成する。配線層の形成には、絶縁樹脂基板上に無電解銅めっきで形成する方法や、あらかじめ別に作成しておいた回路シートを積層する方法が使用できる。20は金属板21上に作成されたバンプ付回路シートである。この回路シートはまず金属板上にめっきレジストを形成し、金属板を電極として電解めっきで配線回路23を形成した後、この配線回路上に絶縁樹脂シート22を真空ラミネートして貼り合わせる。貼り合せた絶縁樹脂シートの所定箇所をレーザーで開口して層間接続用のバンプとなる穴を形成する。金属板を電極として電解めっきによって開口部を銅で充填してバンプ24を形成する。続いてバンプの先端に電解めっきによって半田を形成する。
このようにして得たバンプ付回路シート20を前記の絶縁樹脂基板上に位置決めして加熱積層してバンプ先端の半田によって層間の電気接続を行う(図1(g))。
【0027】
次に回路シート側の金属板をエッチングして除去する。
これを繰り返す事によって、複数層から成る配線層を絶縁樹脂基板上に形成する(図2(h))。
最外層の配線層上にはソルダーレジスト9で、外部接続端子10となるランドを開口形成しておく。
【0028】
次に、絶縁樹脂基板のベースとして使用した金属板の、半導体素子搭載部分のみを除去する。(図2(i))金属板を除去する方法には、化学エッチングが使用できる。
【0029】
この時、金属板にレジストパターンを形成して、選択的に金属板を除去することによって、半導体素子搭載部分を除去すると共に、残った部分にさまざまなパターンを形成する事が出来る。図3に、金属板をエッチングして、格子状のパターン13を形成した例を示す。
【0030】
この半導体素子搭載部分に、半導体素子11の電極を位置合わせし、加熱圧着してフリップチップ接続を行い、外部接続端子に半田ボール12を載せることによって、半導体装置を得ることが出来る(図2(j))。半導体素子の電極部分にはアンダーフィルを充填しても良い。
【0031】
【発明の効果】
本発明の半導体装置によれば、所定の位置に整列したバンプ状の金属電極が表裏を貫通するように埋め込まれている絶縁樹脂基板上に、複数の層からなる配線層が積層されており、半導体素子搭載部分の金属板は除去されており、しかも半導体素子搭載部の周辺部分には金属板が残されているので、半導体素子をフリップチップ接続した後にも平坦な半導体装置を得ることができる。さらに、金属板の半導体素子搭載部分を除去するときに、残りの金属板を所定のパターンにエッチングすることによって、耐湿性に優れた半導体装置を容易に得ることが出来る。
【図面の簡単な説明】
【図1】本発明の実施形態による半導体装置の製造方法の一例を示す断面図である。
【図2】本発明の実施形態による半導体装置の製造方法の一例を示す断面図である(図1の続き)。
【図3】本発明の半導体装置の構造の一例を示す断面図である。
【符号の説明】
1、21 金属板
2 金属電極
3 インジェクション金型
4 フィルム
5、22 絶縁樹脂
6 成形物
7、23 絶縁層
8 配線層
9 ソルダーレジスト
10 外部接続端子
11 半導体素子
12 半田ボール
13 格子状のパターン
20 回路シート
24 バンプ
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which semiconductor elements are flip-chip connected.
[0002]
[Prior art]
In recent years, with the demand for higher functionality of electronic devices and lighter, thinner, and smaller devices, electronic components have been densely integrated and further mounted with high density. Semiconductor packages used in these electronic devices are More than ever, the size and number of pins are increasing.
[0003]
As a method for electrically connecting these miniaturized packages, a method is known in which electrical connection is made using a connection member in which conductor terminal electrodes aligned in an insulating resin layer are embedded. As such an electrical connection member, JP-A-63-86322 proposes a conductive anisotropic adhesive sheet in which columnar conductors are embedded in a predetermined arrangement. Since the columnar conductors are embedded in the insulating layer in a predetermined arrangement in advance, the intended electrodes can be accurately connected.
[0004]
In Japanese Patent Laid-Open No. 63-86322, as a method of manufacturing such a connecting member, a columnar electrode is formed at a predetermined position by plating on a metal plate such as stainless steel or copper, and then an adhesive layer is coated. A method of forming the metal plate and finally peeling the metal plate is introduced.
[0005]
However, in such a method, it is difficult to obtain a uniform thickness because an adhesive resin as an insulating layer must be formed by coating on the surface of the metal plate on which many columnar electrodes are formed. . Further, since the adhesive resin is also applied to the tip of the columnar electrode, in order to obtain conduction, it is necessary to remove the adhesive resin adhering to the surface by a method such as polishing.
[0006]
In JP-A-2-49385, a photosensitive polyimide is spin-coated on a metal sheet, a through hole is formed by photoetching, and then a conductive member is formed by performing electrolytic gold plating. There has been proposed a method of obtaining an anisotropic conductive connecting member in which a conductive member is embedded in a polyimide resin layer by removing a metal sheet by etching. If the anisotropic conductive connecting member obtained in this way is used, since the fine conductive member is formed by photoetching, the intended electrodes can be accurately connected. In addition, since the photosensitive polyimide serving as the insulating layer is formed in advance, it is not necessary to remove the resin applied to the tip of the conductive member later. Further, by forming the conductive member at a pitch finer than the pitch of the electrodes to be connected, the connection can be made without the relative positioning of the electrodes to be connected and the anisotropic conductive connecting member.
[0007]
However, in this method, photosensitive polyimide is formed by spin coating, and it is difficult to obtain a thick coating film, so it is difficult to ensure insulation between layers.
[0008]
Also, in such a semiconductor device, since the circuit is also arranged around the semiconductor element mounting portion for high density, the entire semiconductor device becomes large, and sufficient strength cannot be maintained and flatness is maintained. It has become difficult. Therefore, a countermeasure is taken to reduce warpage by attaching a reinforcing plate to a portion where no semiconductor element is mounted.
[0009]
As the reinforcing plate, a metal plate such as a copper plate or an alloy is used, and is usually bonded using a thermocompression bonding adhesive or a room temperature bonding adhesive. However, when a thermocompression adhesive is used, the substrate is warped because it is heated to a high temperature during bonding. In addition, since the room temperature adhesive has poor heat resistance, there is a problem in that the reinforcing plate is peeled off during solder reflow when the semiconductor device is mounted on the substrate.
[0010]
[Problems to be solved by the invention]
In the present invention, in view of the above-mentioned current problems in a semiconductor device, fine wiring can be formed, and by mounting a reinforcing plate around the semiconductor element mounting portion, the entire device is flattened and connected to the outside. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be easily formed.
[0011]
[Means for Solving the Problems]
In the present invention, a wiring layer composed of a plurality of layers is laminated on an insulating resin substrate in which bump-shaped metal electrodes aligned in a predetermined position are embedded so as to penetrate the front and back surfaces. A manufacturing method relating to a semiconductor device, characterized in that a metal plate is left around.
[0012]
That is, a step of embedding a bump-shaped metal electrode aligned at a predetermined position on the metal plate corresponding to the electrode position of the semiconductor element with an insulating resin by injection molding or transfer molding so that the top of the metal electrode is exposed; Forming a wiring layer composed of a plurality of layers electrically connected to the exposed metal electrode on the insulating resin, and removing only a semiconductor element mounting portion of the metal plate. This is a feature of a method for manufacturing a semiconductor device.
[0013]
As a method of obtaining an insulating resin substrate in which bump-shaped metal electrodes aligned in a predetermined position are embedded so as to penetrate the front and back, a bump-shaped metal electrode aligned on a metal plate is formed on the top of the metal electrode. After embedding with an insulating resin by injection molding or transfer molding, a method of removing a part or all of the metal plate can be used.
[0014]
As a method of aligning the bump-shaped metal electrode on the metal plate, a method of producing a stud bump using a wire bonding apparatus on the metal plate using a gold wire, a half-etching of the metal plate and a mesa bump There can be used a method for producing a bump, a method for forming a plating resist on a metal plate, patterning the bump position, and forming a metal plating bump by electroplating using the metal plate as a plating electrode.
[0015]
As a method of forming an insulating resin by injection molding or transfer molding so that the top of the bump-shaped metal electrode aligned on the metal plate is exposed, the insulating resin attached to the top of the metal electrode after molding is It may be removed by methods such as chemical etching, plasma irradiation, and physical polishing, but a plate-shaped jig, for example, a plastic film or metal plate, is placed to cover the top of all bump-shaped metal electrodes. Then, set the molding die so that the plate-shaped jig is in close contact with the top of the bump-shaped metal electrode, perform molding, and remove the plate-shaped jig after molding, so that the top of the metal electrode The metal electrode can be embedded with an insulating resin so that the insulating resin does not adhere to the substrate. In addition, the thickness and shape of the resin can be precisely controlled with a mold, and there is no need for a process such as drying compared to the coating method and printing method using liquid resin. In addition, it is not necessary to apply pressure to the bumps arranged on the metal plate. According to this method, the forming and the exposure of the top of the metal electrode can be realized in one process, and the insulating resin used for the semiconductor device of the present invention. It is suitable for a substrate manufacturing method.
[0016]
As the plastic film used in the method for producing an electrical connecting member of the present invention, a film made of a resin that can withstand heat during molding can be widely used. Polyester, polypropylene, polyethersulfone, polyimide, polyamideimide, polyetheretherketone, polyetherimide, and other films can be used.
[0017]
As the insulating resin used in the method for manufacturing the electrical connecting member of the present invention, any thermoplastic resin or thermosetting resin can be used as long as it is suitable for this manufacturing method. As the thermoplastic resin, polyamide, polyimide, polyamideimide, polyetherimide, polyesterimide, polyetheretherketone, polyphenylene sulfide, polyquinoline, polynorbornene, liquid crystal polymer, and the like can be widely used. As the thermosetting resin, phenol resin, epoxy resin, bismaleimide, bismaleimide / triazine, triazole, cyanate, isocyanate, polycyanurate, polyisocyanurate, benzocyclobutene, modified products thereof and the like can be used.
[0018]
Copper, aluminum, iron, nickel, a copper alloy, 42 alloy, stainless steel, etc. can be used for the metal plate used for the manufacturing method of the electrical connection member of the present invention.
The metal plate may be a single wafer processed into a frame shape, or a hoop-like continuous shape. In particular, when a hoop-shaped metal plate is used, it can be continuously formed and can be efficiently produced, which is preferable.
[0019]
As a method of removing only the semiconductor element mounting portion of the metal plate, a method of chemically removing with acid or alkali can be preferably used. At this time, a pattern may be formed on the metal plate with a resist. For example, a lattice pattern can be formed. By forming a lattice-like pattern, the metal layer can be reinforced and the resin layer can be partially exposed. Therefore, when the semiconductor device is mounted, the resin layer absorbs moisture when it is suddenly heated in the reflow process. Moisture is easily dehumidified from the lattice portion, and the moisture resistance of the semiconductor device is improved.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto. 1 to 2 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining a cross-sectional structure of the semiconductor device of the present invention. .
[0021]
FIG. 1A shows a metal plate 1 used in the manufacture of an insulating resin substrate used in the semiconductor device of the present invention. First, the metal electrode 2 is aligned and formed on the metal plate in a stud bump shape so as to correspond to the electrode position of the semiconductor element by using a gold-plated wire with a wire bonding apparatus (FIG. 1B). At this time, since the height of the stud bump is usually not constant, it is preferable that the height of the stud bump is made uniform by pressing all the bump tips at once after the stud bump is formed.
[0022]
Next, on the stud bump formed on the metal plate, a film 4 for protecting the insulating resin from adhering to the top of the bump at the time of molding the insulating resin is set in advance, and the injection molding die 3 is set thereon. (FIG. 1 (c)).
As the film, a resin film, a metal thin film, or the like can be used. However, the resin film does not contaminate the surface of the bump-shaped metal electrode, and the film can be easily removed in a later step. In order to facilitate the removal of the film, the surface of the film may be subjected to a release treatment in advance. Further, the film thickness and the digging of the mold are made to predetermined values designed in advance together with the height of the bump-shaped metal electrode.
[0023]
Next, the insulating resin 5 heated and melted in the heating cylinder of the injection molding machine is injected into a mold between the film 4 and the metal plate 1, together with the film set in advance in the mold, A bump-shaped metal electrode is formed by resin molding (FIG. 1D).
[0024]
After the molding, the mold is removed, and a molded product 6 in a state where a film is attached to the top of the bump-shaped metal electrode aligned on the metal plate is obtained (FIG. 1 (e)).
[0025]
The film 4 is removed from the obtained molded product 6 (FIG. 1 (f)).
As a method for removing the film, a method of physically peeling, a method of plasma irradiation, laser ablation, chemical etching or the like can be used. The top of the bump-shaped metal electrode after the film is removed can be used as it is if there is no adhesion of insulating resin. When the insulating resin adheres to the top of the metal electrode, a method of removing it by physical polishing or chemical etching is used.
[0026]
A wiring layer composed of a plurality of layers is formed on the insulating resin substrate thus obtained. For the formation of the wiring layer, a method of forming by electroless copper plating on an insulating resin substrate or a method of laminating circuit sheets prepared separately in advance can be used. Reference numeral 20 denotes a bumped circuit sheet formed on the metal plate 21. In this circuit sheet, first, a plating resist is formed on a metal plate, a wiring circuit 23 is formed by electrolytic plating using the metal plate as an electrode, and then an insulating resin sheet 22 is vacuum-laminated and bonded onto the wiring circuit. A predetermined portion of the bonded insulating resin sheet is opened with a laser to form a hole to be a bump for interlayer connection. The bumps 24 are formed by filling the openings with copper by electrolytic plating using a metal plate as an electrode. Subsequently, solder is formed on the tip of the bump by electrolytic plating.
The bumped circuit sheet 20 thus obtained is positioned on the insulating resin substrate, heated and laminated, and the electrical connection between the layers is performed by solder at the bump tip (FIG. 1 (g)).
[0027]
Next, the metal plate on the circuit sheet side is removed by etching.
By repeating this, a wiring layer composed of a plurality of layers is formed on the insulating resin substrate (FIG. 2 (h)).
On the outermost wiring layer, a land serving as an external connection terminal 10 is formed by opening with a solder resist 9.
[0028]
Next, only the semiconductor element mounting portion of the metal plate used as the base of the insulating resin substrate is removed. (FIG. 2 (i)) Chemical etching can be used as a method for removing the metal plate.
[0029]
At this time, by forming a resist pattern on the metal plate and selectively removing the metal plate, the semiconductor element mounting portion can be removed and various patterns can be formed on the remaining portion. FIG. 3 shows an example in which a metal plate is etched to form a lattice pattern 13.
[0030]
The semiconductor device can be obtained by aligning the electrodes of the semiconductor element 11 on this semiconductor element mounting portion, performing thermo-compression bonding to perform flip chip connection, and placing the solder balls 12 on the external connection terminals (FIG. 2 ( j)). The electrode portion of the semiconductor element may be filled with underfill.
[0031]
【The invention's effect】
According to the semiconductor device of the present invention, a wiring layer composed of a plurality of layers is laminated on an insulating resin substrate in which bump-shaped metal electrodes aligned in a predetermined position are embedded so as to penetrate the front and back. The metal plate of the semiconductor element mounting portion is removed, and the metal plate is left in the peripheral portion of the semiconductor element mounting portion, so that a flat semiconductor device can be obtained even after the semiconductor element is flip-chip connected. . Furthermore, when the semiconductor element mounting portion of the metal plate is removed, the remaining metal plate is etched into a predetermined pattern, whereby a semiconductor device having excellent moisture resistance can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufacturing method according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an example of a semiconductor device manufacturing method according to an embodiment of the present invention (continuation of FIG. 1).
FIG. 3 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 21 Metal plate 2 Metal electrode 3 Injection die 4 Film 5, 22 Insulating resin 6 Molded product 7, 23 Insulating layer 8 Wiring layer 9 Solder resist 10 External connection terminal 11 Semiconductor element 12 Solder ball 13 Lattice pattern 20 Circuit Sheet 24 Bump

Claims (1)

半導体素子の電極位置に対応する金属板上の所定の位置に整列したバンプ状の金属電極を、前記金属電極の頂部が露出するように、インジェクション成形又はトランスファー成形により絶縁樹脂で埋め込む工程と、該露出した金属電極と電気的に接続されてなる複数層からなる配線層を該絶縁樹脂上に形成する工程と、該金属板の半導体素子搭載部分のみを除去するとともに、該金属板に格子状のパターンを形成する工程を含んでなることを特徴とする半導体装置の製造方法。 Embedding a bump-shaped metal electrode aligned with a predetermined position on the metal plate corresponding to the electrode position of the semiconductor element with an insulating resin by injection molding or transfer molding so that the top of the metal electrode is exposed; and Forming a wiring layer composed of a plurality of layers electrically connected to the exposed metal electrode on the insulating resin, removing only the semiconductor element mounting portion of the metal plate, and forming a grid-like pattern on the metal plate; A method of manufacturing a semiconductor device, comprising a step of forming a pattern.
JP2001055841A 2001-02-28 2001-02-28 Manufacturing method of semiconductor device Expired - Fee Related JP4507424B2 (en)

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JP4844216B2 (en) * 2006-04-26 2011-12-28 凸版印刷株式会社 Multilayer circuit wiring board and semiconductor device
US10049950B2 (en) * 2012-03-26 2018-08-14 Advanpack Solutions Pte Ltd Multi-layer substrate for semiconductor packaging

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219421A (en) * 1996-02-14 1997-08-19 Hitachi Ltd Manufacture of semiconductor electronic component and wafer
JP2001024141A (en) * 1999-07-13 2001-01-26 Dainippon Printing Co Ltd Manufacture of circuit component for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219421A (en) * 1996-02-14 1997-08-19 Hitachi Ltd Manufacture of semiconductor electronic component and wafer
JP2001024141A (en) * 1999-07-13 2001-01-26 Dainippon Printing Co Ltd Manufacture of circuit component for semiconductor device

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