JPH09219421A - Manufacture of semiconductor electronic component and wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a TAT and reduce the cost of the TAT by a method wherein stud bump electrodes made of solder are respectively formed again on the point parts of first-layer electrodes, second-layer electrodes of a shape uniformized by reflowing the stud bump electrodes are formed and a wafer is diced into chips to obtain chip-sized packages. SOLUTION: Solder stud bump electrodes 2 formed on a wafer 1 are subjected to leveling, electrodes 2a are formed and organic materials 3 and 4 are respectively provided on both surfaces of the surface and rear of the wafer 1 formed with the electrodes 2a making to interpose the wafer 1 between them by molding, coating or the like. A surface treatment, such as a polishing treatment, of these bump electrodes 2a and first electrodes 2b is performed, which respectively have a bump electrode upper part which is new and is easily wetted, are formed. Solder stud bump electrodes 2c are respectively formed again on the point parts of the electrodes 2b, the wafer 1 is reflowed to form second electrodes 2d obtainable by making even the electrodes 2c and the wafer 1 is diced into chips to obtain chip-sized packages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor electronic component which can be manufactured and provided at a low cost, with a semiconductor electronic component having a size substantially equal to the chip size thereof and having high reliability. The present invention relates to a method and a wafer manufactured by the manufacturing method.

[0002]

2. Description of the Related Art In a conventional semiconductor electronic component, a wafer on which a circuit is formed in a preceding step is first diced into individual chip shapes and fixed by die bonding. Next, the electrode portion of the chip is connected to the lead of the lead frame prepared for external connection by wire bonding.
Thereafter, resin molding is performed by a molding machine, and a final PKG is obtained through a deburring process, a plating process, a trimming process, and a forming process. Also in the PKG using TAB, the dicing chip and the TAB lead are connected by inner lead bonding, and potting resin encapsulation and mold resin encapsulation are performed, and the final PKG is obtained after deburring, trimming, and forming steps.
Becomes

[0003]

SUMMARY OF THE INVENTION In the above-mentioned prior art, the following problems occur when it is attempted to manufacture and provide a semiconductor electronic component having a size approximately the same as the chip size and high reliability at low cost. is there.

1. Since the external electrodes are arranged on the surface of the PKG in the final PKG form, it is extremely difficult to form the electrodes if the structure uses a lead frame, TAB, or the like.

[0005] 2. The wiring lead forming step before the molding step, the electrode forming step after the molding step, etc. are increased from the current PKG step, resulting in higher cost.

[0006] 3. Since a lead frame, TAB, etc. are used, there is a limit to thinning the PKG in the height direction.

[0007] 4. Since the forming of the wiring lead, which is a part of the lead frame, is performed before the molding process, the molding process becomes complicated and the cost becomes high.

[0008] 5. Since the wiring lead extends to the PKG surface from the chip surface electrode portion at a short distance, when the interface between the mold resin and the wiring lead is separated due to stress or the like, the moisture resistance becomes poor in a short time. It is difficult for the PKG structure using the lead frame to reduce the stress generated in the electrode portion and the wiring lead. Further, it is difficult to incorporate the stress relaxation structure in the electrode portion even at the time of mounting. Therefore, it becomes difficult to secure the reliability of the semiconductor electronic component.

6. Since the PKG process is performed using the lead frame, TAB, and the like as carriers, it is difficult to shorten TAT, that is, reduce cost.

[0010]

As means for solving the above problems, first, a TAT is shortened and the number of steps is reduced by going through a molding process for each wafer. Further, the electrodes are not taken out to the outside of the PKG using a lead frame, TAB, etc., but the electrodes are formed on the wafer wiring and taken out to the outside. That is, it is a manufacturing method in which a final PKG form is obtained by performing a dicing process lastly through a molding process for each wafer.

By performing a molding process on a wafer-by-wafer basis, a process of die-bonding and fixing individual chips to a package, and connecting the electrode portions of the chips to the leads of a lead frame prepared for external connection by wire bonding. The number of steps can be reduced. Furthermore, all the PKG manufacturing processes can be performed on a wafer-by-wafer basis, and TAT can be shortened. Further, in the molding process, since the resin is only circularly formed on the wafer, the molding die can be made simple and inexpensive. This means that if the wafer size is the same, the same mold can be used for different specifications and different products, and it is possible to realize a reduction in TAT and a low cost in the production of a large number of small-lot products. Also, the burn-in process can be easily performed using the wafer after molding.

As described above, it is possible to inexpensively manufacture and provide a PKG having a size substantially equal to the chip size. The electrodes are not taken out to the outside of the PKG using a lead frame, TAB, etc., but the electrodes are taken out directly on the wafer wiring and taken out to the outside, so that the PKG surface can be arranged at an arbitrary pitch, size and arrangement. Electrodes can be formed, P
It is possible to provide a thin KG. Also in terms of reliability, the size and height of the electrode can be easily made arbitrary, and any material can be used, so that a highly reliable PKG can be easily provided.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be shown below.

FIG. 1 shows an example of a structure of a chip size PKG and a manufacturing method. FIG. 1a shows the wafer 1 which has completed the pre-process. Figure 1b
The electrode 2 is formed on the wafer 1 of a. Here, the case where the electrode 2 is a solder stud bump is specified. Various kinds of electrodes 2 such as Au, solder and Cu can be considered as the electrode 2. In FIG. 1c, the solder stud bump electrode 2 formed on the wafer 1 is leveled to form an electrode 2a. FIG. 1d shows that the organic material 3 and 4 are interposed between the front and back surfaces of the wafer 1 on which the electrodes 2a are formed by leveling the solder stud bump electrodes 2 of FIG. 1c by molding or coating. Where the electrode 2
Reflow may be performed once in order to make the shape of a uniform. The organic materials 3 and 4 may have different physical property values, and the organic material 3 having conductivity may be used as an electromagnetic wave shield. The organic material 4 is molded and coated so that the height of the organic material 4 is about the same as or lower than the height of the electrode 2a, and the upper portion of the protrusion of the electrode 2a is not stained or coated with the organic material 4. The organic material 4 is also for alleviating stress and the like generated due to the difference in linear expansion coefficient between the chip and the connecting substrate when the semiconductor electronic component of the present invention is connected to the substrate, and the physical properties depend on the type of substrate used. It is necessary to use organic materials 4 having different values. Here, when dirt or a film of the organic material 4 adheres to the upper part of the projection of the electrode 2a during the molding or coating of the organic materials 3 and 4, a surface treatment such as polishing or etching is performed to have a new, easily wet projection electrode upper part. The electrode 2b is formed. When the step of coating with the organic materials 3 and 4 is performed by molding, the molding die may have a very simple shape, which is low in cost and QTA.
It can be easily turned into T. In FIG. 1e, the solder stud bump electrode 2c is formed again on the electrode 2b.
Here, the electrode 2c may be formed by immersing the wafer 1 of FIG. 1d in a solder bath, or solder having a different composition may be used. In FIG. 1f, the wafer 1 of FIG. 1e is reflowed to form an electrode 2d in which the shape of the solder stud bump electrode 2c is made uniform. Figure 1g
FIG. 3 shows the final form of the chip size PKG after dicing the wafer 1 of FIG. 1f. By adopting the manufacturing process and the structure as described above, it is possible to provide a semiconductor electronic component which is approximately the same size as the chip size and which is highly reliable and inexpensive.

FIG. 2 shows another example of the manufacturing method of the chip size PKG. As shown in FIG. 2B, the front and rear surfaces of the wafer 1 are molded and coated with the organic materials 3 and 4 on the wafer 1 which has been subjected to the previous process shown in FIG. Here, the organic materials 3 and 4 are the same as those described in FIG. 1d. However, the thickness of the organic material 4 has a deep relationship with the shape of the electrode, so that the stress relaxation is most effective in consideration of the substrate to be connected. 2c shows a hole or groove 5 for electrode formation in the organic material 4 on the surface side of the wafer 1 of FIG. 2b.
Is constructed by etching, laser irradiation, etc. FIG. 2d shows the electrode 2e formed on FIG. 2c, and FIG. 2e shows the final form of the chip size PKG after dicing the wafer 1 of FIG. 2d.

FIG. 3 also shows another example of the manufacturing method of the chip size PKG. As shown in FIG. 3b, the wafer 1 after the pre-process shown in FIG.
The wire electrodes 2f, etc. are formed at arbitrary heights on the wiring of the wafer. Next, as shown in FIG. 3C, the front and back surfaces of the wafer 1 are molded and coated with organic materials 3 and 4. Here, the organic materials 3 and 4 are the same as those described in FIG. 1d. FIG. 3d shows a new surface which is easily wetted by performing surface treatment such as polishing or etching when dirt or a film of the organic material 4 adheres to the upper part of the wire electrode 2f during molding and coating of the organic materials 3 and 4 of FIG. 3c. The wire electrode 2g to be held is formed. In FIG. 3e, the electrode 2h is formed again on the electrode 2g. Here, the electrode 2h may be formed by immersing the wafer 1 shown in FIG. 3d in a solder bath, or electrode materials having different compositions may be used. FIG.
3f shows the final form of the chip size PKG after dicing the wafer 1 of FIG. 3e.

In FIGS. 4a and 4b, the organic material 3 in the form of a wafer 1 is shown.
The state when coating is shown.

The grid line on the wafer 1 of FIG. 4a is a scribe line 6. The grid-like lines on the organic material 3 in FIG. 4b are the dicing grooves 7, and in order to perform dicing using the current dicing apparatus, the organic materials 3 and 4 above and below the scribe line 6 are etched or the like. Must be removed.

5, 6, 7, 8, 9, 10, 1 shown in FIG.
Reference numerals 1 and 12 show examples of the state of the wafer 1 before the dicing process.

FIG. 5 shows the wafer 1 of FIG.
The steps d, e, and f are performed again only on the surface of the wafer 1, that is, on the electrode side. Electrodes 2b, 2d, 2i at this time
Also, the physical properties of the organic materials 4 and 8 are configured so that the stress and the like generated due to the difference in linear expansion coefficient between the chip and the connecting substrate when the semiconductor electronic component is connected to the substrate can be most relaxed. The same applies to the repetition of this step, and the optimum number of times is repeated n times.

FIG. 6 shows that in the wafer 1 of FIG. 5, the organic material 3 on the back surface of the wafer 1 is used for normal molding and coating, and when the steps of FIGS. 1d, e, and f are repeated for the organic material 9, It is assumed to be conductive and is formed as an electromagnetic wave shield.

FIG. 7 shows that in the wafer 1 of FIG. 2d, the organic material 1 having good thermal conductivity is formed on the organic material 3 on the back surface side of the wafer 1.
High heat dissipation type chip size PKG formed by molding 0
This is an example.

FIG. 8 shows the shape of the electrodes 2j, 2k, 2l in the chip size PKG manufacturing process of FIG. 2 which is arbitrarily shaped so as to improve the reliability of connection with the substrate. Here, the shape of the electrode 2k is formed by an arbitrary shape when the organic material 11 is etched.

FIG. 9 shows that the electrode 2f is formed from the organic material 4 so that the electrode 2f is sufficiently exposed and then the electrode 2m is formed in the chip size PKG manufacturing process of FIG.

The above-mentioned FIGS. 8 and 9 show the chip size PKG.
It is intended to improve the reliability of.

FIG. 10 shows the organic material 3 formed only on the back surface of the wafer 1 of FIG. 1c.

This is an example of the chip size PKG which has the closest structure to the bare chip PKG, but is excellent in terms of handling.

FIG. 11 shows the organic material 4 formed only on the surface of the wafer 1 of FIG. 1c. This is an example of a chip size PKG having excellent heat dissipation, but the mounting form is preferably mounting using an anisotropic conductive film or the like.

FIG. 12 shows an example in which the electrode 2d is formed in FIG. 11, which is an example of a chip size PKG excellent in heat dissipation.

FIG. 13 shows a manufacturing process flowchart in FIG. 1 of the present invention. Here, a particularly important point is that the PKG process is performed on a wafer-by-wafer basis.
AT can be shortened. In addition, a wafer-shaped burn-in, marking, and the like are performed, which is a manufacturing process of a chip size PKG suitable for cost reduction.

[0031]

As described above, according to the present invention, it is possible to manufacture and provide a semiconductor electronic component having a size approximately the same as the chip size thereof and having high reliability at low cost.

[Brief description of drawings]

FIG. 1 is a method 1 for manufacturing a chip size PKG.

FIG. 2 Manufacturing method 2 of chip size PKG

FIG. 3 is a manufacturing method 3 of a chip size PKG.

4] Example of organic material coating on wafer

FIG. 5: Chip size PKG structure 1

FIG. 6 Chip size PKG structure 2

FIG. 7: Chip size PKG structure 3

FIG. 8: Chip size PKG structure 4

FIG. 9: Chip size PKG structure 5

FIG. 10: Chip size PKG structure 6

FIG. 11: Chip size PKG structure 7

FIG. 12: Chip size PKG structure 8

FIG. 13 is a flowchart of a chip size PKG manufacturing process.

[Explanation of symbols]

1 ... Wafer 6 ... Scribe line 2 ... Electrode 7 ... Dicing groove 3 ... Organic material 3 8 ... Organic material 8 4 ... Organic material 4 9 ... Organic material 9 5 ... Electrode forming groove 10 ... Organic material 10.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Yamamoto 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated company, Hitachi, Ltd. Semiconductor Division (72) Inventor Ryo Haruta 5 Mizumizumoto-cho, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd., 20-20-1, Kunihiro Tsubozaki, 5-20-1, Kamimizuhonmachi, Kodaira City, Tokyo Inventor, Kenichiro Morinaga, Tokyo, Ltd., 72, Ltd., Hitachi, Ltd. 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Semiconductor Company, Hitachi Ltd.

Claims (26)

[Claims] 1. A wafer on which a circuit is formed in a previous step,
Solder stud bumps are formed at the electrode formation locations on the wafer wiring, the stud bumps are leveled into a uniform shape, and the front and back surfaces of the wafer are molded or coated with an organic material, to the same extent as the organic material. Of the leveled stud bump, the tip of which is exposed from the organic material at a height of, or higher, the tip of which is polished,
Alternatively, surface treatment such as etching is performed to form a first layer electrode, and a solder stud bump is formed again at the tip of the surface treated first layer electrode, and the stud bump is made uniform by reflow. A method of manufacturing a semiconductor electronic component, comprising a second-layer electrode having the above shape, and dicing the wafer into chips to obtain a chip size package. 2. A step of forming a stud bump of solder again on the tip of the electrode of the first layer according to claim 1, and forming the stud bump with the electrode of the second layer having a uniform shape by reflow. Solder stud bumps are formed again on the tip of the electrode of the first layer, the stud bumps are leveled into a uniform shape, and the organic material is molded again onto the organic material on the surface of the wafer. Or coated, the leveled stud bumps, the tip of which is exposed from the organic material at the same height as the organic material or at a height higher than the organic material, the tip is polished,
Alternatively, a surface layer of etching is applied to form a second layer electrode, and a solder stud bump is formed again at the tip of the surface-treated second layer electrode, and the stud bump is made uniform by reflow. 2. The step of forming a third layer electrode having the above-mentioned shape.
A method of manufacturing a semiconductor electronic component as described in. 3. The stud bump of the solder is Au, or
2. A Cu stud bump.
Alternatively, the method for manufacturing the semiconductor electronic component according to claim 2. 4. The step of remolding or coating the organic material on the front surface of the wafer according to claim 2, wherein the organic material on the back surface of the wafer is electrically conductive. The method according to claim 2, further comprising a step of molding or coating a certain organic material.
A method of manufacturing a semiconductor electronic component as described in. 5. A front surface and a back surface of a wafer on which a circuit is formed in the previous step are molded or coated with an organic material, and the organic material existing in an electrode formation portion on the wafer wiring is etched or laser-irradiated. A method of manufacturing a semiconductor electronic component, which is removed in a hole shape or a groove shape, an electrode is formed in the portion removed in the hole shape or the groove shape, and the wafer is diced into chips to obtain a chip size package. 6. After the step of forming an electrode in the hole-shaped or groove-shaped removed portion according to claim 5, an organic material having good thermal conductivity is applied onto the organic material on the back surface of the wafer. The method for manufacturing a semiconductor electronic component according to claim 5, further comprising a step of forming with a mold. 7. After the step of forming an electrode in the hole-shaped or groove-shaped removed portion according to claim 5, the organic material is again molded on the organic material on the surface of the wafer, or The organic material present in the electrode formation portion of the first layer coated on the wafer is removed by etching or laser irradiation into a hole shape or a groove shape, and the hole shape or a groove shape is removed. 6. The method according to claim 5, wherein the step of forming the second layer electrode is repeated.
A method of manufacturing a semiconductor electronic component as described in. 8. A wafer on which a circuit is formed in the previous step,
Solder wire electrodes are formed at electrode formation points on the wafer wiring, and the front and back surfaces of the wafer are molded or coated with an organic material, and the organic material has the same height or a height higher than that. The wire electrode, the tip of which is exposed from the organic material, is formed into a first layer electrode by subjecting the tip of the wire electrode to surface treatment such as polishing or etching, and the surface-treated first layer electrode. A semiconductor electronic component in which a stud bump of solder is formed at the tip end of the wafer, and the stud bump is formed into a second layer electrode having a uniform shape by reflow, and the wafer is diced into chips to obtain a chip size package. Manufacturing method. 9. The method of manufacturing a semiconductor electronic component according to claim 8, wherein the solder wire electrode or the solder stud bump is made of Au or Cu. 10. A stud bump of solder is formed at an electrode forming position on a wafer wiring on a wafer on which a circuit is formed in a previous step, and the stud bump is leveled to a uniform shape to form an electrode. A method for manufacturing a semiconductor electronic component, wherein a back surface of the wafer is molded or coated with an organic material, and the wafer is diced into chips to obtain a chip size package. 11. A stud bump of a solder is formed on an electrode forming portion of a wafer wiring on a wafer on which a circuit is formed in a previous step, and the stud bump is leveled to a uniform shape. , A mold or coating of an organic material, and the tip of the leveled stud bump, the tip of which is exposed from the organic material by the same height as or higher than the organic material, Polishing,
Alternatively, a method for manufacturing a semiconductor electronic component, in which a surface treatment such as etching is performed to form an electrode, and the wafer is diced into chips to obtain a chip size package. 12. The leveled stud bump, the tip of which is exposed from the organic material by the same height as or higher than that of the organic material according to claim 11, and the tip of the leveled stud bump. After the step of polishing or etching to form an electrode by applying a surface treatment, a solder stud bump is formed again on the tip of the surface-treated electrode, and the stud bump having a uniform shape is formed by reflow. The method of manufacturing a semiconductor electronic component according to claim 11, wherein a step of forming the second layer electrode is added. 13. The stud bump of the solder is a stud bump of Au or Cu.
The method of manufacturing a semiconductor electronic component according to claim 0, claim 11, or claim 12. 14. A wafer on which a circuit has been formed in the previous step is formed with solder stud bumps at electrode formation locations on the wafer wiring, and the stud bumps are leveled into a uniform shape. A mold or coating of an organic material, and the tip of the leveled stud bump, the tip of which is exposed from the organic material at the same height as or higher than the organic material. Polishing,
Alternatively, surface treatment such as etching is performed to form a first layer electrode, and a solder stud bump is formed again at the tip of the surface treated first layer electrode, and the stud bump is made uniform by reflow. A wafer having a second-layer electrode having the above-mentioned shape. 15. A stud bump of solder is formed again on the tip of the electrode of the first layer according to claim 14, and the stud bump is leveled to a uniform shape. On top of that, the organic material is molded or coated again, and the leveled stud bumps whose tips are exposed from the organic material by the same or higher height than the organic material, Polishing its tip,
Alternatively, a surface layer of etching is applied to form a second layer electrode, and a solder stud bump is formed again at the tip of the surface-treated second layer electrode, and the stud bump is made uniform by reflow. 15. The wafer according to claim 14, wherein the wafer has a third-layer electrode having the above-mentioned shape. 16. The solder stud bump is an Au or Cu stud bump.
The wafer according to claim 4 or claim 15. 17. A conductive material is formed on the organic material on the back surface of the wafer as in the case of molding or coating the organic material on the front surface of the wafer according to claim 15, again. 16. The wafer according to claim 15, which is molded or coated with a transparent organic material. 18. A front surface and a back surface of a wafer on which a circuit is formed in a previous step are molded or coated with an organic material, and the organic material existing in an electrode formation portion on the wafer wiring is etched or laser-irradiated. A wafer, characterized in that it is removed in the shape of a hole or groove, and an electrode is formed at the location removed in the shape of a hole or groove. 19. An organic material having a good thermal conductivity is molded on the organic material on the back surface of the wafer after forming an electrode at the portion removed in the hole shape or the groove shape according to claim 18. The wafer according to claim 18, wherein the wafer is formed by. 20. After forming an electrode in the hole-shaped or groove-shaped removed portion according to claim 18, an organic material is molded or coated on the organic material on the surface of the wafer again. The organic material present at the electrode formation portion of the first layer on the wafer is removed into a hole shape or a groove shape by etching or laser irradiation, and a second portion is removed in the hole shape or the groove shape. The method of claim 1, further comprising repeating the steps of forming the layer of electrodes.
8. The wafer according to item 8. 21. A solder wire electrode is formed at an electrode forming position on a wafer wiring with respect to a wafer on which a circuit is formed in a previous step, and an organic material is molded or coated on both front and back surfaces of the wafer, The wire electrode, the tip of which is exposed from the organic material at the same height as or higher than that of the organic material, is subjected to surface treatment such as polishing or etching of the tip to form the first layer. A stud bump of solder is formed on the tip of the surface-treated first layer electrode, and the stud bump is made uniform by reflow to form a second layer electrode. Wafer. 22. The wafer according to claim 21, wherein the solder wire electrode or the solder stud bump is made of Au or Cu. 23. A stud bump of solder is formed at an electrode forming portion on a wafer wiring on a wafer on which a circuit is formed in a previous step, and the stud bump is leveled to a uniform shape to form an electrode. A wafer characterized in that an organic material is molded or coated on the back surface of the wafer. 24. A stud bump of solder is formed at an electrode forming portion of a wafer wiring on a wafer on which a circuit is formed in a previous step, and the stud bump is leveled to have a uniform shape. , A mold or coating of an organic material, and the tip of the leveled stud bump, the tip of which is exposed from the organic material by the same height as or higher than the organic material, Polishing,
Alternatively, the wafer is characterized in that it is formed into an electrode by performing a surface treatment of etching. 25. The tip portion of the leveled stud bump, the tip portion of which is exposed from the organic material at a height comparable to or higher than that of the organic material according to claim 24. After polishing or etching surface treatment to form an electrode, a solder stud bump is formed again at the tip of the surface-treated electrode, and the stud bump having a uniform shape is formed by reflow. The wafer according to claim 24, wherein the wafer comprises two layers of electrodes. 26. The solder stud bump is an Au or Cu stud bump.
The wafer according to claim 3, claim 24, or claim 25.