JP2000323605A - Semiconductor device, manufacture thereof, electronic device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ease a thermal stress resulting from thermal expansion difference between a substrate and a chip by arranging a resin layer including a porous resin between a passivation film and a conductor layer. SOLUTION: After a passivation film 3 having a predetermined aperture 8 is formed on a semiconductor element 1, this film is coated by the spin coating method with a photosensitive polyimide varnish (glass transition temperature >250 deg.C) that becomes a first resin layer 4, and an internal porous film (vacant hole coefficient is about 30%) is formed by blowing hot air. Next, a conductor wiring 5 is formed in a predetermined shape by eliminating an organic material on the semiconductor element electrode 2. A second resin layer 5 consisting of diversified epoxy resin (elasticity at 25 deg.C=2.2 Gpa, glass transition point = 120 deg.C, breakdown elongation = 9%, thickness 3 μm) is formed to cover the conductor wiring 6. As a result, a stress generated due to the expansion coefficient difference between the substrate and chip can be eased by deformation of wiring, first resin layer 4 and second resin layer 5. Moreover, since the porous polyimide has a good dielectric property, electrostatic capacity is reduced and signal characteristic can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a wiring board (circuit board) and a method of manufacturing the same for electronic equipment in which an LSI is mounted on a substrate and functions. In particular, the present invention relates to a structure of a semiconductor element suitable for high-density mounting, a chip-size package with improved connection reliability, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a method of directly connecting an LSI to a wiring board, a method such as a wire bond (WB) or a tape automated bond (TAB) has been mainly used. In these systems, Au is flexible and easily deformed plastically.
It is characterized in that a thin wire or the like is used to connect between an external connection terminal of the LSI and a connection electrode on a wiring board. By having such a connection portion that is easily plastically deformed, a difference in thermal expansion between the LSI and the wiring board in a heating step at the time of connection and after the connection is absorbed by the deformation of the connection portion, and high connection reliability can be ensured. 1 prior art).

However, in the first prior art,
Due to the connection method itself, there is a problem that the external connection terminals of the LSI have no other option than to be arranged on the four sides of the LSI, and it is difficult to cope with an increase in the number of connection terminals of the LSI.

In order to solve the problem of the first prior art, the external connection terminals of the LSI are arranged in an area array, and a solder ball is provided between the external connection terminals of the LSI and the connection electrodes on the wiring board. A connection method has been proposed (second prior art).

In the second prior art, since the LSI and the wiring board are directly connected only by minute solder balls in an area array arrangement, there is an advantage that the mounting area does not need to be increased even if the number of connection terminals is increased. is there.

However, in the second prior art, L
Since the structure has a structure in which the difference in thermal expansion between the SI and the wiring board is absorbed only by the fine solder balls, the reliability of the connection portion is not always high. When the difference in thermal expansion between the LSI and the wiring board is large, the connection portion is broken due to displacement exceeding the plastic deformation limit of the solder ball, or the deformation is repeated even if the displacement is small even below the plastic deformation limit. This may cause fatigue destruction.

As a technique for improving the reliability of the connection portion by improving the disadvantages of the second conventional technique, a resin called an underfill resin is injected and cured into a space between the LSI and the wiring board to mount the LSI on the LSI. There is a method of fixing a substrate (hereinafter referred to as an LSI substrate fixed body). According to this technology, LSI
By fixing the substrate and the mounting substrate, the thermal stress is dispersed throughout the fixed body of the LSI substrate, the amount of distortion generated in the solder joint is averaged, and the destruction of the joint can be prevented (third conventional technique).

However, in the third prior art, since the underfill is filled from a small gap between the LSI and the substrate, it takes a long time to fill the underfill, the filling is not uniform over the whole, or the void is filled. (Underfill filling failure) (first problem in the third conventional technique).

Further, as a result of the thermal stress in the surface direction of the substrate, which has been released in the form of plastic deformation of the solder joint, acting on the entire fixed body of the LSI substrate, the fixed body of the LSI substrate is deformed in the thickness direction thereof. The phenomenon that the whole warps occurs. This deformation may cause a problem that the wiring in the substrate is easily broken or the element characteristics in the LSI fluctuate (second problem in the third conventional technique).

Further, in order to reduce the underfill filling defect (first problem in the third prior art), the filling operation is performed under different conditions depending on the shape and size of each LSI chip. When a large number of LSIs are mounted, there is also a problem that the operation becomes complicated (third problem in the third conventional technique).

In order to solve the problem of the third prior art, Japanese Patent Laid-Open No. 10-125705 proposes a technique of filling a sealing resin by a compression molding method (fourth prior art).

In this technique, since the LSI and the mounting board are mounted in a mold and the resin is compression-molded, underfill filling failure (the first problem in the third conventional technique) does not occur.

[0013] However, by fixing with a rigid resin so as to enclose the solder joint, the thermal stress is reduced by the LSI.
The third prior art is the same as the third prior art from the viewpoint of dispersing the solder on the entire substrate fixed body. Although the thermal stress in the creeping direction applied to each solder ball is reduced, this is the second problem in the third prior art. There is no solution to the warpage of the substrate.

As another technique for solving the problems of the second and third prior arts, JP-A-10-092865 discloses L.
After forming a thin film wiring composed of a resin layer, a wiring layer, and a resin layer on a passivation film of an SI, it is proposed to connect a connection electrode (package electrode) provided on the thin film wiring to a connection electrode on a mounting board. (Fifth prior art).

The first feature of the fifth prior art is that the joint between the LSI and the mounting board is composed of solder balls and thin film wiring, and a resin layer is arranged around the thin film wiring. It has become. By adopting such a structure, the difference in thermal expansion between the LSI and the wiring board is dispersed between the solder ball and the thin film wiring, and the resin layer absorbs the impact, so that the solder ball breaks (the second conventional problem). Can be prevented. Further, since the LSI and the mounting board are not fixedly bonded, deformation of the LSI and the mounting board (a second problem in the third conventional technique) can be suppressed.

A second feature of the fifth prior art is that a thin film wiring composed of a first resin layer, a wiring layer and a second resin layer is formed on the passivation film before cutting the LSI into individual pieces. is there. Through such a manufacturing process, a plurality of LSI chips can be collectively processed on a wafer, and after separating the LSI chips into individual pieces,
There is no need to fill the LSI chip with an underfill (third problem in the third conventional technique).

From the foregoing, it has been found that the fifth prior art can substantially solve the problems of the first to fourth prior arts.

[0018]

SUMMARY OF THE INVENTION The present inventors have fundamentally solved the problem of connection reliability between a chip and a substrate, and have realized a high-density mounting chip and a chip manufacturing technology with good connection reliability at low cost. As a result, the fifth conventional technique has the following problems (1) to (7) and requires further contrivance.

(1) The step of forming an opening for exposing the semiconductor element electrode portion in the first resin layer formed on the passivation film is etching. JP 10-092865
In the publication, the first resin layer is described as being any one of a polyimide resin, an epoxy resin, and a silicone resin. However, since these are all thermosetting resins and have high chemical resistance, they are etched. Removal is not easy.

(2) An etching resist generally used does not have resistance to the conditions under which the first resin layer can be removed by etching. Therefore, in order to form a first resin layer having a desired opening, a resist is formed to be considerably thicker than the first resin layer, a multilayer resist method is used, or an etching resist of a special material is used. Such,
It is complicated and requires a long time and high cost.

(3) Since the first insulating layer is formed by etching, it is inevitable that the upper end of the cross-sectional shape of the opening is widened. If the upper end of the opening is widened, the distance between the opening and the adjacent opening is narrowed, so that a connection failure or a short circuit is likely to occur. In addition, there is a problem that the positional accuracy requirement of the etching resist in the photolithography process becomes severe.

(4) In order to suppress the above problems (1) to (3), it is necessary to make the thickness of the first resin layer extremely small. However, making the first resin layer thin is an initial object of the invention. The stress relaxation function of the thin film wiring layer cannot be expected.

(5) JP-A-10-092865 states that stress is relaxed by the first resin layer, the second resin layer, and the polyimide resin layer. However, LSI
The elastic modulus of (Si) or wiring (Cu) is about 100 times larger than that of the resin material. Therefore, even if these resin layers are present, the influence on the amount of thermal expansion of the LSI and the wiring is negligible, and the difference in thermal expansion between the LSI and the mounting board is not reduced only by the technology proposed in this publication.

(6) Conversely, since the first resin layer is formed below the thin film wiring layer, a stress is generated by the first resin layer having a linear expansion coefficient several times larger than that of the wiring layer to push up the package electrode. When this stress acts on the wiring layer, there is a new problem that the wiring is easily broken.

(7) As is clear from the above (1) to (6), in order to achieve the initial object of the invention, the first resin layer and the second resin layer used for the thin film wiring layer have a specific thickness. , Linear expansion coefficient, and cross-sectional shape, and have to have physical property values (heat resistance, workability) in a specific range compatible with the process.

An object of the present invention is to provide a low-cost semiconductor device which solves the problem of the fifth prior art and reliably reduces stress caused by a difference in thermal expansion with a mounting substrate, and a method of manufacturing the same. .

[0027]

In order to achieve the above object, at least one resin layer is provided on a passivation film on a surface of a semiconductor element, and the semiconductor layer is provided inside the resin layer and / or on the surface of the resin layer. In a semiconductor device having a conductor layer of a desired shape connected to an element electrode portion, in the present invention, the resin layer includes at least one layer made of a porous resin. By using a resin layer containing at least one layer made of a porous resin, the stress relaxation characteristics of the resin are improved, and as a result,
The function of alleviating the thermal stress generated due to the difference in thermal expansion between the substrate and the chip is enhanced.

The porous resin suitable for the present invention has a glass transition temperature Tg or melting point mp of 200 ° C. or more. Specific examples of such a porous material include porous polyimide, porous polysulfone, and porous polyamideimide. Among them, porous polyimide is particularly preferable.

When the glass transition temperature or the melting point is 200 ° C. or lower, the porosity is not lost during the manufacturing process of the semiconductor device or the soldering process for connecting the semiconductor device and the real substrate. The reason for this is that the stress relaxation characteristic, which is the purpose of the above, is reduced. Conversely, there is no particular upper limit as long as the glass transition temperature Tg or the melting point mp is 200 ° C. or higher, and it can be appropriately selected in consideration of factors such as workability, price, and availability of the material. .

In the present invention, a porous resin having a porosity of 3% or more and less than 90% is preferably used. If the porosity is less than 3%, the stress relaxation property which is the object of the present invention is not sufficient, and if the porosity exceeds 90%, the mechanical strength (elongation at break, breaking strength) of the resin decreases. It no longer functions as a wiring insulator.

When a porous resin is used for the wiring insulating layer, the treatment liquid is taken into the pores during the process, or the surface of the pores adsorbs water vapor, and the insulating properties and the dielectric constant of the pores are reduced. May cause degradation. In the present invention, in order to eliminate such a danger, a device for sealing the opening on the surface of the porous resin is devised. More specifically, in the present invention, the following (1) or (2) is used to
Seal the opening on the surface of the porous resin.

(1) The resin provided on the passivation film is composed of at least three layers, and the porous resin is arranged so as not to correspond to either the uppermost layer or the lowermost layer of the resin layer.

(2) The porous resin is formed so as to have a cross-sectional structure including a surface skin layer and an internal porous layer.

In the present invention, in order to exhibit the stress relaxation characteristics of the resin layer containing the porous resin having the above-described characteristics, the conductor layer connected to the semiconductor element electrode portion and the passivation film on the surface of the semiconductor element are required. The resin layer is formed therebetween. By arranging a resin film containing a porous resin having a stress relaxation function between the passivation film and the conductor layer, the resin layer deforms following the stress acting on the wiring, and as a result, the stress is reduced Is done.

The semiconductor device having the above-described stress relaxation function obtained by the technique of the present invention can be used as a chip size package. Conversely, by using the semiconductor device as a chip size package, the stress relaxation function can be improved. Can be used effectively.

In the present invention, in order to form a resin layer having the above-described stress relaxation characteristics, a resin film containing a porous resin is formed through the following steps (1) to (4).

(1) a step of forming a passivation film on a wafer on which a large number of the semiconductor elements are formed; (2)
Forming a layer to be an adhesive at a desired position on the passivation film; (3) attaching a porous film formed in a desired shape in advance on the adhesive layer;
(4) A step of forming a conductor layer of a desired shape connected to the electrode portion of the semiconductor element on at least one or more resin layers including the porous film.

Through these steps, a resin layer containing a porous resin having a stress relaxation property is formed at a desired location, and as a result, thermal stress generated between the mounting substrate and the LSI chip is formed. To relax. The above (1)
Known or customary steps may be added between steps (4) to (4) or before or after the steps, if necessary. For example,
After the step (3), a step of forming an adhesive layer for improving the adhesiveness with the conductor layer on the upper surface of the porous film is inserted, or the surface of the porous film is heated to form an opening in the surface. A step of fusing and sealing may be inserted.

In the present invention, as a second method for forming a resin layer having the above-described stress relaxation characteristics, a resin layer containing a porous resin is formed through the following steps (1) to (4). I do.

(1) forming a passivation film on a wafer on which a large number of the semiconductor elements are formed; (2)
A step of applying a varnish serving as a precursor of a porous resin to a desired portion of the semiconductor element on which the passivation film is formed; (3) a step of forming a porous resin layer from the varnish of the porous resin precursor; (4) Forming a conductor layer of a desired shape connected to an electrode portion of the semiconductor element on at least one or more resin layers including the porous film.

In the present invention, there is no problem in making the most of known and commonly used techniques in these steps.
When applying the varnish which is a precursor of the porous resin in the above step (2), (a) screen printing is performed, and (b) the resin is removed from unnecessary portions by laser processing after forming the entire surface. (C) apply a water- and oil-repellent agent to varnish unnecessary areas beforehand, and then apply varnish to the entire surface. (D) After forming a resist in unnecessary areas in advance by photolithography technology, Techniques such as applying varnish to the entire surface can be used. If necessary, the order of the positive part may be changed. For example, after forming a porous resin layer from a porous resin precursor varnish applied on the entire surface, unnecessary portions are subjected to photolithography or laser processing techniques. May be removed. Further, it goes without saying that there is no problem even if known and commonly used steps are added between the steps (1) to (4) or before or after the steps as necessary.

In the present invention, a manufacturing method of a semiconductor device suitable as a chip size package has been established by providing a manufacturing method and a manufacturing technique for forming a resin layer having the above-described stress relaxation characteristics. In addition, by providing a chip size package including a stress relaxation function as described above and a method of manufacturing the chip size package, a chip size package with high connection reliability can be obtained.By using this chip size package, High performance and high reliability electronic equipment could be provided.

According to the present invention, an inexpensive semiconductor device having high connection reliability, excellent electric characteristics, and suitable for high-density mounting is obtained by forming a resin layer having the above-described characteristics on a semiconductor device. A high-performance electronic device can be provided by appropriately connecting such a semiconductor device to another wiring board by soldering.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 1 shows a part of a cross section of a semiconductor device according to an embodiment of the present invention, in which a semiconductor element electrode part, a wiring drawn out therefrom, a package electrode part, and peripheral parts thereof are shown. 3 shows a cross-sectional structure. Hereinafter, the structure of the present embodiment will be described with reference to the drawings.

The semiconductor device of this embodiment is electrically connected to the mounting substrate through the package electrode 7. The package electrode 7 is electrically connected to the semiconductor element electrode section 2 by the wiring 6. A first resin layer is provided below the wiring 6,
A second resin layer is formed on the wiring 6. A passivation film 3 exists between the first resin layer and the semiconductor element 1.

In this embodiment, the first resin layer is made of porous polyimide (glass transition temperature> 250 ° C.), the second resin layer is a modified epoxy resin (elastic modulus at 25 ° C. = 2.2 GPa,
Glass transition point = 120 ° C, elongation at break = 9%, film thickness 3μ
m).

The formation of the first resin layer was performed according to the following procedure. First, after forming a passivation film having a desired opening on the semiconductor element 1, a varnish serving as a precursor of a porous polyimide as a first resin layer was spin-coated. Hot air was blown onto the surface of the coating film thus obtained to form a skin layer, and an internal porous film was formed using a so-called phase change method (porosity: about 30%). In the ordinary phase change method, drying or heat treatment is performed after internal pore formation. In this embodiment, an opening 8 is provided by a photolithography process to expose the semiconductor element electrode portion 2 before the heat treatment. Heat cured. In this example, a porous film produced by a phase inversion method on a passivation film was used, but there is no particular problem with any known and commonly used porous film forming method.

Thereafter, in order to remove organic substances and the like chemically adsorbed on the semiconductor element electrode portion 2, ashing with oxygen plasma is performed, and then a conductor to be a wiring is formed by sputtering.
By a so-called subtractive method, a conductor wiring 6 having a desired shape was formed through film formation of an etching resist, exposure, development, etching, and removal of the resist.

Finally, a second resin layer was formed so as to cover the conductor wiring, thereby completing the semiconductor device of this embodiment. When this semiconductor device was mounted on a mounting substrate, the stress caused by the difference in expansion between the substrate and the semiconductor device could be alleviated by the deformation of the wiring, the first resin layer, and the second resin layer.
In addition, since the porous polyimide has good dielectric characteristics, the capacitance of the circuit is reduced and the signal characteristics are improved.

Example 2 FIG. 2 is a part of a cross section of a semiconductor device showing a second embodiment according to the present invention, in which a semiconductor element electrode portion, a wiring drawn therefrom, a package electrode portion, and the like are shown. 2 shows a cross-sectional structure around the. Hereinafter, the structure of the present embodiment will be described with reference to the drawings.

The semiconductor device of this embodiment is electrically connected to the mounting substrate through the package electrode 7. The package electrode 7 is electrically connected to the semiconductor element electrode section 2 by the upper wiring 9 and the wiring 6. A second resin layer 5 and a first resin layer 4 are provided below the upper layer wiring 9 and the wiring 6, respectively.
Is formed. The passivation film 3 exists between the first resin layer 4 and the semiconductor element 1. The difference between the structure of this embodiment (FIG. 2) and the structure of the first embodiment (FIG. 1) is that the number of resin layers is increased by one. Although the manufacturing process becomes longer due to the addition of one resin layer, the function (photosensitivity, porosity) of the first resin layer 4 in Example 1 is separated into the first resin layer 4 and the second resin layer 5. This has the advantage that the range of materials and processes can be increased.

In this embodiment, the first resin layer 4 is made of polyimide (glass transition temperature> 300 ° C.), and the second resin layer 5 is made of porous polyimide (glass transition temperature> 250 ° C.)
As the third resin layer 10, the second resin layer 5 of Example 1 was used.

The manufacturing procedure of the structure shown in FIG. 2 according to this embodiment is as follows. First, after a passivation film having a desired opening is formed on the semiconductor element 1, the first resin layer 4
Photosensitive polyimide varnish (Hitachi Chemical DuPont Co., Ltd.)
Was spin-coated. After pre-baking at 90 ° C. for 2 minutes, a desired opening 8 is formed by exposure, post-exposure baking, and development, and the solvent is removed, but at 120 ° C. for 30 minutes and 200 ° C. for 2 hours so as not to completely cure. Heated.

Thereafter, ashing is performed with oxygen plasma to remove organic substances and the like which are chemically adsorbed on the semiconductor element electrode portion 2, and then plating of the wiring conductor 6 is formed on the incompletely cured first resin layer. A conductive wiring 6 having a desired shape is formed by forming a plating resist film, exposing, developing, pattern plating, removing the resist, and removing the underlying conductive film (pattern separation) by a so-called semi-additive method. Formed.

The thus obtained product was treated at 140 ° C. for 2 hours to sufficiently remove the moisture absorbed by the first resin layer 4.
On top of this, a porous polyimide film (pore size 0.5 micrometer or less) previously processed into a desired shape
It was pressed at 230 ° C. under a pressure of 0 N / m and brought into close contact. Since the first resin layer 4 is in an incompletely cured state at the time of the close contact operation, the porous polyimide film is fixed by the adhesive force to become the second resin layer 5, and at the same time, the first resin layer of the porous polyimide film is formed. The opening of the fine hole on the side surface is sealed with the first resin layer resin.

Thereafter, the upper wiring 9 is formed by the same process as the formation of the conductor wiring 6, and then the third resin layer 10 is formed, thereby completing the semiconductor device of this embodiment.
When this semiconductor device is mounted on a mounting substrate, the stress generated by the expansion difference between the substrate and the semiconductor device is increased by the upper wiring 9, the wiring 6, the first resin layer 4, the second resin layer 5, and the third resin layer 10, respectively. It could be alleviated by deformation.

Example 3 In this example, a varnish serving as a precursor of a porous polyimide was applied instead of using a porous polyimide molded in a desired shape in advance as the second resin layer 5. Is almost the same as Also,
Along with the change in the second resin layer forming method, the first resin layer forming method was also slightly changed.
The sectional view showing the embodiment is the same as FIG.

The procedure for manufacturing the structure shown in FIG. 2 according to this embodiment is as follows. First, a photosensitive polyimide varnish (manufactured by Hitachi Chemical DuPont) serving as a first resin layer after a passivation film having a desired opening is formed on a semiconductor element.
Was spin-coated. After a pre-bake treatment at 90 ° C. for 2 minutes, a desired opening 8 is formed by exposure, post-exposure bake, and development.
It was completely cured by heating at 350 ° C. for 1 hour for 0 minutes.

Thereafter, in the same manner as in Example 2, oxygen plasma ashing, deposition formation of a conductive film under plating, film formation of a plating resist, exposure, development, pattern plating, resist removal,
The conductive wiring 6 having a desired shape was formed by sequentially removing the underlying conductive film (pattern separation).

The thus obtained product was treated at 140 ° C. for 1 hour to sufficiently remove the water absorbed by the first resin layer 4.
On this, the porous polyimide varnish precursor used as the first resin layer of Example 1 was screen-printed, and a porous film was formed in the same procedure as in Example 1, and the surface of the porous film was further heated. The second resin layer 5 was obtained by pressing the plate to fuse the openings of the fine holes formed in the skin layer.

Thereafter, the upper wiring 9 and the third resin layer 10 were formed in the same steps as in the second embodiment, and the semiconductor device of the present embodiment was completed. When this semiconductor device is mounted on a mounting substrate, the stress generated by the expansion difference between the substrate and the semiconductor device is increased by the upper wiring 9, the wiring 6, the first resin layer 4, the second resin layer 5, and the third resin layer 10, respectively. It could be alleviated by deformation.

In this embodiment, since the porous polyimide varnish is not processed by photolithography, the thickness of the second resin layer (porous polyimide layer) 5 is not limited by the light transmission amount, exposure sensitivity and the like. Therefore, the stress relaxation function can be increased by forming the second resin layer 5 thick.

Example 4 FIG. 3 is a part of a cross section of a semiconductor device showing a fourth embodiment according to the present invention, and shows a semiconductor element electrode part, a wiring drawn therefrom, a package electrode part, and the like. 2 shows a cross-sectional structure around the. Hereinafter, the structure of the present embodiment will be described with reference to the drawings.

The semiconductor device of this embodiment is electrically connected to the mounting substrate through the package electrode 7. The package electrode 7 is electrically connected to the semiconductor element electrode section 2 by the upper wiring 9 and the wiring 6. The upper wiring 9 is the second resin layer 5
And both are covered with the third resin layer 10. On the other hand, the wiring 6 is formed on the first resin layer 4,
The second resin layer 5 covers it. Further, a passivation film 3 exists between the first resin layer 4 and the semiconductor element 1. The difference between the structure of the present embodiment (FIG. 3) and the structure of the first embodiment (FIG. 2) is that the second resin layer 5 covers the wiring 6 and the first resin layer 4.

The manufacturing procedure of the structure shown in FIG. 3 according to the present embodiment is the same as that of the third embodiment except that the second resin layer 5 is formed by spin-coating and then laser processing.

First, the procedure for forming the first resin layer 4 is as follows: formation of a passivation film, spin coating of a photosensitive polyimide varnish (manufactured by Hitachi Chemical DuPont), pre-baking (90 ° C. for 2 minutes), Exposure, post-exposure bake, development, 120 ° C for 30 minutes, 200 ° C for 30 minutes,
Heat at 350 ° C for 1 hour (complete curing).

Thereafter, similarly to the third embodiment, oxygen plasma ashing, vapor deposition formation of a conductive film under plating, film formation of a plating resist, exposure, development, pattern plating, resist removal,
The conductive wiring 6 having a desired shape was formed by sequentially removing the underlying conductive film (pattern separation).

The thus obtained product was treated at 140 ° C. for 1 hour to sufficiently remove the moisture absorbed by the first resin layer, and the porous polyimide varnish precursor used as the first resin layer in Example 1 was further placed thereon. Was spin-coated, and a porous resin film was formed in the same procedure as in Resin Example 3, and heat-sealing of the fine hole openings was performed to form a second resin layer 5. Thereafter, a desired opening 11 is formed by an infrared laser (manufactured by Hitachi Seiko; LCO-1A21), a predetermined processing residue removal process is performed, and the upper layer wiring 9 and the third resin are formed in the same steps as in the third embodiment. The layer 10 was formed to complete the semiconductor device of this embodiment. When this semiconductor device is mounted on a mounting substrate, the stress generated by the expansion difference between the substrate and the semiconductor device is increased by the upper wiring 9, the wiring 6, the first resin layer 4, the second resin layer 5, and the third resin layer 10, respectively. It could be alleviated by deformation.

In this embodiment, since the porous polyimide varnish is not processed by photolithography, the thickness of the second resin layer (porous polyimide layer) 5 is not limited by the light transmission amount, exposure sensitivity and the like. Therefore, the stress relaxation function can be increased by forming the second resin layer 5 thick. Also, compared with the sheet bonding of the second embodiment and the screen printing of the third embodiment, the laser processing has a better positional accuracy,
Since the microfabrication is easy, it can be applied to a semiconductor device with higher density and more pins.

Embodiment 5 In this embodiment, a varnish containing a precursor of a porous polyimide is applied on a passivation film in the step of forming the first resin layer 4 in the same manner as in Embodiment 1, and the device is formed by a phase inversion method. The above was made porous. However, without using the photosensitive properties of the polyimide varnish, a photosensitive resist is separately prepared and a resist is selectively formed only on the semiconductor element electrode portion in advance, and then the varnish containing the polyimide precursor is removed. A first resin layer was formed by a procedure of spin-coating and simultaneously stripping the resist in a porous process, and thereafter, the same cross-sectional structure (FIG. 1) as in Example 1 was produced using substantially the same procedure and material as in Example 1. .

The manufacturing procedure of the structure shown in FIG. 1 according to this embodiment is as follows. First, a desired opening was formed in the passivation film in the same manner as in Example 1. Then, prior to the application of the porous polyimide precursor varnish, a liquid positive photosensitive resist (manufactured by Tokyo Ohka) is spin-coated, exposed and developed through a desired mask, and a resist pattern is formed only at the opening of the first resin layer. Was formed. Thereafter, as in Example 1, the first resin layer 4 was formed by spin coating of a porous polyimide precursor varnish, forming a skin layer, forming a porous layer by a phase inversion method, and thermosetting. In addition, the said resist pattern is simultaneously removed in a porous process, and the opening 8 is formed.
The semiconductor element electrode part 2 was exposed. Thereafter, similarly to the third embodiment, the thermal fusion of the fine hole opening, the upper wiring 9, the third resin layer 1
0 was formed to complete the semiconductor device of this example.

When this semiconductor device is mounted on a mounting board,
The stress generated by the difference in expansion between the substrate and the semiconductor device is applied to the wiring 6, the upper wiring 9, the first resin layer 4, the second resin layer 5,
The deformation can be alleviated by the deformation of the resin layer 10.

[0074]

According to the present invention, an inexpensive semiconductor device having high connection reliability and excellent electrical characteristics and suitable for high-density mounting can be obtained. By connecting with a solder, high-performance electronic equipment can be provided.

[Brief description of the drawings]

FIG. 1 is a part of a schematic cross-sectional view of a semiconductor device showing an example of an embodiment according to the present invention.

FIG. 2 is a part of a schematic sectional view of a semiconductor device showing an example of a second embodiment according to the present invention;

FIG. 3 is a part of a schematic sectional view of a semiconductor device showing an example of a third embodiment according to the present invention;

[Explanation of Codes] Semiconductor element 2. 2. Semiconductor element electrode part 3. Passivation film First resin layer 5. Second resin layer 6. Wiring 7. 7. Package electrode 8. Opening in first resin layer 9. Upper layer wiring for connecting wiring 6 and package electrode 7 Third resin layer 11. Opening in the second resin layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuko Ito 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. Hitachi, Ltd. Production Technology Laboratory

Claims (10)

[Claims] 1. A conductor layer having a desired shape connected to the semiconductor element electrode portion, wherein at least one resin layer is provided on a passivation film on the surface of the semiconductor element, and the resin layer is provided inside and / or on the surface of the resin layer. Wherein the resin layer includes at least one layer made of a porous resin. 2. The semiconductor device according to claim 1, wherein at least a part of the resin layer provided on the passivation film contains a porous resin, the porous resin has a glass transition temperature Tg or a melting point mp of 200. A semiconductor device having a porosity of at least 3 ° C. and less than 90%. 3. The semiconductor device according to claim 1, wherein when at least a part of the resin layer provided on the passivation film contains a porous resin, the porous resin is a porous polyimide. Semiconductor device. 4. The semiconductor device according to claim 1, wherein at least a part of the resin layer provided on the passivation film contains a porous resin, the porous resin comprises the following (1) or (2). A semiconductor device that satisfies any of (2). (1) The resin provided on the passivation film includes at least three layers, and the porous resin does not correspond to either the uppermost layer or the lowermost layer of the resin layer. (2) The porous resin comprises a surface skin layer and an internal porous layer. 5. The semiconductor device according to claim 1, wherein at least a part of the resin layer provided on the passivation film contains a porous resin, wherein the porous resin comprises a semiconductor element electrode portion. A semiconductor device formed between a conductor layer of a desired shape connected to the semiconductor device and a passivation film on the surface of the semiconductor element. 6. A conductor having a desired shape and having at least one resin layer provided on a passivation film on a surface of a semiconductor element and connected to an electrode portion of the semiconductor element inside the resin layer and / or on the surface of the resin layer. In a semiconductor device having a layer, at least a part of the resin layer includes a layer made of a porous resin, and the resin layer containing the porous resin is formed through the following steps (1) to (4). A method of manufacturing a semiconductor device. (1) a step of forming a passivation film on a wafer on which a large number of the semiconductor elements are formed; (2) a step of forming a layer serving as an adhesive at a desired location on the passivation film; (3) the adhesive Attaching a porous film formed in a desired shape in advance on the layer, (4) a desired shape connected to the electrode portion of the semiconductor element on at least one or more resin layers including the porous film Forming a conductor layer of the above. 7. A conductor having a desired shape connected to an electrode portion of the semiconductor element, wherein at least one resin layer is provided on the passivation film on the surface of the semiconductor element, and at least inside the resin layer and / or on the surface of the resin layer. In a semiconductor device having a layer, at least a part of the resin layer includes a layer made of a porous resin, and the resin layer containing the porous resin is formed through the following steps (1) to (4). A method of manufacturing a semiconductor device. (1) a step of forming a passivation film on a wafer on which a large number of the semiconductor elements are formed; and (2) applying a varnish serving as a precursor of a porous resin to a desired portion of the semiconductor element on which the passivation film is formed. (3) a step of forming a porous resin layer from the porous resin precursor varnish, (4) an electrode portion of the semiconductor element on at least one or more resin layers including the porous film. A step of forming a conductor layer having a desired shape; 8. A chip size package having the configuration according to claim 1. 9. A method for manufacturing a chip size package by the method according to claim 6. 10. An electronic apparatus comprising the semiconductor device according to claim 1 or a chip size package according to claim 8 and another wiring board.