JPH03503342A - Semiconductor device package and its manufacturing method - Google Patents

Semiconductor device package and its manufacturing method

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Publication number
JPH03503342A
JPH03503342A JP1500158A JP50015888A JPH03503342A JP H03503342 A JPH03503342 A JP H03503342A JP 1500158 A JP1500158 A JP 1500158A JP 50015888 A JP50015888 A JP 50015888A JP H03503342 A JPH03503342 A JP H03503342A
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die
conductive
semiconductor device
semiconductor
package
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JP2664259B2 (en
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ロング，ジョン
シドロフスキイ，ラシェル，エス．
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エルエスアイ　ロジック　コーポレーション
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 半導体装置パッケージを製造する方法及び手段見朝勿分及 本発明は、半導体装置パッケージを製造する方法及び装置に関するものである。[Detailed description of the invention] Of course, the method and means for manufacturing a semiconductor device package will be described in detail. The present invention relates to a method and apparatus for manufacturing a semiconductor device package.

光泄ＩすＬ匙 従来の半導体装置パッケージは、サンドイッチ成形形態で製造されており、半導 体装置は封止されて、ダイの両側にパッケージを形成していた。成形処理後にパ ッケージを冷却すると、より大きな成形パッケージはカールする傾向があり、そ れにより欠陥性乃至は使用不能の装置とされる。Light excretion Isu L spoon Traditional semiconductor device packages are manufactured in a sandwich molded format, The body device was sealed to form a package on both sides of the die. Padding after molding process As the package cools, larger molded packages tend to curl; This makes the device defective or unusable.

また、パッケージに、半導体装置の要素へ湿気が浸透することを可能とするよう な小さな開口乃至は亀裂があると、半導体ダイの剥離が発生することがあり、そ れにより該装置を欠陥性のものとするか、又は該装置の動作寿命を減少させる場 合がある。更に、パッケージを構築する為にモールド即ち成形を使用することは 、パッケージの高さ及び面積を著しく増加させることとなる。Additionally, the package is designed to allow moisture to penetrate into the elements of the semiconductor device. Small openings or cracks can cause delamination of the semiconductor die; This may render the device defective or reduce its operating life. There is a case. Additionally, the use of molding to construct the package is , which would significantly increase the height and area of the package.

複合パッケージ組立体は、剛性リードフレーム及び薄い可撓性テープ状構成体で 形成される。該テープ状構成体は、リードフレームのリードへ接続されているリ ードフィンガーで構成されている。ボンドワイヤを包含する半導体組立体は、リ ードフレーム、テープ状構成体、ボンドワイヤ及び導電性リードを有する半導体 装置を取り囲む為に多数の成形ステップを必要とする２セクシヨンモールドを使 用して、封止させる。The composite package assembly consists of a rigid lead frame and a thin flexible tape-like structure. It is formed. The tape-like structure is connected to the leads of the lead frame. It consists of a board finger. Semiconductor assemblies containing bond wires are Semiconductor with board frame, tape-like structure, bond wires and conductive leads Using a two-section mold that requires multiple molding steps to enclose the device Use to seal.

半導体業界において標準的である従来の半導体モールドパッケージは、最大１６ ０本の導電性リードを受は付けることが可能であり、それは、典型的に、中心間 において５０乃至２５ミリインチの間の間隔があけられている。リード数が増加 すると、リードへ接続するボンドワイヤの数も増加する。ボンドワイヤの数が増 加すると、パッケージが大型化する。Traditional semiconductor mold packages, which are standard in the semiconductor industry, have up to 16 It is possible to attach zero conductive leads, which are typically center-to-center. They are spaced between 50 and 25 millimeters apart. Increased number of leads Then, the number of bond wires connected to the leads also increases. Increased number of bond wires If the size of the package is increased, the size of the package will increase.

半導体業界の主要目的は、より多くの導電性リードを有しているが一層小型のパ ッケージとした半導体装置を製造することである。パッケージが一層小型である と、一層多くのダイパッドを有する半導体ダイを使用することが可能であり、そ れは半導体組立体のリードの間隔が一層近接したものであることを必要とする。A key goal in the semiconductor industry is to create smaller semiconductor devices with more conductive leads. The goal is to manufacture semiconductor devices in packages. The package is smaller , it is possible to use a semiconductor die with more die pads, and This requires that the leads of the semiconductor assembly be more closely spaced.

その結果、動作の信頼性を改善すると共に、一層高速の回路動作速度を実現する ことが可能である。The result is improved operational reliability and faster circuit operating speeds. Is possible.

光−叫迎−」杵 本発明の目的とするところは、プラスチックパッケージ本体を形成する為のモー ルドプロセスに対する必要性を取り除いた新規で且つ改良した半導体パッケージ を提供することである。Light - Shouting -" Pestle It is an object of the present invention to provide a mold for forming a plastic package body. New and improved semiconductor package that eliminates the need for hard processing The goal is to provide the following.

本発明の別の目的とするところは、ワイヤボンディングを除去することの可能な 半導体パッケージを提供することである。Another object of the invention is to make it possible to eliminate wire bonding. Our goal is to provide semiconductor packages.

別の目的とするところは、比較的多数の導電性リード及び外部ピンを提供する半 導体パッケージを提供することである。Another objective is to provide a semiconductor with a relatively large number of conductive leads and external pins. The purpose of the present invention is to provide a conductor package.

本発明の更に別の目的とするところは、湿気からの高度の保護を可能とする半導 体パッケージを提供することである。It is a further object of the invention to provide a semiconductor which provides a high degree of protection from moisture. It is to provide a body package.

本発明によれば、テープはパターン化した絶縁層及び該絶縁層へ接続されている 導電層から形成されている。半導体ダイを該テープの１表面上のパッドへ取り付 は且つ該導電層のリードへ電気的に接続する。絶縁性被覆を該ダイ及びワイヤー リード上に付与する。ダイ取り付はパッドに対向する表面において、絶縁性テー プ要素を導電層へ付着させる。パッケージフレーム乃至は本体フレームを半導体 ダイ及び電気的接続部及びリードを取り巻くテープへ接続させる。該本体フレー ムは、本体フレーム頂部、ダイ及び導電性ワイヤー及びリード上に付与した封止 物質を閉じ込めるへく作用する。According to the invention, the tape is connected to a patterned insulating layer and to the insulating layer. It is formed from a conductive layer. attaching a semiconductor die to a pad on one surface of the tape; and electrically connects to the leads of the conductive layer. Insulating coating on the die and wire Grant on the lead. For die attachment, use insulating tape on the surface facing the pad. 3. Attach the drop element to the conductive layer. The package frame or main body frame is a semiconductor Connect to the tape surrounding the die and electrical connections and leads. The body frame The seal is applied to the top of the main body frame, the die and the conductive wires and leads. It acts to trap substances.

１実施例において、ワイヤーリードの変わりに導電性バンプを電気的接続用に使 用する。タブボンディングを使用して、該ダイ上に形成されているバンブと導電 層とを接続させる。その結果、半導体装置パッケージは、一層小型となり、且つ 増加した数のリード及び外部ピンを受番ブ付けることが可能である。In one embodiment, conductive bumps are used for electrical connections instead of wire leads. use Use tab bonding to connect the bumps and conductors formed on the die. connect layers. As a result, semiconductor device packages have become smaller and smaller. It is possible to number an increased number of leads and external pins.

し■吐Φ１１児 本発明を図面を参照してより詳細に説明する。11 children with vomiting The present invention will be explained in more detail with reference to the drawings.

第１図は部分的に本発明に基づいて構成された半導体組立体の断面側面図、 第２図は第１図の部分的組立体への半導体ダイの取り付けを図示しており、 第３図は該組立体の導電性リードフィンガーへのダイのワイヤボンディングを例 示しており、 第４図は半導体ダイ及びボンドワイヤー上への保護被覆の付与を示しており、 第５図は本発明に基づいて整合した背面テープへ取付ける為に反転させた部分的 組立体を示しており、第６図は該組立体へのフレーム本体の一体化を示しており 、 第７図は本発明に基づいて構成された半導体装置パッケージの断面図であり、 第８図は本発明に基づいて構成された半導体装置パッケージを図示した部分的に 開放した平面図であり、第８図のＡ−Ａ線は第５図及び第１図乃至第７図及び第 ９図の断面を取った切断線を表しており。FIG. 1 is a cross-sectional side view of a semiconductor assembly constructed partially in accordance with the present invention; FIG. 2 illustrates the attachment of a semiconductor die to the subassembly of FIG. 1; Figure 3 shows an example of die wire bonding to the conductive lead fingers of the assembly. It shows FIG. 4 shows the application of a protective coating over the semiconductor die and bond wires; Figure 5 shows a partially inverted version for attachment to aligned back tape according to the present invention. The assembly is shown, and FIG. 6 shows the integration of the frame body into the assembly. , FIG. 7 is a cross-sectional view of a semiconductor device package constructed based on the present invention, FIG. 8 is a partial diagram illustrating a semiconductor device package constructed in accordance with the present invention. This is an open plan view, and the A-A line in FIG. 8 is the same as in FIG. It represents the cutting line from which the cross section of Figure 9 was taken.

第９図は導電性バンブによって半導体ダイをパターン化した導電層へ一体化させ 且つ電気的に接続させる為にテープ自動化ボンディング（ＴＡＢ）を使用する半 導体装置パッケージの断面図であり、 第１０図は本発明の半導体装置パッケージの分解図である。Figure 9 shows how conductive bumps integrate a semiconductor die into a patterned conductive layer. and a semi-conductor that uses Tape Automated Bonding (TAB) to make the electrical connection. 1 is a cross-sectional view of a conductor device package; FIG. 10 is an exploded view of the semiconductor device package of the present invention.

図面全体にわたって、同様の数字は同様の要素を示している。Like numerals indicate like elements throughout the drawings.

完即Ｂ矢薙剣ＡＩｔ升 第１図を参照すると、本発明の実施において、ワイヤーホント可能なテープ１０ は、例えばデュポン社の商標名であるカプトン（Ｋａｐｔｏｎ）からなるパター ン化した絶縁層１２、及び該カプトン層へ一体化された全鍍金層１４から形成さ れている。該全鍍金層は、例えば、約３０乃至４０ミクロンの厚さである。米国 特許第４，７１１，３３０号に開示される如く、カプトン絶縁層１２をエッチし 且つパターン化してダウンボンディング用の空洞１３を形成する。米国特許第４ ，７７１，３３０号に開示される如く、全鍍金層１４もパターン化して絶縁層１ ２の「ウェッジ」部下側にギャップ２３を形成する。Kansoku B Yanagiken AIt Masu Referring to FIG. 1, in the practice of the present invention, a wire bondable tape 10 For example, a putter made of Kapton, a trademark of DuPont. It is formed from an insulating layer 12 which has been plated, and a fully plated layer 14 that is integrated into the Kapton layer. It is. The total plating layer is, for example, about 30 to 40 microns thick. US Etch the Kapton insulating layer 12 as disclosed in Patent No. 4,711,330. Then, it is patterned to form a cavity 13 for down bonding. US Patent No. 4 , 771,330, the entire plating layer 14 is also patterned to form the insulating layer 1. A gap 23 is formed on the lower side of the "wedge" of No. 2.

パターン化したワイヤボンド可能なテープ１０を基台１８内に位置させて、テー プ】０に平坦性を与える。アミコン（Ａｍｉｃｏｎ）９９０Ｇ　（アミコン社の 商標）等のダイ取り付は用エポキシ−２２を、ワイヤーボンド可能なテープ１０ の１表面上に形成したダイ取り付はパッド２０上に付与する。次いで、第２図に 示した如く、半導体ダイ２４を整合させ且つダイ取り付はエポキシ−上に配置さ せる。The patterned wirebondable tape 10 is positioned within the base 18 and the tape Gives flatness to 0. Amicon 990G (Amicon) For die attachment such as trademark), use epoxy 22 and wire bondable tape 10. A die attach formed on one surface of the pad 20 is applied. Next, in Figure 2 As shown, the semiconductor die 24 is aligned and the die attach is placed on the epoxy. let

該ダイを取付けたユニットを、約１時間の最大硬化時間の間約１−５０℃の最大 硬化温度で硬化させる為に炉内にいれる。The unit with the die attached is heated to a maximum temperature of about 1-50°C for a maximum curing time of about 1 hour. It is placed in a furnace to be cured at the curing temperature.

硬化したダイを取付けたユニットを１例えば米国特許第４．７９０，８９７号に 開示される如く、真空ヒーターブロック−にに配置させて、該ユニットを堅実に 且つ約２００℃の温度で保持する。次いで、該ユニットを、第３図に示した如く 、熱音波的に金ワイヤ−２６とワイヤーボンドさせて、ダイ２４とリードフィン ガー乃至はパターン化した金層１４の導電要素との間に電気的接続を形成する。A unit with a hardened die attached is shown in one example in U.S. Pat. No. 4,790,897. As disclosed, the unit is placed firmly in the vacuum heater block. and maintained at a temperature of about 200°C. Then, the unit was assembled as shown in FIG. The die 24 and the lead fin are wire-bonded to the gold wire 26 using thermosonic waves. Electrical connections are made between the conductive elements of the patterned gold layer 14.

例えばダウコーニング社のＱ　１．−４９３９等の基材に対して硬化剤を１対１ ０の混合比を有するシリコーンゲル２８を、最初に角部から初めて次いで該ゲル を該ダイの中央部に付与することにより、該ダイ上にダイ被覆として付与する。For example, Dow Corning's Q1. -1:1 hardening agent to base material such as 4939 The silicone gel 28 having a mixing ratio of 0 is added starting from the corners and then the gel is added. is applied as a die coating onto the die by applying it to the center of the die.

該ゲルを流動させて、該ダイ及びワイヤーを被覆させ（第４図参照）るが、米国 特許第４，７１１，３３０号に開示する如く、所定の区域内に閉じ込める。次い で、該ダイを被着したユニットを約１時間の間約１５０℃で炉内において硬化さ せる。The gel is allowed to flow to coat the die and wires (see Figure 4), but the US Confinement within a predetermined area, as disclosed in Patent No. 4,711,330. Next The die-coated unit was then cured in an oven at about 150°C for about 1 hour. let

ダイ被覆の硬化の後に、該ユニットを反転させ且つ、第５図に示した如く、！１ 合台３０内に位置させる。基台１８は、ダイ、ワイヤ及びダイ被覆が損傷するこ とから保護する為に使用している。１表面上に接着剤３４を有する絶縁性テープ 要素３２を、ワイヤーボンド可能なテープ１０の一部である導電層１４の下部表 面乃至は背面上に固定させる。約１００〜１５０℃の範囲内の温度でホットプレ ート上において予熱させた金属ブロック３６を、約１乃至１゜５分の間テープ要 素３２と接触させて、接着剤３４を流動させ且つ導電性要素１４の背面へ付着さ せ、一方テープ１０を整合状態に維持する。後の硬化プロセス期間中に接着剤３ ４が台３０へ引っ付くことがないことを確保する為に、台３０をより広い窓を持 った台（不図示）と置換させる。After curing of the die coating, invert the unit and as shown in FIG. 5! 1 It is located in the combination stand 30. The base 18 prevents damage to the die, wires, and die coating. It is used to protect against. Insulating tape with adhesive 34 on one surface Element 32 is attached to the lower surface of conductive layer 14 that is part of wirebondable tape 10. It is fixed on the face or back. Hot preheat at a temperature within the range of approximately 100-150°C. Place the preheated metal block 36 on top of the tape for approximately 1 to 1.5 minutes. element 32 to cause adhesive 34 to flow and adhere to the back side of conductive element 14. while maintaining the tape 10 in alignment. Adhesive 3 during the post curing process To ensure that 4 does not stick to the pedestal 30, the pedestal 30 has a wider window. Replace it with a stand (not shown).

硬化を達成する為に、該ユニットを、テープ１０のダイ側乃至は上部表面を下側 に向けて約１５０℃で約０．５時間の間、炉内に配置させる。To accomplish curing, place the unit with the die side or top surface of tape 10 facing down. Place in an oven at about 150° C. for about 0.5 hour.

本発明によれば、好適には例えばフィリップスケミカル社の商標であるライドン （Ｒｙｔｏｎ）等のポリマー物質からなるパッケージフレーム乃至は本体フレー ム４０を、例えばＲＴ−４８（ＲＪＲポリマー社の商標）等のＢ−ステージ接着 剤とすることが可能なエポキシ−接着剤４２によって該硬化させたユニットヘ一 体化させる。該ユニットを、第６図に示した如く、ダイを上に向けたままで、台 乃至はトレイ４４内に挿入する。インサート４６を該ユニットの上に位置させ、 且つ整合台４８を該インサートの上に位置させる。該ユニットを１２０〜１５０ ℃の間の温度に維持する一方、本体フレーム４０を整合台４８内に配置させ、従 って接着剤４２は、全鍍金層１′４及びテープ要素３２と接触する。第６図に示 した如く、ブロック５０によりフレームの上部周辺部へ軽い力を付与する。該圧 力は約１５〜３０秒の間該フレームへ付与される。次いで、取付けたフレームを 有する該ユニットを約１時間の間約１５０℃で硬化させる。According to the invention, it is preferable, for example, to use Rydon, a trademark of Philips Chemical Company. Package frame or body frame made of polymer material such as (Ryton) B-stage adhesive such as RT-48 (trademark of RJR Polymers, Inc.) An epoxy adhesive 42, which can be used as an adhesive, is applied to the cured unit. Embodiment. Place the unit on the stand with the die facing upward, as shown in Figure 6. Alternatively, it is inserted into the tray 44. positioning the insert 46 on the unit; Then, position the alignment table 48 on top of the insert. The unit is 120-150 While maintaining the temperature between The adhesive 42 then contacts the entire plating layer 1'4 and the tape element 32. Shown in Figure 6. As described above, the block 50 applies a light force to the upper periphery of the frame. the pressure Force is applied to the frame for about 15-30 seconds. Next, attach the attached frame to The unit is cured at about 150° C. for about 1 hour.

該本体フレームを有するユニットが硬化した後に５例えばハイツル（Ｈｙｓｏｌ ）ＣＮＢ４０５−１２　（ハイツル社の商標）等の電子グレードエポキシ−物質 ５２を使用して該装置を封止し、一方該ユニットの温度を約５０〜７０℃に維持 する。該エポキシ−を、例えば、回転運動における供給針によって、周辺部乃至 は本体内側角部から初めてダイ区域の中心へ移動して、供給する。該エポキシ− を均一に流動させ、従って実質的に平担な表面が得られ且つ空気の泡が除去され る。該エポキシ−は、第７図に示した如く１本体フレームの上部及び該フレーム 内に閉じ込められている要素を効果的に封止する。次いで、該エポキシー封止物 を、１３０℃乃至１５０℃の間の温度で２〜４時間の間、該ユニットを炉内に配 置させることによって硬化させる。After the unit with the body frame is cured, 5 e.g. Hysol ) Electronic grade epoxy materials such as CNB405-12 (trademark of Heitzl) 52 to seal the device while maintaining the temperature of the unit at approximately 50-70°C. do. The epoxy is applied to the periphery by, for example, a feed needle in a rotating motion. moves from the inner corner of the body first to the center of the die area and supplies it. The epoxy flows uniformly, thus providing a substantially flat surface and eliminating air bubbles. Ru. The epoxy is applied to the upper part of the main body frame and the frame as shown in FIG. effectively sealing the elements trapped within. Then, the epoxy sealant The unit is placed in a furnace for a period of 2 to 4 hours at a temperature between 130°C and 150°C. Allow it to harden.

第８図の平面図において、本発明の新規な半導体装置パッケージ、パターン化し たカプトン層１２に対する本体フレーム４０の関係を示しである。スプロケット 孔５６がワイヤーンド可能なテープ１０に設けてあり、該テープの自動化処理の 助けとなっている。ボンドワイヤー５８は、ボンドワイヤー２６を外側リードフ ィンガーへ結合しており、上述した米国特許に記載される如く、外部接続部乃至 はピン６０への電気的接続を可能としている。In the plan view of FIG. 8, the novel semiconductor device package of the present invention is patterned. The relationship of the main body frame 40 to the Kapton layer 12 is shown. sprocket Holes 56 are provided in the wired tape 10 to facilitate automated processing of the tape. It's been helpful. Bond wire 58 connects bond wire 26 to the outer lead leaf. external connections or allows electrical connection to pin 60.

本発明の別の実施例において、ボンドワイヤー２６の変わりに導電性バンプ５４ を使用して、第９図に示した如く、ダイパッド２０から導電層１４へ導電性経路 を与えている。In another embodiment of the invention, conductive bumps 54 replace bond wires 26. is used to create a conductive path from the die pad 20 to the conductive layer 14, as shown in FIG. is giving.

金、銅、又は半田等から構成することが可能なバンプを形成し且つ当該技術にお いて公知のテープ自動化ボンディング（ＴＡＢ）プロセスによって一体化させる 。該バンプを使用することは、ボンドワイヤーの為に必要とされる空間を減少さ せる。ボンドワイヤーを除去する効果として、本組立体は一層小型のパッケージ を与えており且つ比較的高いリード数とすることを可能としている。何故ならば 、従来技術における如くモールドした包囲体による物理的な空間制限がないから である。Forming bumps that can be made of gold, copper, solder, etc. and using the technology and integrated by a well-known tape automated bonding (TAB) process. . Using the bump reduces the space required for the bond wire. let As a result of eliminating bond wires, the assembly is a smaller package. This makes it possible to obtain a relatively high number of reads. because , there is no physical space limitation due to a molded enclosure as in the prior art. It is.

第１０図を参照すると、本発明の半導体装置パッケージの分解図が、垂直寸法を 持っており、例えば約６０ミリインチとすることが可能である本体フレーム４０ ．及びエポキシ−封止本体５２をそれらがワイヤーボンド可能なテープに関連し て示している。該組立体は、半導体要素を取り巻くモールドしたパッケージを包 含しておらず、また、電気的に導電性の経路の一部である導電性のパターン化し たリードフレームを組み込んではいない。本発明の本体フレーム乃至はパッケー ジフレームは、半導体装置の周りにパッケージをモールドする為の必要性を取り 除いており且つプラスチック乃至は非導電性物質から形成することが可能である 。該本体フレームは、半導体装置の構成要素に所望の保護を与えるエポキシ−封 止本体を収納する為に使用されている。Referring to FIG. 10, an exploded view of the semiconductor device package of the present invention shows the vertical dimensions. The body frame 40 has a diameter of approximately 60 millimeters, for example. ．． and epoxy-sealed bodies 52 as they relate to the wire bondable tape. It shows. The assembly includes a molded package surrounding the semiconductor element. conductive patterning that does not contain or is part of an electrically conductive path. It does not incorporate a lead frame. The main body frame or package of the present invention The frame eliminates the need for molding a package around a semiconductor device. can be made from plastic or non-conductive materials. . The body frame includes an epoxy seal that provides the desired protection for the semiconductor device components. It is used to store the stopper body.

ここにおける説明は単一のユニットの処理に関するものであるが１本プロセスは 複数個のユニットを同時的に処理する為に適用可能であることを理解すべきであ る。また、本発明は、ここに特定した物質及びパラメータに制限されるべきもの ではなく１本発明の範囲内において修正を行うことが可能である。Although the description here relates to the processing of a single unit, one process is It should be understood that it can be applied to process multiple units simultaneously. Ru. Further, the present invention is not limited to the materials and parameters specified herein. However, modifications may be made within the scope of the invention.

本パッケージ構成を実施する為の半導体装置パッケージ及び方法についての新規 な構成について開示した。本新規なプラスチックパッケージは、モールドした包 囲体に対する必要性を取り除いており、著しく高さ及び全体的な面積が減少され ており、且つ改善した電気的性能及び信頼性を実現している。間に導電性膜を有 する導電性層から例えばカプトンである絶縁性区域の剥離の問題は事実上存在し ない。湿気の侵入は効果的に最小とされている。また、ダイ表面腐食の問題もな い。New information regarding semiconductor device packages and methods for implementing this package configuration. The structure was disclosed. This new plastic package is a molded packaging. Eliminates the need for an enclosure, significantly reducing height and overall area. and provides improved electrical performance and reliability. with a conductive film between The problem of delamination of insulating areas, e.g. Kapton, from conductive layers is virtually non-existent. do not have. Moisture ingress is effectively minimized. Also, there is no problem of die surface corrosion. stomach.

トーＡ 国際調査報告To A international search report

Claims (15)

【特許請求の範囲】[Claims] １．パターン化した絶縁層及び導電層を具備しており前記導電層が前記絶縁層へ 一体化されているテープ、前記テープの１表面へ固定した半導体ダイ、前記導電 層へ一体化させた絶縁性要素、前記半導体ダイを前記導電層へ電気的に結合させ る手段、前記導電層へ一体化されており且つ前記半導体ダイ及び前記電気的結合 手段の周りに位置させた本体フレーム、前記フレーム上月つ前記ダイ及び前記電 気的結合手段上で前記フレーム内に配置させた封止本体、を有する半導体装置パ ッケージ。1. A patterned insulating layer and a conductive layer are provided, and the conductive layer is connected to the insulating layer. integrated tape, a semiconductor die fixed to one surface of said tape, said conductive an insulating element integrated into a layer, electrically coupling the semiconductor die to the conductive layer; means integrated into said conductive layer and connected to said semiconductor die and said electrical coupling; a main body frame positioned around the means, the frame upper part, the die and the electric wire; a semiconductor device package having an encapsulation body disposed within the frame over a gaseous coupling means; package. ２．請求の範囲第１項において、前記絶縁層が可撓性物質から形成されている半 導体装置パッケージ。2. Claim 1, wherein the insulating layer is made of a flexible material. Conductor equipment package. ３．請求の範囲第１項において、前記絶縁層がカプトンから形成されている半導 体装置パッケージ。3. The semiconductor device according to claim 1, wherein the insulating layer is made of Kapton. body equipment package. ４．請求の範囲第１項において、前記導電層が金鍍金から形成されている半導体 装置パッケージ。4. The semiconductor according to claim 1, wherein the conductive layer is made of gold plating. equipment package. ５．請求の範囲第１項において、前記結合手段がボンドワイヤーを有する半導体 装置パッケージ。5. Claim 1: A semiconductor device according to claim 1, wherein the coupling means comprises a bond wire. equipment package. ６．請求の範囲第４項において、前記ダイ及び前記ボンドワイヤー上に配設した シリコーンゲルを有する半導体装置パッケージ。6. According to claim 4, disposed on the die and the bond wire. A semiconductor device package containing silicone gel. ７．請求の範囲第１項において、前記ボンドワイヤーへ結合されているボンドリ ードフィンガー、及び外部導電性リードヘの接続の為に前記ボンドリードフィン ガーへ結合されている導電性ピンを有する半導体装置パッケージ。7. Claim 1, wherein the bond wire is coupled to the bond wire. bond lead fins for connection to external conductive leads. A semiconductor device package having conductive pins coupled to a conductive pin. ８．請求の範囲第１項において、前記電気的結合手段が導電性バンプを有してい る半導体装置パッケージ。8. In claim 1, the electrical coupling means has a conductive bump. Semiconductor device package. ９．請求の範囲第７項において．前記絶縁性要素が背面要素であり、且つ前記本 体フレームが前記導電性リードを取り巻く前記背面要素へ接続されている半導体 装置パッケージ。9. In claim 7. the insulating element is a back element and the book a semiconductor body frame connected to the back element surrounding the conductive lead; equipment package. １０．請求の範囲第１項において、前記本体フレームは前記パターン化した絶縁 層の厚さよりも実質的に大きな高さを有する半導体装置パッケージ。10. Claim 1, wherein the body frame includes the patterned insulation. A semiconductor device package having a height substantially greater than the thickness of the layers. １１．絶縁層をエッチングして所定のパターンを画定し且つ前記絶縁層上にパタ ーン化した導電層を付着させることによって絶縁層を具備するパターン化したワ イヤーボンド可能なテープを形成し、前記ワイヤーボンド可能なテープへ半導体 ダイを取り付け、前記ダイと前記導電層の間に電気的接続部を形成し、前記導電 層の背面へ絶縁要素を取り付け、前記ダイ及び電気的接続部上に保護用絶縁被覆 を付着させ、前記ダイと電気的接続部と被覆とを取り巻いて前記導電層及び絶縁 要素の上部表面へ本体フレームを取り付け、前記本体フレームと被覆とダイと電 気的接続部とを絶縁物質で封止する、上記各ステップを有する半導体装置パッケ ージの製造方法。11. etching the insulating layer to define a predetermined pattern and forming a pattern on the insulating layer; patterned wires with an insulating layer by depositing a patterned conductive layer. forming an earbondable tape and applying a semiconductor to the wirebondable tape; attaching a die and forming an electrical connection between the die and the conductive layer; Attach an insulating element to the back side of the layer and provide a protective insulating coating over the die and electrical connections. the conductive layer and the insulating layer surrounding the die, electrical connections, and coating. Attach a body frame to the top surface of the element and connect the body frame, coating, die and electrical A semiconductor device package having each of the above steps, in which the electrical connections are sealed with an insulating material. method of manufacturing the page. １２．請求の範囲第１１項において、前記ダイをダイ取り付けエポキシ−によっ て前記テープへ取り付け且つ１時間以内の間約１５０℃の温度で硬化させる方法 。12. Claim 11, wherein the die is attached with die attach epoxy. A method of attaching the tape to the tape and curing it at a temperature of about 150°C for less than 1 hour. . １３．請求の範囲第１１項において、前記電気的接続部を形成するステップが、 前記ダイパッドと前記パターン化した導電層の導電性リードとの間で熱音波的ボ ンディングワイヤーによって形成される方法。13. Claim 11, wherein the step of forming the electrical connection comprises: A thermosonic bubble is formed between the die pad and the conductive leads of the patterned conductive layer. method formed by winding wire. １４．請求の範囲第１１項において、前記保護用被覆を付着するステップが、前 記ダイ及び電気的接続部上を流動すべくシリコーンゲルを付与し且つ該ゲル被覆 を硬化させることを包含する方法。14. Claim 11, wherein the step of applying the protective coating comprises the step of: applying a silicone gel to flow over the die and electrical connections and coating the gel; A method comprising curing. １５．請求の範囲第１１項において、本体フレーム接着剤を前記導電性リード上 の前記絶縁性要素へ流動させるステップを有する方法。15. Claim 11, wherein a body frame adhesive is applied onto the conductive lead. A method comprising the step of flowing into said insulating element.
JP1500158A 1987-10-30 1988-10-26 Semiconductor device package and method of manufacturing the same Expired - Lifetime JP2664259B2 (en)

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