JP2000031195A - Semiconductor device and production thereof - Google Patents

Semiconductor device and production thereof

Info

Publication number
JP2000031195A
JP2000031195A JP10201471A JP20147198A JP2000031195A JP 2000031195 A JP2000031195 A JP 2000031195A JP 10201471 A JP10201471 A JP 10201471A JP 20147198 A JP20147198 A JP 20147198A JP 2000031195 A JP2000031195 A JP 2000031195A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding wire
insulating resin
semiconductor device
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10201471A
Other languages
Japanese (ja)
Inventor
Tetsuhiro Nakamura
中村　　哲浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP10201471A priority Critical patent/JP2000031195A/en
Publication of JP2000031195A publication Critical patent/JP2000031195A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent contact or breakage of bonding wire at the time of injection and molding of transfer mold by coating a bonding wire connecting a semiconductor chip with a wiring board with insulating resin. SOLUTION: Insulating resin 10 is sprayed, before curing, to cover a bonding wire 8 by means of a spray and then it is cured thus protecting the bonding wire 8 with the insulating resin 10. A low viscosity insulating resin having insulating resistance equal to or higher than that of a transfer mold 9, e.g. epoxy adhesive employing a liquid anhydride, is employed as the insulating resin 10. Subsequently, a semiconductor chip 1 and the wire 8 are sealed with the transfer mold 9. According to the method, short circuit due to contact of bonding wires 8 is eliminated at the time of molding and the bonding wire 8 is protected against breakage because strength thereof is enhanced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は配線基板に半導体チ
ップを実装し、その半導体チップを樹脂封止してなる半
導体装置に関するもので、さらに詳しくはハンダバンプ
付き半導体装置およびその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted on a wiring board and sealing the semiconductor chip with a resin, and more particularly to a semiconductor device with solder bumps and a method of manufacturing the same. .

【０００２】[0002]

【従来の技術】近年、電子回路の高機能化にともなっ
て、多数の電極端子を有する半導体装置が開発されてい
る。その代表的なものとして表面実装形多端子パッケー
ジであるプラスチック・ボールグリッドアレイ（Ｐｌａ
ｓｔｉｃ Ｂａｌｌ ＧｒｉｄＡｒｒａｙ）（以下、Ｐ
ＢＧＡと記載する。）がある。2. Description of the Related Art In recent years, semiconductor devices having a large number of electrode terminals have been developed as electronic circuits become more sophisticated. A typical example is a plastic ball grid array (Pla) which is a surface mount type multi-terminal package.
stick Ball GridArray) (hereinafter P
Described as BGA. ).

【０００３】以下、図面を用いて従来の技術を説明す
る。図５は従来例のＰＢＧＡを示す断面図である。図５
に記載するように上面側に半導体チップ１とワイヤボン
ディングするための接続電極３を備え、下面側にハンダ
バンプ６を設けるためのパット電極４を備え、さらに、
樹脂基板２の中心部分の配線１５とパット電極４を接続
して半導体チップ１の発熱を放散させるためのサーマル
ビアホール１６と、接続電極３とパット電極４を接続す
るためのスルーホール１４と、配線１５を保護するため
のレジスト５とを備える配線基板１８と、配線基板１８
の中心部分にダイボンド剤７で固定される半導体チップ
１と、半導体チップ１上の回路素子を保護するための樹
脂膜１２と、半導体チップ１の電極と配線基板１８の接
続電極３を接続するためのボンディングワイヤ８と、半
導体チップ１とボンディングワイヤ８を封止するための
トランスファモールド９と、配線基板１８のパット電極
４上にハンダバンプ６とを有する構造となっている。[0003] A conventional technique will be described below with reference to the drawings. FIG. 5 is a cross-sectional view showing a conventional PBGA. FIG.
And a connection electrode 3 for wire bonding with the semiconductor chip 1 on the upper surface side and a pad electrode 4 for providing a solder bump 6 on the lower surface side,
A thermal via hole 16 for connecting the wiring 15 in the central portion of the resin substrate 2 to the pad electrode 4 to dissipate heat generated by the semiconductor chip 1; a through hole 14 for connecting the connection electrode 3 to the pad electrode 4; A wiring board provided with a resist for protecting the wiring board;
A semiconductor chip 1 fixed to a central portion of the semiconductor chip 1 with a die bonding agent 7, a resin film 12 for protecting circuit elements on the semiconductor chip 1, and an electrode of the semiconductor chip 1 and a connection electrode 3 of a wiring board 18 , A transfer mold 9 for sealing the semiconductor chip 1 and the bonding wires 8, and a solder bump 6 on the pad electrode 4 of the wiring board 18.

【０００４】つぎにＰＢＧＡの製造方法を説明する。図
６から図９は、従来技術のＰＢＧＡの製造工程を示す断
面図である。Next, a method of manufacturing a PBGA will be described. 6 to 9 are cross-sectional views showing a manufacturing process of a conventional PBGA.

【０００５】図６に記載するように、樹脂基板２は四角
形で板厚が０．２mm程度のガラスエポキシ樹脂からな
り、その上下両面に厚さ１８μｍ程度の銅箔１７が設け
られている。その樹脂基板２には、複数のスルーホール
１４と半導体チップ１との放熱のためのサーマルビアホ
ール１６を切削ドリル加工によって設ける。スルーホー
ル１４とサーマルビアホール１６の壁面を含む基板面を
洗浄した後、樹脂基板２の全表面には、無電解銅メッキ
層が設けられる。その銅メッキ層はスルーホール１４と
サーマルビアホール１６の内部にまで形成される。As shown in FIG. 6, a resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with thermal via holes 16 for heat radiation between the plurality of through holes 14 and the semiconductor chip 1 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 14 and the thermal via hole 16, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed up to the inside of the through hole 14 and the thermal via hole 16.

【０００６】つぎに樹脂基板２の上下両面に、感光性ド
ライフィルムを張り付け、露光現像してエッチングレジ
スト膜を形成させる。その後、エッチング液を樹脂基板
２の上下両面に吹き付け、エッチングレジスト膜のない
露出した銅を除去する。このエッチング後、残ったエッ
チングレジスト膜を除去する。この工程により図７に記
載するように、樹脂基板２の上面側には、ワイヤーボン
ディング用の接続電極３を、下面側にはハンダバンプ６
を形成するためのパット電極４と、両面に配線１５が設
けられる。なお樹脂基板２の中心部分の配線１５とパッ
ト電極４は、サーマルビアホール１６を介して、またレ
ジストの開口部に当たる接続電極３とパット電極４はス
ルーホール１４を介して接続される。Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 7, the connection electrodes 3 for wire bonding are formed on the upper surface of the resin substrate 2 and the solder bumps 6 are formed on the lower surface.
And a wiring 15 on both sides. The wiring 15 and the pad electrode 4 at the center of the resin substrate 2 are connected via a thermal via hole 16, and the connection electrode 3 and the pad electrode 4 corresponding to the opening of the resist are connected via a through hole 14.

【０００７】さらに図８に記載するように樹脂基板２の
両面にレジストをラミネートし、露光現像を行うことに
よりレジスト５を設け、接続電極３とパット電極４に当
たる部分にはレジスト５に開口部を設ける。Further, as shown in FIG. 8, a resist is laminated on both surfaces of the resin substrate 2 and exposed and developed to provide a resist 5, and an opening is formed in the resist 5 at a portion corresponding to the connection electrode 3 and the pad electrode 4. Provide.

【０００８】つぎに樹脂基板２の上下両面の露出してい
る電極の銅メッキ層の表面に、厚さ２から５μｍ程度の
ニッケルメッキ層を設ける。さらに、そのニッケルメッ
キ層の表面に、コバルト等の不純物を含み、ニッケルメ
ッキ層に食いつきやすい、膜厚が０．０５μｍ程度のフ
ラッシュ金メッキ層を設ける。図示していないが、以上
の銅メッキ層とニッケルメッキ層とフラッシュ金メッキ
層までの工程が、下地メッキ層を設ける下地メッキ工程
である。Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps for providing the base plating layer.

【０００９】つぎに下地メッキ層の上に、ボンディング
ワイヤー８と導通性の優れた厚さ０．３μｍから０．７
μｍ程度の金メッキ層を設ける。図示していないが、こ
の工程が金メッキ層を形成する金メッキ工程である。こ
れで配線基板１８が完成される。Next, a thickness of 0.3 μm to 0.7 μm, which is excellent in conductivity with the bonding wire 8, is formed on the base plating layer.
A gold plating layer of about μm is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

【００１０】つぎに図９に記載するように配線基板１８
の上面側の中心部分の上に、ダイボンド剤７を塗布し、
その上に半導体チップ１をのせ、ダイボンド剤７が硬化
するまで乾燥させることで半導体チップ１は配線基板１
８上に固定され、半導体チップ１の電極と、配線基板１
８上の接続電極３をボンディングワイヤ８で電気的に接
続する。つぎに半導体チップ１とボンディングワイヤ８
は、トランスファモールド９で封止する。Next, as shown in FIG.
A die bonding agent 7 is applied on the central portion on the upper surface side of
The semiconductor chip 1 is placed thereon and dried until the die bonding agent 7 is cured, so that the semiconductor chip 1 is
8, the electrodes of the semiconductor chip 1 and the wiring board 1
The connection electrodes 3 on 8 are electrically connected by bonding wires 8. Next, the semiconductor chip 1 and the bonding wires 8
Is sealed with a transfer mold 9.

【００１１】この時、半導体チップ１上には回路素子を
保護するための樹脂膜１２を形成し、ワイヤーボンディ
ングで接続する電極部分は樹脂膜１２を露光現像して開
口させておく。At this time, a resin film 12 for protecting circuit elements is formed on the semiconductor chip 1, and an electrode portion connected by wire bonding is opened by exposing and developing the resin film 12.

【００１２】つぎに配線基板１８の下面側のパット電極
４に、直径０．６ｍｍから０．８ｍｍのハンダボールを
供給し、加熱炉を用いて加熱することによって、ハンダ
バンプ６が設けられる。これでＰＢＧＡが完成する。Next, solder balls having a diameter of 0.6 mm to 0.8 mm are supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, so that the solder bumps 6 are provided. This completes the PBGA.

【００１３】[0013]

【発明が解決しようとする課題】前述した半導体装置に
は以下に記載するような問題点がある。ＰＢＧＡではト
ランスファモールド９を注入および成型する際、その注
入圧力によりボンディングワイヤ８同士が接触したり、
断線したりしていた。The above-described semiconductor device has the following problems. In PBGA, when the transfer mold 9 is injected and molded, the bonding pressure may cause the bonding wires 8 to come into contact with each other.
It was broken.

【００１４】これまではボンディングワイヤ８同士の接
触や断線を防ぐために、トランスファモールド９を注入
するときの圧力を低くしていたが、完全にボンディング
ワイヤ８同士の接触や断線を防ぐことはできず、ＰＢＧ
Ａの歩留まりを低下させていた。Until now, the pressure at the time of injecting the transfer mold 9 has been reduced in order to prevent contact and disconnection between the bonding wires 8, but the contact and disconnection between the bonding wires 8 cannot be completely prevented. , PBG
A had reduced the yield.

【００１５】本発明の目的は、上記課題を解決して、ト
ランスファモールドの注入および成型時に、ボンディン
グワイヤ同士が接触または断線せず、歩留が良く、信頼
性の高い半導体装置およびその製造方法を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor device having a high yield and a high reliability, in which bonding wires do not contact or break during transfer mold injection and molding, and a method of manufacturing the same. To provide.

【００１６】[0016]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明における半導体装置およびその製造方法
は、下記記載の構成と製造方法を採用する。In order to achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention employ the following configurations and manufacturing methods.

【００１７】本発明の半導体装置は、半導体チップの電
極と配線基板の接続電極とを接続するためのボンディン
グワイヤと、半導体チップとボンディングワイヤとを封
止するためのトランスファモールドとを有する半導体装
置において、主にボンディングワイヤとトランスファモ
ールドとの間に絶縁樹脂が形成されていることを特徴と
している。A semiconductor device according to the present invention is a semiconductor device having a bonding wire for connecting an electrode of a semiconductor chip and a connection electrode of a wiring board, and a transfer mold for sealing the semiconductor chip and the bonding wire. An insulating resin is mainly formed between a bonding wire and a transfer mold.

【００１８】本発明の半導体装置の製造方法は、主にボ
ンディングワイヤ表面に絶縁樹脂を散布および硬化させ
る絶縁コーティング工程と、配線基板上に固定された半
導体チップと配線基板上の接続電極とを接続するボンデ
ィングワイヤを樹脂で封止するトランスファモールド工
程を有することを特徴としている。According to the method of manufacturing a semiconductor device of the present invention, an insulating coating step of spraying and curing an insulating resin mainly on the surface of a bonding wire, and connecting a semiconductor chip fixed on a wiring board to a connection electrode on the wiring board. And a transfer molding step of sealing a bonding wire to be sealed with a resin.

【００１９】［作用］本発明では、半導体チップと配線
基板とを接続しているボンディングワイヤを絶縁樹脂で
コーティングしているため、トランスファモールドの注
入、成型時のボンディングワイヤ同士の接触によるショ
ートが発生せず、絶縁樹脂によりボンディングワイヤの
強度が補強されているので断線が発生しない。その結
果、歩留まりが良い半導体装置を得ることができる。[Operation] In the present invention, since the bonding wires connecting the semiconductor chip and the wiring board are coated with an insulating resin, a short circuit occurs due to transfer molding injection and contact between the bonding wires during molding. No disconnection occurs because the strength of the bonding wire is reinforced by the insulating resin. As a result, a semiconductor device with good yield can be obtained.

【００２０】[0020]

【発明の実施の形態】以下、図面を用いて、本発明の実
施の形態を実施例により、本発明の半導体装置およびそ
の製造方法について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings, by way of examples, of a semiconductor device of the present invention and a method of manufacturing the same.

【００２１】[0021]

【実施例】図１は本発明の実施例であるＰＢＧＡを示す
断面図である。図１に記載するように、上面側に半導体
チップ１とワイヤボンディングするための接続電極３を
備え、下面側にハンダバンプ６を設けるためのパット電
極４を備え、さらに、樹脂基板２の中心部分の配線１５
とパット電極４を接続して半導体チップ１の発熱を放散
させるためのサーマルビアホール１６と、接続電極３と
パット電極４を接続するためのスルーホール１４と、配
線１５を保護するためのレジスト５とを備える配線基板
１８と、配線基板１８の中心部分上にダイボンド剤７で
固定される半導体チップ１と、半導体チップ１上の回路
素子を保護するための樹脂膜１２と、半導体チップ１の
電極と配線基板１８の接続電極３を接続するためのボン
ディングワイヤ８と、主にボンディングワイヤを覆う絶
縁樹脂１０と、半導体チップ１とボンディングワイヤ８
を封止するためのトランスファモールド９と、配線基板
１８のパット電極４上にハンダバンプ６とを有する構造
となっている。FIG. 1 is a sectional view showing a PBGA according to an embodiment of the present invention. As shown in FIG. 1, a connection electrode 3 for wire bonding with the semiconductor chip 1 is provided on the upper surface side, a pad electrode 4 for providing solder bumps 6 on the lower surface side, and a central portion of the resin substrate 2 is further provided. Wiring 15
A thermal via hole 16 for connecting the semiconductor chip 1 to the pad electrode 4 to dissipate heat, a through hole 14 for connecting the connection electrode 3 and the pad electrode 4, and a resist 5 for protecting the wiring 15. A semiconductor chip 1 fixed on a central portion of the wiring board 18 with a die bonding agent 7, a resin film 12 for protecting circuit elements on the semiconductor chip 1, and electrodes of the semiconductor chip 1. Bonding wires 8 for connecting the connection electrodes 3 of the wiring board 18, an insulating resin 10 mainly covering the bonding wires, the semiconductor chip 1 and the bonding wires 8
And a solder bump 6 on the pad electrode 4 of the wiring board 18.

【００２２】つぎに実施例における半導体装置の製造方
法を説明する。配線基板は従来の方法で製造できる。Next, a method of manufacturing a semiconductor device according to the embodiment will be described. The wiring board can be manufactured by a conventional method.

【００２３】図２に記載するように、上記に記載した方
法で形成した配線基板１８上面側の中心部分の上に、ダ
イボンド剤７を塗布し、その上に半導体チップ１をの
せ、ダイボンド剤７が硬化するまで乾燥させ、半導体チ
ップ１を配線基板１８上に固定し、半導体チップ１の電
極と、配線基板１８上の接続電極３をボンディングワイ
ヤ８で電気的に接続する。このとき実装する半導体チッ
プ１は図１に記載するように回路素子を保護するための
樹脂膜１２が形成してあり、ワイヤボンディングで接続
する端子部分の樹脂膜１２を露光現像により開口させて
いる。As shown in FIG. 2, a die bonding agent 7 is applied on the central portion on the upper surface side of the wiring board 18 formed by the method described above, and the semiconductor chip 1 is placed thereon, and the die bonding agent 7 The semiconductor chip 1 is fixed on the wiring board 18, and the electrodes of the semiconductor chip 1 and the connection electrodes 3 on the wiring board 18 are electrically connected by the bonding wires 8. At this time, the semiconductor chip 1 to be mounted has a resin film 12 for protecting circuit elements as shown in FIG. 1, and the resin film 12 at a terminal portion connected by wire bonding is opened by exposure and development. .

【００２４】図３に記載するように、硬化する前の絶縁
樹脂１０をスプレーにより主にボンディングワイヤが８
覆われるように散布し、硬化させることでボンディング
ワイヤ８が絶縁樹脂１０により保護される。As shown in FIG. 3, the insulating resin 10 before being cured is mainly sprayed with the bonding wires 8 by spraying.
The bonding wire 8 is protected by the insulating resin 10 by spraying and curing so as to be covered.

【００２５】この時使用する絶縁樹脂１０は、少なくと
もトランスファモールド９と同等かそれ以上の絶縁抵抗
で、スプレー散布し易い低粘度絶縁樹脂として液状酸無
水物を硬化剤としたエポキシ接着剤が好ましい。The insulating resin 10 used at this time is preferably an epoxy adhesive using a liquid acid anhydride as a curing agent as a low-viscosity insulating resin having an insulation resistance at least equal to or higher than that of the transfer mold 9 and easy to spray.

【００２６】粘度が高くスプレー散布が難しい絶縁樹脂
においても、粘度調整のために希釈剤を添加することで
問題なくスプレー散布が行える。Even for an insulating resin having a high viscosity and which is difficult to spray, spraying can be performed without any problem by adding a diluent for adjusting the viscosity.

【００２７】その後、図４に記載するように、半導体チ
ップ１とボンディングワイヤ８は、トランスファモール
ド９で封止する。Thereafter, as shown in FIG. 4, the semiconductor chip 1 and the bonding wires 8 are sealed with a transfer mold 9.

【００２８】つぎに配線基板１８の下面側のパット電極
４に、直径０．６ｍｍから０．８ｍｍのハンダボールを
供給し、加熱炉を用いて加熱することによって、ハンダ
バンプ６を設ける。これで本発明の半導体装置が完成す
る。Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and the solder bump 6 is provided by heating using a heating furnace. Thus, the semiconductor device of the present invention is completed.

【００２９】[0029]

【発明の効果】以上の説明で明らかなように、本発明に
おける半導体装置および製造方法では、トランスファモ
ールド工程前に、主にボンディングワイヤ表面にスプレ
ーにより絶縁樹脂をコーティングしているので、トラン
スファモールド工程時に発生するボンディングワイヤ同
士の接触を防ぐことができる。As is apparent from the above description, in the semiconductor device and the manufacturing method according to the present invention, before the transfer molding step, the surface of the bonding wire is coated with an insulating resin mainly by spraying. The contact between the bonding wires, which sometimes occurs, can be prevented.

【００３０】また、絶縁樹脂をコーティングすることで
ボンディングワイヤの強度を高めることができ、信頼性
の高いボンディングワイヤの接続が可能となる。Further, by coating the insulating resin, the strength of the bonding wire can be increased, and a highly reliable bonding wire can be connected.

【００３１】すなわち、本発明の半導体装置およびその
製造方法を実施することで、歩留まりが良く、信頼性の
高い半導体装置を得ることができる。That is, by implementing the semiconductor device and the method of manufacturing the same according to the present invention, a highly reliable semiconductor device having a high yield can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例における半導体装置を示す断面
図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図２】本発明の実施例における半導体装置を形成する
ための製造方法を示す断面図である。FIG. 2 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to an embodiment of the present invention.

【図３】本発明の実施例における半導体装置を形成する
ための製造方法を示す断面図である。FIG. 3 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to an embodiment of the present invention.

【図４】本発明の実施例における半導体装置を形成する
ための製造方法を示す断面図である。FIG. 4 is a cross-sectional view showing a manufacturing method for forming a semiconductor device according to an embodiment of the present invention.

【図５】従来例における半導体装置を示す断面図であ
る。FIG. 5 is a sectional view showing a semiconductor device in a conventional example.

【図６】従来例における半導体装置を形成するための製
造方法を示す断面図である。FIG. 6 is a sectional view showing a manufacturing method for forming a semiconductor device in a conventional example.

【図７】従来例における半導体装置を形成するための製
造方法を示す断面図である。FIG. 7 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device in a conventional example.

【図８】従来例における半導体装置を形成するための製
造方法を示す断面図である。FIG. 8 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device in a conventional example.

【図９】従来例における半導体装置を形成するための製
造方法を示す断面図である。FIG. 9 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device in a conventional example.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ 樹脂基板 ３ 接続電極 ４ パット電極 ５ レジスト ６ ハンダバンプ ７ ダイボンド剤 ８ ボンディングワイヤ ９ トランスファモールド １０ 絶縁樹脂 １１ スプレーヘッド １２ 樹脂膜 １４ スルーホール １５ 配線 １６ サーマルビアホール １７ 銅箔 １８ 配線基板 Reference Signs List 1 semiconductor chip 2 resin substrate 3 connection electrode 4 pad electrode 5 resist 6 solder bump 7 die bonding agent 8 bonding wire 9 transfer mold 10 insulating resin 11 spray head 12 resin film 14 through hole 15 wiring 16 thermal via hole 17 copper foil 18 wiring substrate

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの電極と配線基板の接続電
極とを接続するためのボンディングワイヤと、半導体チ
ップとボンディングワイヤとを封止するためのトランス
ファモールドとを有する半導体装置において、主にボン
ディングワイヤとトランスファモールドとの間に絶縁樹
脂が形成されていることを特徴とする半導体装置。In a semiconductor device having a bonding wire for connecting an electrode of a semiconductor chip and a connection electrode of a wiring board and a transfer mold for sealing the semiconductor chip and the bonding wire, a bonding wire is mainly used. A semiconductor device, wherein an insulating resin is formed between the semiconductor device and a transfer mold. 【請求項２】 主にボンディングワイヤ表面に絶縁樹脂
を散布および硬化させる絶縁コーティング工程と、配線
基板上に固定された半導体チップと、配線基板上の接続
電極とを接続するボンディングワイヤを樹脂で封止する
トランスファモールド工程を有することを特徴とする半
導体装置の製造方法。2. An insulating coating step for spraying and hardening an insulating resin mainly on the surface of the bonding wire, and sealing the bonding wire for connecting the semiconductor chip fixed on the wiring board and the connection electrode on the wiring board with the resin. A method for manufacturing a semiconductor device, comprising: a transfer molding step of stopping.
JP10201471A 1998-07-16 1998-07-16 Semiconductor device and production thereof Pending JP2000031195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10201471A JP2000031195A (en) 1998-07-16 1998-07-16 Semiconductor device and production thereof

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Application Number Priority Date Filing Date Title
JP10201471A JP2000031195A (en) 1998-07-16 1998-07-16 Semiconductor device and production thereof

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Publication Number Publication Date
JP2000031195A true JP2000031195A (en) 2000-01-28

Family

ID=16441639

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006060065A (en) * 2004-08-20 2006-03-02 Mitsubishi Electric Corp Semiconductor device and method for manufacturing the same
US7202109B1 (en) * 2004-11-17 2007-04-10 National Semiconductor Corporation Insulation and reinforcement of individual bonding wires in integrated circuit packages
EP3163610A1 (en) * 2015-11-02 2017-05-03 MediaTek Inc. Semiconductor package with coated bonding wires
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
WO2021251219A1 (en) * 2020-06-11 2021-12-16 株式会社村田製作所 Module

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006060065A (en) * 2004-08-20 2006-03-02 Mitsubishi Electric Corp Semiconductor device and method for manufacturing the same
US7202109B1 (en) * 2004-11-17 2007-04-10 National Semiconductor Corporation Insulation and reinforcement of individual bonding wires in integrated circuit packages
EP3163610A1 (en) * 2015-11-02 2017-05-03 MediaTek Inc. Semiconductor package with coated bonding wires
CN106941098A (en) * 2015-11-02 2017-07-11 联发科技股份有限公司 Semiconductor packages and its manufacture method
US10037936B2 (en) 2015-11-02 2018-07-31 Mediatek Inc. Semiconductor package with coated bonding wires and fabrication method thereof
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
US11257780B2 (en) 2015-11-02 2022-02-22 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
WO2021251219A1 (en) * 2020-06-11 2021-12-16 株式会社村田製作所 Module

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