JP3617072B2 - Chip carrier - Google Patents
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- JP3617072B2 JP3617072B2 JP6715494A JP6715494A JP3617072B2 JP 3617072 B2 JP3617072 B2 JP 3617072B2 JP 6715494 A JP6715494 A JP 6715494A JP 6715494 A JP6715494 A JP 6715494A JP 3617072 B2 JP3617072 B2 JP 3617072B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】
【産業上の利用分野】
本発明は、半導体集積回路素子（以下、チップと称する）を搭載し、外部回路に接続するために用いるチップキャリアに関する。
詳しくは、ボール・グリッド・アレイ型（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ …以下、ＢＧＡと称する）の半導体パッケージ向けのチップキャリアに関する。
【０００２】
【従来の技術】
従来、チップをプリント配線板などの外部回路に接続するための代表的な装置として、クワッド・フラット・パッケージ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ …以下、ＱＦＰと称する）がある。
【０００３】
ＱＦＰは、パッケージの内部でチップとリードフレームのインナー・リードとをワイヤボンディング等により接続し、チップを含む領域を樹脂にてモールドしてパッケージとし、その四辺からリードフレームのアウター・リードを引き出し、前記リードをガルウィング状に形成し、外部回路と接続する方式の半導体パッケージであり、最も広く普及している。（図３参照）
【０００４】
昨今、新規な上記の接続用装置として、ＢＧＡ型の半導体パッケージが普及しつつある。
【０００５】
前記パッケージは、特開昭５９−１７２７５８号公報に例示されるような、外部回路に直接的表面取付けができるリードレス・チップキャリヤに関するものであり、
▲１▼複数のワイヤボンドパッド５１によって取り囲まれたダイボンディング部位を有する上方のボンディング面。（図５（ａ） 参照）
▲２▼前記上方のボンディング面に対向し、内側のはんだパッド５２配列を含む下方のはんだ付け面。（図５（ｂ） 参照）
▲３▼前記はんだパッド５２の一部を前記ワイヤボンドパッド５１の一部に電気的に結合する手段５３。（図５（ｃ） 参照）
▲４▼前記内側のはんだパッド５２を取り囲んでいる前記下方のはんだ付け面の絶縁性周辺部位５４。（図５（ｃ） 参照）
を具えることを特徴とする。（図５参照）
【０００６】
また、これに似た形態の半導体パッケージとして、上記はんだパッドの代わりに金属ピンを立てた構造で、プリント配線板に予め形成したスルーホールに挿入してはんだ付けすることで固定する、いわゆるピン・グリッド・アレイ型（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ…以下、ＰＧＡと称する）の半導体パッケージがある。（図４参照）
【０００７】
なお、上記参照図面では、チップの端子の数およびリードの本数が９個についての場合で説明を簡略化している。
【０００８】
ＱＦＰに対してのＢＧＡの利点は、特に実装密度の向上にあり、ＱＦＰを取り付けるのに必要な外部回路基板の実質的面積よりも、ＢＧＡを取り付けるのに必要な前記面積が大幅に小さくなる点にある。
【０００９】
一般的なＢＧＡ型の半導体パッケージは、プリント配線板用の銅張積層板（エポキシ樹脂等からなる絶縁性基材の両面または片面に、銅箔を貼り合わせたもの）をベース材料（上記▲３▼）とし、これをフォトエッチング法等の方法で加工して、チップ搭載部と配線部（上記▲１▼と▲２▼）を形成している。
【００１０】
【発明が解決しようとする課題】
上記のようにベース材料として銅張積層板を使用したＢＧＡ型の半導体装置では、広く一般的に使われているＱＦＰ型の半導体パッケージ用の製造設備がそのまま使用できないため、ＢＧＡ向けの製造設備が新たに必要となる。
【００１１】
また、ＢＧＡ型の半導体パッケージをプリント配線板（外部回路）に接続する際、２３０〜２６０℃程度に加熱してはんだボール（パッド）を溶融させる必要があり、この時の熱で半導体パッケージとプリント配線板（外部回路）の両方に反りが発生することにより、ボール状に形成した半導体装置上の端子（はんだパッド）とプリント配線板上に形成したパッドとの間に隙間が発生してしまうため、端子数がおよそ３００ピンを越えるチップを搭載する場合には、全てのピンを安定して接続することが難しい。
【００１２】
さらに、発熱量の大きいチップを使用する場合も、上記ベース材料として樹脂を基本とする従来のＢＧＡでは、放熱性・接続信頼性の点で満足のいくものではない。
【００１３】
そのため、端子数がおよそ３００ピン以上のものや、発熱量の大きいチップを使用する場合には、接続信頼性を向上させるために、ＰＧＡ型の半導体パッケージに加工してチップを搭載することになるので、半導体装置自体が高価になってしまうという問題がある。
【００１４】
本発明は上記問題を考慮して、従来から広く使用されているＱＦＰ型の半導体装置の製造設備をそのまま使用でき、ＰＧＡ型の半導体装置より安価で、従来のＢＧＡ型の半導体装置より放熱性・接続信頼性の高い、新規なＢＧＡ型の半導体装置を達成するようなチップキャリアを提供することを目的とする。
【００１５】
【課題を解決するための手段】
請求項１に記載の本発明は、半導体集積回路の搭載用金属板の表面に、前記搭載部を除く形状に設けられた絶縁性シートを介して、所定の導体パターンよりなるリードが配置されてなるチップキャリアであって、前記リードは、金属材料をエッチング成形したものを、前記絶縁性シートに積層したものであり、前記リードが、半導体集積回路素子と接続される多数の始端より略放射状に外側に延びており、それらの末端が前記絶縁性基材の表面に略マトリクス状に配置されており、個々の前記末端には、外部回路との接続用の球状パッドが設けられていることを特徴とする。
【００１６】
上記構成（絶縁性シートを介して所定の導体パターンよりなるリードが配置された構成）とする理由は、前記リードの一例を示す平面図（図２）からわかるように、各リードの末端が略マトリクス状に配置されており、各リードが独立しているため、単層の金属板のみを用いては成形できないので、絶縁性シートによって各リードを支持する必要があるためである。
【００１７】
さらに、請求項１に記載の発明は、前記リードの末端部のみが露出するように、略マトリクス状に開口が存在する絶縁性シートが、前記リードの表面に積層され、前記開口部に外部回路との接続用の球状パッドが設けられた構成であることを特徴とする。
【００１８】
請求項２に記載の発明は、前記接続用の球状パッドとして、錫，錫−鉛合金，金とこれらの金属を主成分とする合金のうち、２種以上の金属を積層した構成のものを用い、前記末端部側に金を含む合金を配置し、外側に錫または錫−鉛合金を配置したことを特徴とする。
【００１９】
請求項３に記載の発明は、前記導体パターンの末端部が、対応する箇所の前記絶縁性基材と１０μｍ以上の間隔を隔てていることを特徴とする。
【００２０】
【作用】
ＱＦＰと同様に、４連または５連のフレーム状（帯状のフレーム材料に、モジュールが４つまたは５つある構成）として、この状態でチップの搭載からパッケージングまでが行なえるようになり、また、従来のＢＧＡと異なり、配線パターンであるリード自体が剛性を有する厚さであり、リードが主体な構成であるため、既存のＱＦＰの製造設備がそのまま適用でき、ＢＧＡ型の半導体パッケージが製造できる。
【００２１】
また、導体パターンからなるリードを絶縁性シートを介して形成したことにより、導体パターンの電気特性（インピーダンス・インダクタンス等）を改善することも可能となる。
【００２２】
また、チップ搭載部を金属材料にて成形することにより、チップからの発熱を直接金属部で放散できるようになり、放熱特性も向上する。
【００２３】
さらに、接続用パッドとしてボール状のはんだパッドを用いると、外部回路との接続が確実となるが、加熱・加圧によるボールの溶融に起因する隣合う配線との短絡の問題が、前記パッドの層構成を改善したことと、前記パッドの形成部に対応した開口を有する絶縁性シートを介したことで改善される。
【００２４】
加えて、リードの末端部が対応する箇所の絶縁性基材と１０μｍ以上の間隔を隔てていることにより、外部回路との接続の際の反り等に起因する接続部の凹凸を吸収することが可能になる。
【００２５】
【実施例】
（１） リード材料の前処理
ニッケル約４２％を含有する厚さ１５０μｍの鉄−ニッケル合金の条（ＹＥＦ−４２（商品名）；日立金属（株）製）をリード材料とし、前記材料を７０℃に加熱したアルカリ脱脂液（エークスリーン（商品名）；奥野製薬（株）製を水に溶解させたもの）に１０分間浸漬し、約５０℃の湯で攪拌しながら２分間洗浄し、さらに約２０℃の水に２分間浸漬し、水を交換して再び２分間浸漬した。
【００２６】
次に、リード材料を約２０℃の５％塩酸に３０〜６０秒間浸漬し、その後、約２０℃の水に１分間浸漬し、別の槽に溜めておいた約２０℃の純水に１分間浸漬して取り出した後、乾燥空気を吹きつけて表面の水滴を完全に除去した。
【００２７】
前記材料を、予め８０℃に加熱しておいたオーブンに入れ、１０分後に取り出し、すぐにデシケータに入れて温度が３０℃以下になるまでそのまま放置した。
【００２８】
（２） リードの成形（レジスト・パターンの形成）
前記材料を、約６０分後、デシケータから取り出し、塗布・乾燥後の膜厚が約１０μｍになるように、ネガ型液状レジスト（ＰＭＥＲ Ｎ−ＨＣ４０（商品名）；東京応化（株）製）をディップコータで表面に塗布した。約７０℃のオーブンに３０分間入れて、表面に塗布したレジストがベトつかなくなるまで乾燥させた。
【００２９】
次いで、前記材料にパターンマスクを重ね合わせ、両面露光機（ＨＭＷ５３２Ｄ（商品名）；オーク（株）製）にセットして、紫外線を約１００ｍＪ／ｃｍ２照射して、被照射部のレジストを現像液に不溶な状態に変化させた。
【００３０】
レジスト・パターンは、成形後のリード・パターンであり、チップと接続される多数の始端より略放射状に外側に延びており、それらの末端が略マトリクス状に配置されており、必要に応じて、前記末端部が、他の導体部より幅が広く、円形または多角形もしくはこれに類似する形状となるようにパターニングする。
【００３１】
さらに、５％のトリエタノールアミン溶液に浸漬し、１０秒に１〜２回の割合で揺動しながら２分後に取り出し、現像液が表面に残らなくなるまで水で洗浄した。さらに、純水で洗浄し、約４０℃の乾燥空気を吹きつけて水分を完全に飛ばし、表面を乾燥させた。その後、前記材料を、予め１１０℃に加熱しておいたオーブンに入れ、エッチング液で剥離したり溶解したりしないようにレジストを十分に硬化させた。
【００３２】
（３） リードの成形（金属材料のエッチング成形）
前記材料に、５０℃の塩化第二鉄をスプレーで吹きつけ、レジストで覆われていない部分の鉄−ニッケル合金を腐食させて除去した。材料表面に付着した塩化第二鉄液を良く落としてから、約３０℃の水をスプレーで吹きつけて塩化第二鉄液を完全に洗い流した。次いで、乾燥空気を吹きつけて表面に付着した水分を飛ばした後、５０℃に加熱した水酸化ナトリウム５％溶液に約２分間浸漬し、レジストを膨潤させて除去し、３０℃の水で良く洗浄して乾燥させた。
以上、（１） 〜（３） の工程により、例えば図２に示すようなリード部材２０を得た。
【００３３】
（４） チップ搭載用金属板の成形
上記とは別に、厚さ約０．５ｍｍの銅板の中央部の縦横約２０ｍｍを除いた部分を絞り加工して、深さ約０．７ｍｍの窪みを形成し、チップ搭載部とした。
【００３４】
次に、窪み部分の外側部に、絶縁性シートとなる厚さ６０μｍのエポキシ系接着シート（ＹＥＦ−０４０（商品名）；三菱油化（株）製）を重ね、約１００℃の熱板で２〜５ｋｇ／ｃｍ２ の圧力を約１０秒間加えて、チップ搭載部と絶縁性基材とを貼り合せ、チップ搭載用金属板１１を得た。（図１参照）
【００３５】
この際、エポキシ系接着シート（絶縁性基材）を任意のパターン状とすることによって、後工程において、リード部材と積層した場合に、リード・パターンの末端部の接続用パッド部分がチップ搭載用金属板と離間（シートの厚さ分）した構成とすることができる。
【００３６】
（５） チップキャリアの製造（以下、図１参照）
チップ搭載用金属板１１に設けられた絶縁性基材（接着シート）１２側の面に、リード部材２０を位置合わせして重ね、そのまま２〜５ｋｇ／ｃｍ２ の圧力を加えながら、１８０℃に加熱し、両者を貼り合わせた。約３０分後、冷却して取り出した。
【００３７】
リード部材２０とチップ搭載用金属板１１の導体部とを電気的に接続させることが必要な箇所には、予め接続用の穴３０を形成しておいた。両者の貼り合わせ後、この穴３０に銅粉を含む導電ペースト（ＮＦ２０００（商品名）；タツタ電線（株）製）を充填し、１５０℃で３０分間加熱してペーストを硬化させた。
【００３８】
（６） 接続用パッドの形成
次に、リード部材２０のリード末端部以外を覆うための絶縁性樹脂（プロビマー５２（商品名）；チバガイギー製）を、リード部材２０のある面に塗布し、そのまま室温で乾燥させた。
【００３９】
次いで、８０℃で約１０分間加熱し、樹脂中に含まれる溶剤を揮発させ、表面に塗布したレジストがベトつかなくなるまで乾燥させた。
【００４０】
その後、開口部分がリード部材２０のリード末端部に対応するパターンマスクを重ね合わせ、両面露光機（ＨＭＷ５３２Ｄ（商品名）；オーク（株）製）にセットして、紫外線を約７０００ｍＪ／ｃｍ２ 照射して、被照射部の樹脂を現像液に不溶な状態に変化させた。次いで、現像処理によって、紫外線の当たらなかった部分の樹脂を溶解させて除去した。１４０℃で３０分間加熱して樹脂を完全に硬化させた。
【００４１】
樹脂を除去した部分にディスペンサで、はんだクリーム（ＳＱ−１０３２０ＳＨＺ（商品名）；（株）タムラ製作所製）を塗布し、ＩＲリフロー装置（ＲＦ−３３０（商品名）；日本パルス技研（株）製）で２３０℃、約１分間加熱してはんだクリームを溶融させた。このまま冷却し洗浄することによって、球状のはんだパッド４０をリード部材２０の導体パターンの外部端子上に形成した。
【００４２】
この際、はんだパッドを複層構成とすることも任意である。例えば、錫，錫−鉛合金，金とこれらの金属を主成分とする合金のうち、２種以上の金属を積層した構成とし、前記末端部側に金を含む合金のような高融点の金属を配置し、外側に錫または錫−鉛合金を配置することで、外側のはんだは接続に寄与し、内側のはんだは接続の際の加熱・加圧によってもつぶれない剛性を有するものであり、隣り合うリードとの短絡が防止される。
【００４３】
（７） チップの搭載
次に、チップ搭載用金属板１１の中央部に形成した窪み（チップ搭載箇所）に銀ペースト（ＣＲＮ−１０２２（商品名）；住友ベークライト（株）製）を塗布し、チップを乗せ、２００℃で３０分間加熱することにより、銀ペーストを硬化してチップを固定させた。これらの一連の操作はダイボンディング装置で行った。
【００４４】
（８） 半導体パッケージの製造
チップ上の電極とリード部材２０との電気的な接続を、ワイヤーボンダを用いて直径３０μｍの金線で行った。また、チップ上のグランド電極は、チップ搭載用金属板１１の導体部と接続させた。
【００４５】
なお、電気的に接続できる方法であれば、ワイヤーボンディングによる方法に限定する必要はなく、導電ペーストによる方法やバンプを使用する方式でも良い。
【００４６】
金線と半導体素子を保護するため、封止用樹脂を任意の方法（例えば、ディスペンサやトランスファ・モールド）で塗布し、１８０℃で３０分間加熱して樹脂を硬化させ、その後、フレームとの接続部を金型で切断して半導体パッケージを得た。
【００４７】
【発明の効果】
ＱＦＰ型の半導体装置の製造設備をそのまま使用でき、ＰＧＡ型の半導体装置より安価で、既存のＢＧＡ型の半導体装置より放熱性・接続信頼性の高い、新規なＢＧＡ型の半導体装置を達成するようなチップキャリアが提供された。
【図面の簡単な説明】
【図１】本発明のチップキャリアの断面説明図。
【図２】本発明のチップキャリアを形成するリード部材の一例を示す平面図。
【図３】従来のチップキャリア（ＱＦＰ）の説明図。
【図４】従来のチップキャリア（ＰＧＡ）の説明図。
【図５】従来のＢＧＡ方式のチップキャリアのの説明図。
【符号の説明】
１０…チップキャリア
１１…チップ搭載用金属板
１２…絶縁性基材
２０…リード部材
４０…はんだパッド
５０…ＢＧＡ型の半導体パッケージ[0001]
[Industrial application fields]
The present invention relates to a chip carrier on which a semiconductor integrated circuit element (hereinafter referred to as a chip) is mounted and used for connection to an external circuit.
Specifically, the present invention relates to a chip carrier for a semiconductor package of a ball grid array type (Ball Grid Array, hereinafter referred to as BGA).
[0002]
[Prior art]
Conventionally, as a typical apparatus for connecting a chip to an external circuit such as a printed wiring board, there is a quad flat package (hereinafter referred to as QFP).
[0003]
QFP connects the chip and the inner lead of the lead frame by wire bonding or the like inside the package, molds the region including the chip with resin, and draws the outer lead of the lead frame from its four sides. This is a semiconductor package in which the leads are formed in a gull wing shape and connected to an external circuit, and is most widely used. (See Figure 3)
[0004]
In recent years, BGA type semiconductor packages have become widespread as new connection devices.
[0005]
The package relates to a leadless chip carrier that can be directly surface-mounted to an external circuit, as exemplified in JP-A-59-172758,
(1) An upper bonding surface having a die bonding portion surrounded by a plurality of
(2) A lower soldering surface facing the upper bonding surface and including an
(3) A
(4) An insulating
It is characterized by comprising. (See Figure 5)
[0006]
Moreover, as a semiconductor package of a similar form, a structure in which metal pins are erected in place of the solder pads, and is fixed by inserting into a through hole formed in advance on a printed wiring board and soldering. There is a grid array type (Pin Grid Array, hereinafter referred to as PGA) semiconductor package. (See Figure 4)
[0007]
In the reference drawings, the description is simplified in the case where the number of terminals of the chip and the number of leads are nine.
[0008]
The advantage of the BGA over the QFP is that the mounting density is particularly improved, and the area required for mounting the BGA is significantly smaller than the substantial area of the external circuit board required for mounting the QFP. It is in.
[0009]
A general BGA type semiconductor package is made of a copper-clad laminate for printed wiring boards (a copper foil bonded to both sides or one side of an insulating substrate made of epoxy resin) as a base material ((3) above) The chip mounting portion and the wiring portion (above (1) and (2)) are formed by processing this by a method such as a photo etching method.
[0010]
[Problems to be solved by the invention]
In the BGA type semiconductor device using the copper clad laminate as the base material as described above, the manufacturing equipment for the QFP type semiconductor package which is widely used generally cannot be used as it is. Newly needed.
[0011]
In addition, when connecting a BGA type semiconductor package to a printed wiring board (external circuit), it is necessary to heat the solder balls (pads) by heating to about 230 to 260 ° C. Since warpage occurs in both the wiring board (external circuit), a gap is generated between the terminal (solder pad) on the ball-shaped semiconductor device and the pad formed on the printed wiring board. When a chip having more than about 300 pins is mounted, it is difficult to stably connect all the pins.
[0012]
Furthermore, even when a chip with a large amount of heat generation is used, the conventional BGA based on resin as the base material is not satisfactory in terms of heat dissipation and connection reliability.
[0013]
Therefore, when using a terminal with about 300 pins or more or a chip with a large amount of heat generation, the chip is mounted after being processed into a PGA type semiconductor package in order to improve connection reliability. Therefore, there is a problem that the semiconductor device itself becomes expensive.
[0014]
In view of the above problems, the present invention can use the manufacturing equipment of the QFP type semiconductor device that has been widely used in the past as it is, is cheaper than the PGA type semiconductor device, and has better heat dissipation than the conventional BGA type semiconductor device. An object of the present invention is to provide a chip carrier that achieves a novel BGA type semiconductor device with high connection reliability.
[0015]
[Means for Solving the Problems]
According to the first aspect of the present invention, a lead made of a predetermined conductor pattern is disposed on the surface of a mounting metal plate of a semiconductor integrated circuit via an insulating sheet provided in a shape excluding the mounting portion. In the chip carrier, the lead is formed by etching a metal material and laminated on the insulating sheet, and the lead is substantially radial from a plurality of start ends connected to the semiconductor integrated circuit element. The outer ends of the insulating base material are arranged in a substantially matrix form on the surface of the insulating base, and each of the ends is provided with a spherical pad for connection to an external circuit. Features.
[0016]
The reason for the above configuration (configuration in which leads made of a predetermined conductor pattern are arranged via an insulating sheet) is that the end of each lead is substantially as can be seen from the plan view (FIG. 2) showing an example of the lead This is because each lead is independent because it is arranged in a matrix and cannot be formed using only a single-layer metal plate, and therefore it is necessary to support each lead with an insulating sheet.
[0017]
Furthermore, in the invention described in claim 1 , an insulating sheet having an opening in a substantially matrix shape is laminated on the surface of the lead so that only an end portion of the lead is exposed, and an external circuit is formed in the opening. It is the structure provided with the spherical pad for connection with.
[0018]
The invention according to claim 2 has a structure in which two or more kinds of metals are laminated as tin, tin-lead alloy, gold and an alloy mainly composed of these metals as the spherical pad for connection. It is characterized in that an alloy containing gold is arranged on the end side and tin or a tin-lead alloy is arranged on the outside.
[0019]
The invention according to
[0020]
[Action]
As with QFP, it is possible to perform from chip mounting to packaging in this state as a 4- or 5-frame structure (a configuration in which 4 or 5 modules are provided in a belt-shaped frame material). Unlike the conventional BGA, the lead itself, which is a wiring pattern, has a rigid thickness, and the lead is the main component. Therefore, the existing QFP manufacturing equipment can be applied as it is, and a BGA type semiconductor package can be manufactured. .
[0021]
Further, by forming the lead made of the conductor pattern via the insulating sheet, it is possible to improve the electrical characteristics (impedance, inductance, etc.) of the conductor pattern.
[0022]
Further, by forming the chip mounting portion with a metal material, the heat generated from the chip can be directly dissipated in the metal portion, and the heat dissipation characteristics are improved.
[0023]
Furthermore, when a ball-shaped solder pad is used as the connection pad, the connection with the external circuit is ensured, but the problem of short circuit with the adjacent wiring due to the melting of the ball by heating and pressurization is It is improved by improving the layer structure and through an insulating sheet having an opening corresponding to the pad forming portion.
[0024]
In addition, the unevenness of the connection part due to warpage or the like when connecting to an external circuit can be absorbed by the distance of 10 μm or more from the insulating base material at the corresponding end part of the lead. It becomes possible.
[0025]
【Example】
(1) Lead material pretreatment Nickel-iron alloy strip (YEF-42 (trade name); manufactured by Hitachi Metals Co., Ltd.) having a thickness of 150 μm containing about 42% nickel is used as the lead material. Immerse in an alkaline degreasing solution heated to ℃ (Axleen (trade name); Okuno Seiyaku Co., Ltd. product dissolved in water) for 10 minutes, wash with hot water at about 50 ℃ for 2 minutes, and further about It was immersed in water at 20 ° C. for 2 minutes, the water was changed, and it was immersed again for 2 minutes.
[0026]
Next, the lead material is dipped in 5% hydrochloric acid at about 20 ° C. for 30 to 60 seconds, then dipped in water at about 20 ° C. for 1 minute, and then added to about 20 ° C. pure water stored in another tank. After taking out by dipping for a minute, water droplets on the surface were completely removed by blowing dry air.
[0027]
The material was placed in an oven preheated to 80 ° C., removed 10 minutes later, immediately placed in a desiccator and allowed to stand until the temperature reached 30 ° C. or lower.
[0028]
(2) Lead molding (resist pattern formation)
The material is removed from the desiccator after about 60 minutes, and a negative liquid resist (PMER N-HC40 (trade name); manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used so that the film thickness after application and drying becomes about 10 μm. It was applied to the surface with a dip coater. It was placed in an oven at about 70 ° C. for 30 minutes and dried until the resist applied on the surface was not sticky.
[0029]
Next, a pattern mask is overlaid on the material, set on a double-sided exposure machine (HMW532D (trade name); manufactured by Oak Co., Ltd.), and irradiated with about 100 mJ / cm 2 of ultraviolet light to develop the resist in the irradiated area. The solution was changed to an insoluble state.
[0030]
The resist pattern is a lead pattern after molding, extends radially outward from a large number of starting ends connected to the chip, and the ends thereof are arranged in a substantially matrix shape. The terminal portion is patterned so as to be wider than the other conductor portions and to have a circular shape, a polygonal shape, or a similar shape.
[0031]
Further, it was immersed in a 5% triethanolamine solution, taken out after 2 minutes while shaking at a rate of 1 to 2 times in 10 seconds, and washed with water until no developer remained on the surface. Further, the surface was washed with pure water, and dry air at about 40 ° C. was blown to completely blow off moisture, thereby drying the surface. Thereafter, the material was put in an oven preheated to 110 ° C., and the resist was sufficiently cured so as not to be peeled off or dissolved by the etching solution.
[0032]
(3) Lead molding (etching molding of metal material)
The material was sprayed with 50 ° C. ferric chloride to remove the portion of the iron-nickel alloy that was not covered with the resist by corrosion. After the ferric chloride solution adhering to the surface of the material was well removed, the ferric chloride solution was completely washed away by spraying water at about 30 ° C. with a spray. Next, after blowing dry air to remove the water adhering to the surface, the resist is swelled and removed by immersing in a 5% sodium hydroxide solution heated to 50 ° C. for about 2 minutes. Washed and dried.
As described above, for example, the
[0033]
(4) Molding of chip-mounted metal plate Separately from the above, a portion of the central portion of a copper plate having a thickness of about 0.5 mm, except for about 20 mm in length and width, is drawn to form a recess having a depth of about 0.7 mm. And it was set as the chip mounting part.
[0034]
Next, an epoxy adhesive sheet (YEF-040 (trade name); manufactured by Mitsubishi Yuka Co., Ltd.) having a thickness of 60 μm, which becomes an insulating sheet, is stacked on the outer side of the recessed portion, and a hot plate at about 100 ° C. A chip mounting portion and an insulating substrate were bonded together by applying a pressure of 2 to 5 kg / cm 2 for about 10 seconds to obtain a chip mounting metal plate 11. (See Figure 1)
[0035]
At this time, by forming the epoxy adhesive sheet (insulating base material) in an arbitrary pattern, the connection pad portion at the end of the lead pattern is for chip mounting when laminated with the lead member in the subsequent process. A structure separated from the metal plate (by the thickness of the sheet) can be adopted.
[0036]
(5) Manufacture of chip carriers (refer to Fig. 1 below)
The
[0037]
A
[0038]
(6) Formation of connection pad Next, an insulating resin (Provimer 52 (trade name); manufactured by Ciba Geigy) for covering the
[0039]
Subsequently, it heated at 80 degreeC for about 10 minutes, the solvent contained in resin was volatilized, and it was dried until the resist apply | coated to the surface was no longer sticky.
[0040]
Thereafter, a pattern mask whose opening corresponds to the lead end of the
[0041]
Solder cream (SQ-10320SHZ (trade name); manufactured by Tamura Seisakusho Co., Ltd.) is applied to the portion from which the resin has been removed with a dispenser, and an IR reflow device (RF-330 (trade name); manufactured by Nippon Pulse Giken Co., Ltd.) ) At 230 ° C. for about 1 minute to melt the solder cream. The
[0042]
At this time, it is also optional to make the solder pads have a multilayer structure. For example, a high melting point metal such as tin, tin-lead alloy, gold and an alloy containing these metals as a main component, in which two or more kinds of metals are laminated, and an alloy containing gold on the end portion side. , And by placing tin or tin-lead alloy on the outside, the outer solder contributes to the connection, and the inner solder has rigidity that is not crushed by heating and pressing during connection, Short circuit with adjacent leads is prevented.
[0043]
(7) Chip mounting Next, a silver paste (CRN-1022 (trade name); manufactured by Sumitomo Bakelite Co., Ltd.) is applied to the recess (chip mounting location) formed in the central portion of the chip mounting metal plate 11. The chip was placed and heated at 200 ° C. for 30 minutes to cure the silver paste and fix the chip. These series of operations were performed with a die bonding apparatus.
[0044]
(8) The electrical connection between the electrode on the manufacturing chip of the semiconductor package and the
[0045]
Note that the method is not limited to the method using wire bonding as long as it can be electrically connected, and a method using a conductive paste or a method using bumps may be used.
[0046]
In order to protect the gold wire and the semiconductor element, a sealing resin is applied by any method (for example, dispenser or transfer mold), heated at 180 ° C. for 30 minutes to cure the resin, and then connected to the frame. The part was cut with a mold to obtain a semiconductor package.
[0047]
【The invention's effect】
To achieve a new BGA type semiconductor device that can use the manufacturing facility of the QFP type semiconductor device as it is, is cheaper than the PGA type semiconductor device, and has higher heat dissipation and connection reliability than the existing BGA type semiconductor device. Chip carriers were provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional explanatory view of a chip carrier of the present invention.
FIG. 2 is a plan view showing an example of a lead member forming the chip carrier of the present invention.
FIG. 3 is an explanatory diagram of a conventional chip carrier (QFP).
FIG. 4 is an explanatory diagram of a conventional chip carrier (PGA).
FIG. 5 is an explanatory diagram of a conventional BGA type chip carrier.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Chip carrier 11 ...
Claims (3)
前記リードは、金属材料をエッチング成形したものを、前記絶縁性シートに積層したものであり、
前記リードが、半導体集積回路素子と接続される多数の始端より略放射状に外側に延びており、それらの末端が前記絶縁性基材の表面に略マトリクス状に配置されており、個々の前記末端には、外部回路との接続用の球状パッドが設けられており、
前記リードの末端部のみが露出するように、略マトリクス状に開口が存在する前記絶縁性シートが、前記リードの表面に積層され、前記開口部に外部回路との前記球状パッドが設けられた構成であることを特徴とするチップキャリア。 A chip carrier in which leads made of a predetermined conductor pattern are arranged on the surface of a mounting metal plate of a semiconductor integrated circuit via an insulating sheet provided in a shape excluding the mounting portion,
The lead is obtained by laminating a metal material etched on the insulating sheet,
The leads extend radially outward from a large number of starting ends connected to the semiconductor integrated circuit element, and the ends thereof are arranged in a substantially matrix on the surface of the insulating base, Is provided with a spherical pad for connection to an external circuit ,
A configuration in which the insulating sheet having an opening in a substantially matrix shape is laminated on the surface of the lead so that only the end portion of the lead is exposed, and the spherical pad with an external circuit is provided in the opening. A chip carrier characterized by being.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715494A JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715494A JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07283336A JPH07283336A (en) | 1995-10-27 |
| JP3617072B2 true JP3617072B2 (en) | 2005-02-02 |
Family
ID=13336708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6715494A Expired - Fee Related JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3617072B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3031323B2 (en) * | 1997-12-26 | 2000-04-10 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH11284092A (en) * | 1998-03-27 | 1999-10-15 | Mitsui High Tec Inc | Semiconductor device |
| EP1079433A3 (en) * | 1999-08-27 | 2004-03-03 | Texas Instruments Incorporated | Ball grid array package having two ground levels |
| JP3269815B2 (en) | 1999-12-13 | 2002-04-02 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| US6882042B2 (en) * | 2000-12-01 | 2005-04-19 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
| US6879039B2 (en) | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
| US6876553B2 (en) | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
| US7239024B2 (en) * | 2003-04-04 | 2007-07-03 | Thomas Joel Massingill | Semiconductor package with recess for die |
| CN101584044B (en) * | 2006-12-12 | 2014-12-17 | 艾格瑞系统有限公司 | An integrated circuit package and a method for dissipating heat in an integrated circuit package |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6286848A (en) * | 1985-10-14 | 1987-04-21 | Matsushita Electric Works Ltd | Chip carrier |
| JP2602834B2 (en) * | 1987-06-09 | 1997-04-23 | 三菱電機株式会社 | Semiconductor device |
| JP2810130B2 (en) * | 1989-07-26 | 1998-10-15 | 松下電工株式会社 | Semiconductor package |
| JPH03297152A (en) * | 1990-04-16 | 1991-12-27 | Hitachi Chem Co Ltd | Manufacture of semiconductor device |
| JP2962586B2 (en) * | 1991-03-05 | 1999-10-12 | 新光電気工業株式会社 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
| JPH05144980A (en) * | 1991-11-25 | 1993-06-11 | Sumitomo Bakelite Co Ltd | Manufacture of semiconductor loading substrate |
| JPH05218228A (en) * | 1992-02-04 | 1993-08-27 | Ibiden Co Ltd | Substrate for electronic component mounting use |
| JPH0645401A (en) * | 1992-07-23 | 1994-02-18 | Nec Corp | Package for semiconductor device |
-
1994
- 1994-04-05 JP JP6715494A patent/JP3617072B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07283336A (en) | 1995-10-27 |
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