JP3205686B2 - Semiconductor device for mounting and its mounting method - Google Patents
Semiconductor device for mounting and its mounting methodInfo
- Publication number
- JP3205686B2 JP3205686B2 JP21173195A JP21173195A JP3205686B2 JP 3205686 B2 JP3205686 B2 JP 3205686B2 JP 21173195 A JP21173195 A JP 21173195A JP 21173195 A JP21173195 A JP 21173195A JP 3205686 B2 JP3205686 B2 JP 3205686B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- bump
- bumps
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止された実装用
半導体装置とその実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device for mounting and a method for mounting the same.
【０００２】[0002]
【従来の技術】従来、半導体装置は図１１に示すよう
に、リードフレーム１のタブ上に搭載された半導体素子
３の電極であるボンディングパッド２４とインナーリー
ドをボンディングワイヤ２３で接続した構造をとってい
る。そして、プリント基板９上にリードフレーム１を接
続はんだ２５で固着している。2. Description of the Related Art Conventionally, as shown in FIG. 11, a semiconductor device has a structure in which a bonding pad 24 which is an electrode of a semiconductor element 3 mounted on a tab of a lead frame 1 and an inner lead are connected by a bonding wire 23. ing. Then, the lead frame 1 is fixed on the printed circuit board 9 with connection solder 25.
【０００３】しかし、最近では、半導体装置の実装密度
を向上させる目的から、図１２に示すような半導体素子
上に接着テープ２６を用いてリードフレーム１に搭載
後、半導体素子の電極であるボンディングパッドとイン
ナーリードとを接続するＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈ
ｉｐ）方式がＤＲＡＭ等の半導体装置に採用されてい
る。However, recently, for the purpose of improving the mounting density of a semiconductor device, the semiconductor device is mounted on a lead frame 1 using an adhesive tape 26 as shown in FIG. LOC (Lead On Ch) that connects
The ip) method is used for semiconductor devices such as DRAM.
【０００４】また、半導体素子の電極であるボンディン
グパッド２４と外部リードとの接続にボンディングワイ
ヤ２３を用いないで、金属バンプで直接接続する構造の
半導体装置も見受けられる。[0004] Also, there is a semiconductor device having a structure in which a bonding pad 23, which is an electrode of a semiconductor element, and an external lead are directly connected by a metal bump without using a bonding wire 23.
【０００５】半導体装置は、その信頼性を確保するた
め、通常は半導体素子とリードとを接続後、樹脂封止が
行なわれている。これらの半導体装置は、図１１（ｂ）
と図１２（ｂ）に示すように、そのリードフレーム１の
端子が接続半田２５によってプリント基板９上に接続，
固定され実装される。[0005] In order to ensure the reliability of a semiconductor device, resin sealing is usually performed after connecting a semiconductor element and a lead. These semiconductor devices are shown in FIG.
As shown in FIG. 12B, the terminals of the lead frame 1 are connected to the printed
Fixed and implemented.
【０００６】上記のような従来の半導体装置では、外部
回路との接続用リードが半導体素子から水平にはみ出る
ような構造となっているため、半導体装置の外形寸法を
小さくするには限界がある。In the above-described conventional semiconductor device, the lead for connecting to an external circuit has a structure that protrudes horizontally from the semiconductor element, so that there is a limit in reducing the external dimensions of the semiconductor device.
【０００７】また、半導体装置の多ピン化に伴い、その
ピン数を多くするにはリード間の狭ピッチ化が必要であ
るが、ピッチが０.３ｍｍ以下になると、半導体装置の
プリント基板への実装が困難になる。そのため、多ピン
化するためには半導体装置の外形寸法を大きくする必要
がある。また、水平にはみ出たリードを有する半導体装
置では、リード長による抵抗インダクタンスを無視でき
ず、半導体装置の高速化に影響を及ぼす。Further, as the number of pins of a semiconductor device increases, it is necessary to reduce the pitch between leads in order to increase the number of pins. However, if the pitch becomes less than 0.3 mm, the semiconductor device may not be mounted on a printed circuit board. Implementation becomes difficult. Therefore, in order to increase the number of pins, it is necessary to increase the outer dimensions of the semiconductor device. Further, in a semiconductor device having a lead that protrudes horizontally, the resistance inductance due to the lead length cannot be ignored, which affects the speed of the semiconductor device.
【０００８】これらの問題を解決するため、半導体装置
を外部回路と接続するリードを半導体素子ボンディング
パッドに対して垂直方向に設ける構造が提案されてい
る。In order to solve these problems, there has been proposed a structure in which leads for connecting a semiconductor device to an external circuit are provided in a direction perpendicular to a semiconductor element bonding pad.
【０００９】例えば、図１３に示すように、半導体素子
３の電極表面に金属柱体やバンプを設け、バンプ部分を
残して全体を封止樹脂５で封止した構造のものが特開平
５−８２５８２号、同５−２９１３４６号、同６−１２
０２９７号、同６−１５１６５０号、同６−３１０５６
３号、同６−３０２６０４号公報に記載されている。For example, as shown in FIG. 13, a structure in which a metal column or a bump is provided on an electrode surface of a semiconductor element 3 and the whole is sealed with a sealing resin 5 except for a bump portion is disclosed in Japanese Unexamined Patent Application Publication No. No. 82581, No. 5-291346, No. 6-12
Nos. 0297, 6-151650 and 6-31056
No. 3, 6-302604.
【００１０】さらに、前記バンプを有する半導体素子に
おいて、バンプ接合部の信頼性を上げるための方法も種
々提案されている。例えば、特開平６−２１６１９４号
公報には応力緩和プレート２７を半導体素子３の上面に
貼り付けた構造〔図１４（ａ）〕が、また、サーフェイ
スマウントテクノロジー ９３年 冬号には半導体素子
３とプリント基板９との間に、注入樹脂２８を注入し、
これにより応力を分散する方法〔図１４（ｂ）〕が示さ
れている。[0010] Further, various methods have been proposed for improving the reliability of the bump bonding portion in the semiconductor device having the bump. For example, Japanese Patent Application Laid-Open No. 6-216194 discloses a structure in which a stress relaxation plate 27 is adhered to the upper surface of a semiconductor element 3 (FIG. 14A). Inject resin 28 between the printed circuit board 9 and
A method for dispersing the stress (FIG. 14B) is shown.
【００１１】[0011]
【発明が解決しようとする課題】上記従来技術は、半導
体装置の外形寸法の小型化や高速化に効果があるもの
の、半導体装置としての信頼性を十分満足することはで
きない。Although the above prior art is effective in reducing the external dimensions of the semiconductor device and in increasing the speed, the reliability of the semiconductor device cannot be sufficiently satisfied.
【００１２】前記半導体素子の電極表面に金属柱体やバ
ンプを設け、バンプ部分を残してその他を樹脂で封止し
た構造では、耐湿信頼性は優れているが、はんだ接続信
頼性に問題がある。特に、半導体素子の封止樹脂５は、
クラック防止のために低熱膨張化の傾向にあるため、半
導体装置とプリント基板との線膨張係数のミスマッチに
よる応力発生が、はんだ接続信頼性を大幅に低下させ
る。A structure in which metal pillars or bumps are provided on the electrode surface of the semiconductor element and the other portions are sealed with resin except for the bump portions has excellent moisture resistance reliability, but has a problem in solder connection reliability. . In particular, the sealing resin 5 of the semiconductor element is
Since the thermal expansion tends to be low in order to prevent cracks, the occurrence of stress due to the mismatch in the linear expansion coefficient between the semiconductor device and the printed circuit board greatly reduces the solder connection reliability.
【００１３】また、半導体素子全体を樹脂で封止した半
導体装置は、素子の放熱性が劣るため、素子発熱量が大
きい大容量，高速デバイスには適用できない場合があ
る。Further, a semiconductor device in which the entire semiconductor element is sealed with resin is inferior in heat dissipation of the element, so that it may not be applicable to a large-capacity, high-speed device having a large element heat generation.
【００１４】はんだ接続信頼性を向上する方法として提
案された前記応力緩和プレート２７は、はんだ接続性の
向上をある程度図ることができるが、実用レベルには到
達していないのが実情である。The stress relaxation plate 27 proposed as a method for improving the solder connection reliability can improve the solder connection to some extent, but has not reached a practical level.
【００１５】図１４の半導体素子とプリント基板との間
を樹脂で充填する方法は、応力を分散するためには効果
的であるが、半導体素子をプリント基板に搭載後に樹脂
を充填する工程が必要である。さらにまた、この樹脂の
充填方法は、半導体装置とプリント基板との狭い隙間へ
行なうために、充填不良やボイド発生の原因となる。さ
らに、半導体素子の一部が露出しているために、その管
理には細心の注意を要し、特に、湿度や汚染に弱いた
め、樹脂封止型半導体装置のように安易な取扱いができ
ない。The method of filling the space between the semiconductor element and the printed circuit board with a resin as shown in FIG. 14 is effective for dispersing stress, but requires a step of filling the resin after the semiconductor element is mounted on the printed circuit board. It is. Furthermore, since this resin filling method is performed in a narrow gap between the semiconductor device and the printed circuit board, it causes a defective filling or a void. Furthermore, since a part of the semiconductor element is exposed, it requires careful attention for its management. In particular, since it is susceptible to humidity and contamination, it cannot be handled as easily as a resin-sealed semiconductor device.
【００１６】本発明の目的は、はんだ接続信頼性並びに
耐湿信頼性の優れた実装用半導体装置およびそれの実装
方法を提供することにある。An object of the present invention is to provide a mounting semiconductor device having excellent solder connection reliability and moisture resistance reliability and a mounting method thereof.
【００１７】[0017]
【課題を解決するための手段】前記目的を達成する本発
明の要旨は次のとおりである。The gist of the present invention to achieve the above object is as follows.
【００１８】（１） 電極形成面に外部接続用の金属柱
体またはバンプを備えた半導体素子が樹脂封止されてい
る半導体装置であって、前記金属柱体またはバンプが形
成されている面に半硬化状態の熱硬化性樹脂層または成
形温度が１００℃以上の樹脂フィルム層が形成されてお
り、該樹脂層または樹脂フィルム層の厚さが、前記金属
柱体またはバンプの高さ以上の厚さに形成されているこ
とを特徴とする実装用半導体装置。(1) A semiconductor device in which a semiconductor element having a metal column or bump for external connection on a surface on which an electrode is formed is resin-sealed. A thermosetting resin layer in a semi-cured state or a resin film layer having a molding temperature of 100 ° C. or more is formed, and the thickness of the resin layer or the resin film layer is equal to or greater than the height of the metal column or the bump. A mounting semiconductor device characterized in that it is formed as described above.
【００１９】（２） 電極形成面に外部接続用の金属柱
体またはバンプを備えた半導体素子が前記金属柱体また
はバンプを露出させて樹脂封止されている半導体装置で
あって、前記金属柱体またはバンプが形成されている封
止樹脂面に半硬化状態の熱硬化性樹脂層または成形温度
が１００℃以上の樹脂フィルム層が形成されていること
を特徴とする実装用半導体装置。(2) A semiconductor device in which a semiconductor element having a metal column or bump for external connection on an electrode forming surface is sealed with a resin by exposing the metal column or bump, and A mounting semiconductor device, wherein a semi-cured thermosetting resin layer or a resin film layer having a molding temperature of 100 ° C. or more is formed on a sealing resin surface on which a body or a bump is formed.
【００２０】本発明において、半硬化状態の熱硬化性樹
脂層または１００℃以上で成形可能な樹脂フィルム層
は、半導体装置とプリント基板との間の接着と、発生す
る応力を分散させるために設けるものである。この熱硬
化性樹脂層または樹脂フィルム層は圧着させながら、加
熱することにより樹脂層または樹脂フィルム層を溶融し
半導体装置とプリント基板とを密着させる。In the present invention, a semi-cured thermosetting resin layer or a resin film layer moldable at 100 ° C. or higher is provided for bonding between a semiconductor device and a printed board and dispersing generated stress. Things. The thermosetting resin layer or the resin film layer is heated while being pressed, so that the resin layer or the resin film layer is melted and the semiconductor device and the printed board are brought into close contact with each other.
【００２１】さらに、加圧した状態で前記金属柱体また
はバンプのリフロー温度（２００℃以上）に上昇させる
ことにより、金属柱体またはバンプを一部溶融させるこ
とによりプリント基板と電気的な接続を行う。この場
合、半硬化状態の熱硬化性樹脂層は加熱によって硬化反
応が進行し、半導体装置とプリント基板とを強固に接着
する。樹脂フィルム層の場合は、金属柱体またはバンプ
の接続後、冷却することによって同様に半導体装置とプ
リント基板とを強固に接着する。Further, the metal column or the bump is raised to a reflow temperature (200 ° C. or more) of the metal column or the bump in a pressurized state, and the metal column or the bump is partially melted to establish an electrical connection with the printed circuit board. Do. In this case, the curing reaction of the thermosetting resin layer in the semi-cured state proceeds by heating, and the semiconductor device and the printed circuit board are firmly bonded. In the case of a resin film layer, the semiconductor device and the printed board are similarly firmly bonded by cooling after connecting the metal pillars or the bumps.
【００２２】以上の操作によって、半導体装置とプリン
ト基板との間に樹脂層が形成されるが、この樹脂層はボ
イドや未充填部分の発生を抑える必要がある。そのため
に半硬化状態の熱硬化性樹脂層または１００℃以上で成
形可能な樹脂フィルム層の厚さを、金属柱体またはバン
プの高さ以上の厚さに形成することが望ましい。これに
よって加圧、加熱時に溶融した樹脂は金属柱体またはバ
ンプ周辺の微細な部分にまで充填され、ボイドの少ない
均一な樹脂層を得ることができる。By the above operation, a resin layer is formed between the semiconductor device and the printed circuit board, and it is necessary to suppress the occurrence of voids and unfilled portions in this resin layer. For this purpose, it is desirable that the thickness of the semi-cured thermosetting resin layer or the resin film layer moldable at 100 ° C. or higher be equal to or greater than the height of the metal pillars or bumps. As a result, the resin melted at the time of pressurization and heating is filled up to a minute portion around the metal pillar or the bump, and a uniform resin layer with few voids can be obtained.
【００２３】本発明における半硬化状態の熱硬化性樹脂
は、半導体装置の取扱い性を図るため、形成後の樹脂表
面をタックフリー（粘着のない状態）にする必要があ
る。こうした樹脂としては、従来から半導体の封止また
は接着等に用いられているエポキシ樹脂や熱硬化性のポ
リイミド樹脂があるが、これらの中で室温において固形
のものが半硬化状態でタックフリーにできるため好適で
ある。The thermosetting resin in the semi-cured state in the present invention needs to have a tack-free (adhesion-free state) surface of the formed resin in order to facilitate the handling of the semiconductor device. As such resins, there are epoxy resins and thermosetting polyimide resins which have been conventionally used for sealing or bonding of semiconductors, and among them, solid ones at room temperature can be tack-free in a semi-cured state. Therefore, it is suitable.
【００２４】これら半硬化状態の熱硬化性樹脂は、線膨
張係数を半導体素子やプリント基板のそれに近付けるこ
とにより熱応力を低減させることができる。例えば、無
機質フィラまたは繊維を配合することができる。無機質
フィラとしては溶融シリカ、結晶性シリカ、アルミナ、
窒化アルミナ等の１種以上を用いることができる。無機
質繊維としてはガラスクロス、ガラスマット等があり、
これらを配合し半硬化状態（Ｂステージ）にしたエポキ
シ樹脂またはポリイミド樹脂等のプリプレグを用いるこ
とも可能である。These semi-cured thermosetting resins can reduce thermal stress by bringing the coefficient of linear expansion closer to that of a semiconductor element or a printed circuit board. For example, inorganic fillers or fibers can be blended. As the inorganic filler, fused silica, crystalline silica, alumina,
One or more of alumina nitride and the like can be used. As inorganic fibers, there are glass cloth, glass mat, etc.
It is also possible to use a prepreg such as an epoxy resin or a polyimide resin in which these are blended into a semi-cured state (B stage).
【００２５】これらの樹脂または無機質のフィラまたは
繊維を含む樹脂組成物は、金属柱体またはバンプが形成
された半導体装置に次の方法で適用することができる。The resin or the resin composition containing an inorganic filler or fiber can be applied to a semiconductor device having a metal pillar or a bump formed by the following method.
【００２６】固形のエポキシ樹脂または熱硬化性ポリイ
ミド樹脂からなる組成物を、溶剤を用いて液状となし、
スクリーン印刷またはデイスペンサ方式によって半導体
装置の所定の面上に塗布した後、１５０℃以下で溶剤を
蒸発揮散させて得られる。A composition comprising a solid epoxy resin or a thermosetting polyimide resin is converted into a liquid state using a solvent,
It is obtained by applying the solution on a predetermined surface of the semiconductor device by screen printing or dispenser method, and then evaporating the solvent at 150 ° C. or less.
【００２７】溶剤を使用しない場合は、樹脂組成物を１
２０℃以下で混練機を用いて均一に混練した後、タブレ
ット成形機等によってペレット化し、半導体装置の所定
の面上に熱圧着して得ることができる。この時、上記ペ
レットをフィルム上に配置して半導体装置に熱圧着して
転写することもできる。さらに、ペレットの転写を容易
にするため、予め、シリコーンオイルやシリコーン樹脂
で離型処理したフィルムを用いることも可能である。When no solvent is used, the resin composition
After uniformly kneading at 20 ° C. or lower using a kneading machine, the mixture can be pelletized by a tablet molding machine or the like, and can be obtained by thermocompression bonding on a predetermined surface of a semiconductor device. At this time, the pellets can be arranged on a film and transferred by thermocompression bonding to a semiconductor device. Furthermore, in order to facilitate the transfer of the pellets, it is also possible to use a film that has been previously subjected to a release treatment with silicone oil or silicone resin.
【００２８】本発明においては、半硬化状態の熱硬化性
樹脂表面のタックフリーを得るために、樹脂内部の流動
性を維持させたまま、表面層のみをほぼ完全に硬化させ
る方法を採用することができる。それは、光硬化性樹脂
と熱硬化性樹脂との併用にある。この場合、光照射によ
って表面層の光硬化性樹脂の硬化を優先的に行なうこと
ができる。この時に、熱硬化性樹脂は反応が進まないた
め、プリント基板への実装時に樹脂層全体の流動，硬化
が可能となり、半導体装置とプリント基板との間で強固
な接着を容易に得ることができる。In the present invention, in order to obtain tack-free on the thermosetting resin surface in a semi-cured state, a method of almost completely curing only the surface layer while maintaining fluidity inside the resin is employed. Can be. It lies in the combination of a photocurable resin and a thermosetting resin. In this case, the photocurable resin of the surface layer can be preferentially cured by light irradiation. At this time, the reaction of the thermosetting resin does not proceed, so that the entire resin layer can flow and harden at the time of mounting on the printed board, and a strong bond can be easily obtained between the semiconductor device and the printed board. .
【００２９】光硬化性樹脂としては、アクリレート基ま
たはメタクリレート基を有する樹脂に、光重合開始剤を
配合した組成物や、芳香族ジアゾニウム塩、ジアリルヨ
ードニウム塩、スルホニウム塩等の光硬化剤を含むエポ
キシ樹脂が用いられる。Examples of the photocurable resin include a composition in which a photopolymerization initiator is added to a resin having an acrylate group or a methacrylate group, and an epoxy containing a photocuring agent such as an aromatic diazonium salt, a diallyliodonium salt, or a sulfonium salt. Resin is used.
【００３０】上記光硬化性樹脂と併用する熱硬化性樹脂
としては、室温で固形、あるいは、液状の樹脂、例え
ば、液状エポキシ樹脂を用いることができる。また、前
記の光硬化剤と熱による硬化促進剤を併用したエポキシ
樹脂を用いることもできる。As the thermosetting resin used in combination with the photocurable resin, a resin which is solid or liquid at room temperature, for example, a liquid epoxy resin can be used. Further, an epoxy resin in which the above-mentioned photocuring agent and a curing accelerator by heat are used in combination can also be used.
【００３１】これらの熱硬化性樹脂または光硬化性樹脂
は、前記無機質フィラまたは繊維を配合することも可能
である。These thermosetting resins or photocurable resins can also contain the above-mentioned inorganic fillers or fibers.
【００３２】本発明の１００℃以上で成形可能な樹脂フ
ィルムとしては、半導体装置とプリント基板との接着力
を上げるためその少なくとも一方の表面に熱硬化性樹脂
層を有するものがよい。上記フィルムとしてはポリイミ
ド、ポリフェニレンスルフィド、アラミド、ポリエーテ
ルケトン、ポリエーテルイミド、ポリエーテルスルホン
等の耐熱性フィルムがある。これに前記のエポキシ樹脂
または熱硬化性のポリイミド樹脂をフィルム上に塗布ま
たはラミネートすることにより得られる。The resin film of the present invention which can be molded at 100 ° C. or higher preferably has a thermosetting resin layer on at least one surface thereof in order to increase the adhesive strength between the semiconductor device and the printed circuit board. Examples of the film include a heat-resistant film such as polyimide, polyphenylene sulfide, aramid, polyether ketone, polyether imide, and polyether sulfone. It is obtained by applying or laminating the epoxy resin or the thermosetting polyimide resin on a film.
【００３３】また、耐熱性の樹脂フィルムの少なくとも
一方の面に熱可塑性樹脂層を設けたフィルムを用いるこ
とができる。Further, a film having a thermoplastic resin layer provided on at least one surface of a heat-resistant resin film can be used.
【００３４】上記耐熱性の樹脂フィルムとしては、リフ
ロー時の温度においてフィルムの変形が生じないような
ガラス転移温度２５０℃以上の樹脂が好適であり、例え
ば、ポリイミド樹脂等が用いられる。As the heat-resistant resin film, a resin having a glass transition temperature of 250 ° C. or higher which does not cause deformation of the film at the temperature at the time of reflow is suitable. For example, a polyimide resin is used.
【００３５】上記熱可塑性樹脂としては、２００℃以上
で溶融する樹脂であればよいが、好ましくは耐熱性ポリ
エステル、ポリブチレンテレフタレート、ポリアミドイ
ミド等の接着性が優れた樹脂が好ましい。この場合、半
導体装置とプリント基板との圧着時の温度（１５０℃以
下）と、金属柱体またはバンプを接続するためのリフロ
ー温度（２００℃以上）を区別するために、溶融温度の
異なる熱可塑性樹脂を重ね合わせたものが好ましい。例
えば、溶融温度１５０℃以下の熱可塑性樹脂と溶融温度
２００℃以上の熱可塑性樹脂とを前記耐熱性フィルムの
両面に形成したフィルムが使用される。The thermoplastic resin may be any resin that can be melted at a temperature of 200 ° C. or higher, and is preferably a resin having excellent adhesion such as heat-resistant polyester, polybutylene terephthalate, or polyamideimide. In this case, in order to distinguish the temperature at the time of pressure bonding between the semiconductor device and the printed board (150 ° C. or less) and the reflow temperature (200 ° C. or more) for connecting the metal pillars or the bumps, thermoplastics having different melting temperatures are used. Those obtained by overlapping resins are preferred. For example, a film in which a thermoplastic resin having a melting temperature of 150 ° C. or less and a thermoplastic resin having a melting temperature of 200 ° C. or more are formed on both surfaces of the heat-resistant film is used.
【００３６】本発明の実装用半導体装置は、半導体素子
の放熱性を向上させるために、前記電極表面と反対側の
半導体素子素面に放熱プレートを配置する構造であって
もよい。放熱プレートとしては、特に、熱伝導性に優れ
たセラミックや、銅，アルミ等の金属が主に使われる。
この他に、金属をコアとする樹脂基板や銅配線樹脂基板
も放熱効果があり、放熱プレートとして用いることがで
きる。The mounting semiconductor device of the present invention may have a structure in which a heat dissipation plate is disposed on a semiconductor element element surface opposite to the electrode surface in order to improve heat dissipation of the semiconductor element. In particular, ceramics having excellent thermal conductivity and metals such as copper and aluminum are mainly used as the heat radiation plate.
In addition, a resin substrate having a metal core or a copper wiring resin substrate also has a heat radiation effect and can be used as a heat radiation plate.
【００３７】これらの放熱プレートは、半導体装置と外
部回路であるプリント基板とのはんだ接続信頼性の向上
効果も兼ね備えているため、線膨張係数を半導体素子よ
りも大きくする必要がある。好ましくは、プリント基板
に近い線膨張係数の放熱プレートを用いる。Since these heat radiating plates also have the effect of improving the reliability of solder connection between the semiconductor device and a printed circuit board as an external circuit, it is necessary to make the linear expansion coefficient larger than that of the semiconductor element. Preferably, a heat dissipation plate having a linear expansion coefficient close to that of a printed circuit board is used.
【００３８】また、この放熱プレートは、半導体素子を
金型を用いて樹脂封止する場合に、金型押さえのフレー
ム治具として兼用できる。樹脂封止後、半導体装置から
はみ出た前記フレーム治具部分を、切断除去して半導体
装置の外形寸法内に在る部分だけ残し放熱プレートとす
ることができる。Further, this heat dissipation plate can also be used as a frame jig for holding down the mold when the semiconductor element is sealed with a resin using a mold. After the resin sealing, the frame jig portion protruding from the semiconductor device can be cut and removed to leave only a portion within the external dimensions of the semiconductor device to form a heat dissipation plate.
【００３９】[0039]
【作用】本発明の実装用半導体装置は、金属柱体または
バンプのはんだ接続信頼性が高い理由は、半硬化状態の
熱硬化性樹脂層または１００℃以上で成形可能な樹脂フ
ィルム層が実装後、半導体装置とプリント基板との間に
均一な絶縁層を形成し、金属柱体またはバンプに発生す
る応力を分散させるためである。The semiconductor device for mounting of the present invention has a high reliability of solder connection of metal pillars or bumps because a thermosetting resin layer in a semi-cured state or a resin film layer moldable at 100 ° C. or higher is mounted. This is because a uniform insulating layer is formed between the semiconductor device and the printed board to disperse the stress generated in the metal pillar or the bump.
【００４０】また、湿度や汚染に対する信頼性を確保で
きるのは、半導体素子全体が封止樹脂（または封止樹脂
と放熱プレート）で完全に密閉されているためである。Further, the reliability against humidity and contamination can be ensured because the entire semiconductor element is completely sealed with the sealing resin (or the sealing resin and the heat dissipation plate).
【００４１】[0041]
【実施例】本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.
【００４２】〔実施例 １〕図１は、本実施例の実装用
半導体装置の製造工程を示す模式断面図である。[Embodiment 1] FIG. 1 is a schematic sectional view showing a manufacturing process of a mounting semiconductor device of this embodiment.
【００４３】銅製のリードフレーム１のダイパッド２上
〔図１（ａ）〕に、半導体素子３を銀含有エポキシ樹脂
系ダイボンディング剤で接着し、搭載する〔図１
（ｂ）〕。The semiconductor element 3 is mounted on the die pad 2 of the copper lead frame 1 [FIG. 1 (a)] with a silver-containing epoxy resin die bonding agent [FIG.
(B)].
【００４４】この半導体素子を搭載したリードフレーム
をモールド金型４内に配置し、低圧トランスファ成形機
を用いて１７５℃，９０秒間の条件で、溶融シリカ含有
エポキシ樹脂系成形材料により樹脂封止した後〔図１
（ｃ）〕、１７５℃，５時間の後硬化を行なう〔図１
（ｄ）〕。The lead frame on which the semiconductor element was mounted was placed in the mold 4 and sealed with a fused silica-containing epoxy resin-based molding material at 175 ° C. for 90 seconds using a low-pressure transfer molding machine. After [Fig.
(C)] After-curing at 175 ° C. for 5 hours [FIG.
(D)].
【００４５】次に、はんだボール６を用いて、半導体素
子の電極パッド部分に外部回路と接続するためのバンプ
を形成する〔図１（ｅ）〕。Next, bumps for connecting to an external circuit are formed on the electrode pad portions of the semiconductor element using the solder balls 6 (FIG. 1E).
【００４６】この半導体装置のバンプ形成面に、溶融シ
リカを含む室温で固形のエポキシ樹脂組成物を溶剤に溶
解し、スクリーン印刷で塗布した後、１２０℃で溶剤を
乾燥させて、半硬化状態の熱硬化性樹脂層８を、バンプ
の高さ以上の厚さに形成〔図１（ｆ）〕する。On a bump-forming surface of this semiconductor device, a solid epoxy resin composition containing fused silica at room temperature was dissolved in a solvent and applied by screen printing, and then the solvent was dried at 120 ° C. to obtain a semi-cured state. The thermosetting resin layer 8 is formed to have a thickness equal to or greater than the height of the bump [FIG. 1 (f)].
【００４７】上記の室温で固形のエポキシ樹脂組成物
は、オルソクレゾールノボラック型エポキシ樹脂（軟化
温度６５℃）と、フェノールノボラック樹脂硬化剤（軟
化温度６５℃）およびイミダゾール系硬化促進剤からな
る組成物で、溶剤にはメチルエチルケトンを用いた。The above-mentioned epoxy resin composition which is solid at room temperature is a composition comprising an orthocresol novolak type epoxy resin (softening temperature: 65 ° C.), a phenol novolak resin curing agent (softening temperature: 65 ° C.) and an imidazole curing accelerator. The solvent used was methyl ethyl ketone.
【００４８】以上の製造工程によって、図１（ｆ）に示
すような、バンプ形成面に半硬化状態のエポキシ樹脂組
成物からなる熱硬化性樹脂層を有する実装用半導体装置
を得ることができる。By the above manufacturing steps, a mounting semiconductor device having a thermosetting resin layer made of a semi-cured epoxy resin composition on the bump formation surface as shown in FIG. 1F can be obtained.
【００４９】〔実施例 ２〕図２は本実施例の実装用半
導体装置のバンプ配置面とその断面を示す模式図であ
る。Embodiment 2 FIG. 2 is a schematic diagram showing a bump arrangement surface and a cross section of a mounting semiconductor device of this embodiment.
【００５０】実施例１と同様にして、溶融シリカを含
み、固形のマレイミド樹脂からなる半硬化状態の熱硬化
性樹脂層８を、デイスペンサを用いて、バンプ形成面の
バンプ配列間に、該バンプの高さ以上の厚さに線状に形
成し、実装用半導体装置を作成した。In the same manner as in Example 1, a semi-cured thermosetting resin layer 8 containing fused silica and made of a solid maleimide resin was placed between bump arrangements on the bump formation surface using a dispenser. The semiconductor device for mounting was formed in a linear shape with a thickness of not less than the height.
【００５１】〔実施例 ３〕図３は本実施例の実装用半
導体装置のバンプ配置面とその断面を示す模式図であ
る。[Embodiment 3] FIG. 3 is a schematic diagram showing a bump arrangement surface and a cross section of a mounting semiconductor device of this embodiment.
【００５２】実施例１と同様にして、溶融シリカを含
み、固形エポキシ樹脂からなる半硬化状態の熱硬化性樹
脂層８を、バンプ形成面全面に、該バンプの高さ以上の
厚さに形成し、実装用半導体装置を作成した。In the same manner as in Example 1, a semi-cured thermosetting resin layer 8 containing fused silica and made of a solid epoxy resin is formed on the entire bump formation surface to a thickness equal to or greater than the height of the bump. Then, a mounting semiconductor device was prepared.
【００５３】〔実施例 ４〕図４は本実施例の実装用半
導体装置の製造工程を示す模式断面図である。[Embodiment 4] FIG. 4 is a schematic sectional view showing a manufacturing process of a mounting semiconductor device of this embodiment.
【００５４】実施例１と同様な方法で、銅製のリードフ
レーム１のダイパッド２（ａ）上に搭載した半導体素子
３（ｂ）を、モールド金型４に配置（ｃ）し、溶融シリ
カを含むエポキシ樹脂系成形材料で樹脂封止した
（ｄ）。In the same manner as in Example 1, the semiconductor element 3 (b) mounted on the die pad 2 (a) of the copper lead frame 1 is placed (c) in a mold 4 and contains fused silica. The resin was sealed with an epoxy resin-based molding material (d).
【００５５】ここで、実施例１とは異なる形状の金型を
用いたため、バンプ搭載面には樹脂層が形成されない構
造を有する。この面にはんだボールを用いて、半導体素
子の電極パッド部分にバンプを形成する（ｅ）。その
後、バンプ搭載面に、実施例１と同じエポキシ樹脂組成
物を塗布し（ｆ）、１２０℃で乾燥することによりバン
プ高さ以上の厚さを有する半硬化状態の熱硬化性樹脂層
８を形成して実装用半導体装置を得た（ｇ）。Here, since a mold having a shape different from that of the first embodiment is used, the structure is such that no resin layer is formed on the bump mounting surface. A bump is formed on the electrode pad portion of the semiconductor element using a solder ball on this surface (e). Thereafter, the same epoxy resin composition as in Example 1 is applied to the bump mounting surface (f) and dried at 120 ° C. to form a semi-cured thermosetting resin layer 8 having a thickness equal to or greater than the bump height. Thus, a semiconductor device for mounting was obtained (g).
【００５６】以上の製造工程で得た実装用半導体装置の
プリント基板への実装例を図５の（ａ）〜（ｃ）に示
す。FIGS. 5A to 5C show examples of mounting the mounting semiconductor device obtained by the above manufacturing steps on a printed circuit board.
【００５７】実装用半導体装置をプリント基板９に搭載
後、放熱プレート面に加圧用プレート１１を介して加圧
する。加圧したまま温度を１５０℃まで上げ、半硬化状
態の樹脂層を溶融させることによって、バンプのはんだ
ボール６とプリント基板９の配線パターン１０とを完全
に接触させる（ａ）。After the mounting semiconductor device is mounted on the printed circuit board 9, pressure is applied to the heat radiating plate surface via the pressing plate 11. The temperature is raised to 150 ° C. while pressing, and the semi-cured resin layer is melted, so that the solder balls 6 of the bumps and the wiring pattern 10 of the printed circuit board 9 are completely contacted (a).
【００５８】次いで、同じ圧力で加圧したまま、２４０
℃に加熱してバンプをプリント基板の配線に確実に接
続，固定して半導体装置を実装する（ｂ）ことにより、
半硬化状態の樹脂層は完全硬化状態の樹脂層１２とな
る。加圧用プレート１１を取り除いて半導体装置の実装
が完了する（ｃ）。Next, with the same pressure applied, 240
The semiconductor device is mounted by heating to ℃ and securely connecting and fixing the bumps to the wiring of the printed circuit board (b).
The resin layer in a semi-cured state becomes the resin layer 12 in a completely cured state. The mounting of the semiconductor device is completed by removing the pressing plate 11 (c).
【００５９】本実施例においては、図４（ａ）の工程後
に、半導体装置の電気特性をチェックして動作不良を検
査することができる。この工程後では、半導体装置とプ
リント基板との間に形成された絶縁樹脂層の硬化がまだ
完全に終了していないため、接着力が低い。そのため、
搭載した半導体装置に動作不良等があれば、急速な高温
加熱によって容易にプリント基板から着脱できる。この
ように、本発明の実装用半導体装置はリペア性にも優れ
ている。In the present embodiment, after the step of FIG. 4A, it is possible to check the electrical characteristics of the semiconductor device and inspect the operation failure. After this step, the adhesion of the insulating resin layer formed between the semiconductor device and the printed circuit board is low because the curing has not yet been completed. for that reason,
If the mounted semiconductor device has a malfunction or the like, it can be easily attached to and detached from the printed circuit board by rapid high-temperature heating. As described above, the mounting semiconductor device of the present invention has excellent repairability.
【００６０】〔実施例 ５〕図６は本実施例の実装用半
導体装置の製造工程を示す模式断面図である。[Embodiment 5] FIG. 6 is a schematic sectional view showing a manufacturing process of a semiconductor device for mounting according to this embodiment.
【００６１】アルミ製の金属キャップ１３に、半導体素
子３を銀含有エポキシ樹脂接着剤（図示省略）で接着す
る（ａ）。半導体素子の配線パッド部分にはんだボール
のバンプを形成する（ｂ）。次いで、溶融シリカを含む
液状封止樹脂１４（ビスフェノールＡ型エポキシ樹脂、
酸無水物、シリコーン可とう化剤およびイミダゾール硬
化促進剤からなる樹脂組成物）をデイスペンサで、半導
体素子３上にバンプ高さよりいくぶん低い位置まで注入
し、１５０℃で１時間の硬化を行なう（ｃ）。さらに、
バンプ配置面に光硬化性樹脂（エポキシアクリレート、
アクリレートモノマ、光重合開始剤）と熱硬化性樹脂
（エポキシ樹脂、酸無水物、イミダゾール）とを混合し
た液状の熱硬化性樹脂層１５を、デイスペンサーを用い
て半導体装置のバンプ面に再度塗布，形成した後
（ｄ）、その上部から高圧水銀灯により紫外線照射を行
ない、表面をタックフリーとして実装用半導体装置を得
た（ｅ）。The semiconductor element 3 is bonded to the aluminum metal cap 13 with a silver-containing epoxy resin adhesive (not shown) (a). A solder ball bump is formed on a wiring pad portion of the semiconductor element (b). Next, a liquid sealing resin 14 containing a fused silica (bisphenol A type epoxy resin,
A resin composition comprising an acid anhydride, a silicone flexibilizing agent and an imidazole curing accelerator) is injected onto the semiconductor element 3 with a dispenser to a position slightly lower than the bump height and cured at 150 ° C. for 1 hour (c). ). further,
Light curable resin (epoxy acrylate,
A liquid thermosetting resin layer 15 obtained by mixing an acrylate monomer, a photopolymerization initiator) and a thermosetting resin (epoxy resin, acid anhydride, imidazole) is applied again to the bump surface of the semiconductor device using a dispenser. After the formation, (d), ultraviolet light was irradiated from the upper part by a high-pressure mercury lamp, and the surface was tack-free to obtain a mounting semiconductor device (e).
【００６２】次に、上記の実装用半導体装置を、図５と
同様にしてプリント基板上に実装した。Next, the mounting semiconductor device was mounted on a printed circuit board in the same manner as in FIG.
【００６３】実装用半導体装置をプリント基板９に搭載
後、金属キャップ１３面に加圧用プレート１１を乗せて
加圧しながら温度を１５０℃まで上げ、半硬化状態の樹
脂層を溶融させることによって、バンプとプリント基板
の配線パターン１０とを完全に接触させ、同じ圧力で加
圧したまま、２４０℃に昇温してバンプをプリント基板
の配線パターンに接続，固定することによりプリント基
板上への半導体装置の実装が完了する。After the mounting semiconductor device is mounted on the printed circuit board 9, the temperature is raised to 150 ° C. while the pressing plate 11 is placed on the surface of the metal cap 13 and pressurized, and the semi-cured resin layer is melted. And the wiring pattern 10 of the printed circuit board are completely brought into contact with each other, and the temperature is raised to 240 ° C. while the same pressure is applied to connect and fix the bumps to the wiring pattern of the printed circuit board. Is completed.
【００６４】〔実施例 ６〕図７は本実施例の実装用半
導体装置の連続的な製造工程を示す模式断面図である。[Embodiment 6] FIG. 7 is a schematic sectional view showing a continuous manufacturing process of a mounting semiconductor device of this embodiment.
【００６５】実施例４で得られたバンプ形成後の半導体
装置を、支持フィルム１６上に予め形成された半硬化状
態の熱硬化性樹脂層１７のはんだボール挿入用穴１８に
バンプの位置を合わせて圧着する。The semiconductor device after bump formation obtained in Example 4 is aligned with the solder ball insertion hole 18 of the semi-cured thermosetting resin layer 17 formed on the support film 16 in advance. And crimp.
【００６６】なお、上記半硬化状態の熱硬化性樹脂は、
溶融シリカを含み、オルソクレゾールノボラック型エポ
キシ樹脂（軟化温度６５℃）とフェノールノボラック樹
脂硬化剤（軟化温度６５℃）およびトリフェニルホスフ
ィン硬化促進剤からなる固形のエポキシ樹脂組成物を、
溶剤を用いて液状にした後、支持フィルム１６上に塗布
し、１２０℃以下の温度で乾燥して形成する。この半硬
化状態の熱硬化性樹脂層１７には、予め、半導体装置の
バンプ位置に対応する穴１８がスタンピング法によって
設けてある。The thermosetting resin in the semi-cured state is:
A solid epoxy resin composition containing fused silica, an ortho-cresol novolak type epoxy resin (softening temperature 65 ° C.), a phenol novolak resin curing agent (softening temperature 65 ° C.) and a triphenylphosphine curing accelerator,
After it is made liquid using a solvent, it is applied on the support film 16 and dried at a temperature of 120 ° C. or less to form a film. The semi-cured thermosetting resin layer 17 is provided with holes 18 corresponding to the bump positions of the semiconductor device in advance by a stamping method.
【００６７】次に、前記バンプ形成後の半導体装置を、
圧着したまま１５０℃で短時間加熱して半硬化状態の熱
硬化性樹脂層１７による接着を行なう。その後、半導体
装置をテープから引きはがし、半硬化状態の熱硬化性樹
脂絶縁層を有する実装用半導体装置を得た。Next, the semiconductor device after the formation of the bumps is
Heating is performed at 150 ° C. for a short time while being pressed, so that the thermosetting resin layer 17 in a semi-cured state is bonded. Thereafter, the semiconductor device was peeled off from the tape to obtain a mounting semiconductor device having a thermosetting resin insulating layer in a semi-cured state.
【００６８】〔実施例 ７〕図８は本実施例の実装用半
導体装置と、それのプリント基板への実装例を示す模式
断面図である。Embodiment 7 FIG. 8 is a schematic sectional view showing a mounting semiconductor device of this embodiment and an example of mounting the same on a printed circuit board.
【００６９】実施例４で得たバンプ形成後の実装用半導
体装置を用い、バンプ位置に対応する穴を設けた熱硬化
性樹脂塗布フィルム１９と圧着する。フィルム１９はポ
リイミドフィルムの両面に、固形のエポキシ樹脂組成物
を塗布したもので、その厚さは半導体装置への圧着後に
おいてバンプ高さ以上となるように設定する。圧着はエ
ポキシ樹脂組成物が完全硬化しないよう、１５０℃以下
の温度で数分以内に行なう。Using the mounting semiconductor device after bump formation obtained in Example 4, it is pressure-bonded to the thermosetting resin coating film 19 provided with holes corresponding to the bump positions. The film 19 is formed by applying a solid epoxy resin composition to both surfaces of a polyimide film, and the thickness thereof is set to be equal to or larger than the bump height after pressure bonding to a semiconductor device. The pressure bonding is performed within several minutes at a temperature of 150 ° C. or less so that the epoxy resin composition is not completely cured.
【００７０】得られた実装用半導体装置は、プリント基
板９へ搭載後、加圧しながら２４０℃まで昇温して、バ
ンプをプリント基板の配線パターンに接続，固定する。After mounting the obtained semiconductor device on the printed circuit board 9, the temperature is raised to 240 ° C. while applying pressure to connect and fix the bumps to the wiring pattern of the printed circuit board.
【００７１】実装後の半導体装置はバンプ周辺部分が溶
融，硬化したエポキシ樹脂によって完全に充填されてお
り、ポリイミドフィルムとエポキシ樹脂とのボイドレス
絶縁層が半導体素子とプリント基板との間に形成され
る。The semiconductor device after mounting is completely filled with epoxy resin in which the bump periphery is melted and cured, and a voidless insulating layer of a polyimide film and epoxy resin is formed between the semiconductor element and the printed board. .
【００７２】〔実施例 ８〕図９は本実施例の実装用半
導体装置と、それのプリント基板への実装例を示す模式
断面図である。[Embodiment 8] FIG. 9 is a schematic sectional view showing a mounting semiconductor device of this embodiment and an example of mounting the same on a printed circuit board.
【００７３】実施例１で得たバンプ形成後の実装用半導
体装置を用い、バンプ位置に対応する穴１８を設けた熱
可塑性樹脂ラミネートフィルム２１と圧着する。該フィ
ルム２１はポリイミドフィルムに、融点１３０℃のポリ
エステルフィルムと融点２２５℃のポリブチレンテレフ
タレートフィルムとでサンドイッチしたものである。フ
ィルムの厚は、圧着後の厚さがバンプ高さ以上となるよ
うに設定されている。Using the mounting semiconductor device after the formation of the bumps obtained in Example 1, it is pressure-bonded to the thermoplastic resin laminated film 21 having the holes 18 corresponding to the bump positions. The film 21 is a polyimide film sandwiched between a polyester film having a melting point of 130 ° C. and a polybutylene terephthalate film having a melting point of 225 ° C. The thickness of the film is set so that the thickness after pressure bonding is equal to or greater than the bump height.
【００７４】また、半導体装置のプリント基板への圧着
後にバンプがプリント基板の配線部分と接触できるよ
う、低融点ポリエステルフィルムが絶縁層の厚さを調節
できるよう厚く形成されている。The low-melting-point polyester film is formed thick so that the thickness of the insulating layer can be adjusted so that the bump can come into contact with the wiring portion of the printed board after the semiconductor device is pressed onto the printed board.
【００７５】半導体装置とフィルム２１との圧着は、低
融点ポリエステルフィルムが溶融する１５０℃で加圧し
て行なう。得られた実装用半導体装置は、プリント基板
９へ搭載後、加圧しながらポリブチレンテレフタレート
フィルムが溶融できる２４０℃以上に昇温し、バンプを
プリント基板９の配線パターンに確実に接続する。その
後、室温まで冷却し、プリント基板配線パターンへのバ
ンプの接続を固定する。The pressure bonding between the semiconductor device and the film 21 is performed by applying a pressure at 150 ° C. at which the low melting point polyester film is melted. After mounting the obtained semiconductor device on the printed circuit board 9, the temperature is raised to 240 ° C. or higher at which the polybutylene terephthalate film can be melted while applying pressure, and the bump is securely connected to the wiring pattern of the printed circuit board 9. Then, it is cooled to room temperature, and the connection of the bump to the printed circuit board wiring pattern is fixed.
【００７６】実装後の半導体装置はバンプ周辺部が溶融
した熱可塑性樹脂２２によって完全に融着されており、
ポリイミドフィルムと熱可塑性樹脂からなるボイドレス
の絶縁層が半導体素子とプリント基板との間に形成され
る。The semiconductor device after mounting is completely fused with the thermoplastic resin 22 in which the periphery of the bump is melted.
A voidless insulating layer made of a polyimide film and a thermoplastic resin is formed between the semiconductor element and the printed board.
【００７７】〔実施例 ９〕図１０は、本実施例の実装
用マルチチップ半導体装置の製造工程を示す模式断面図
である。[Embodiment 9] FIG. 10 is a schematic sectional view showing a manufacturing process of a mounting multi-chip semiconductor device of this embodiment.
【００７８】銅リードフレーム１のダイパッド２上に
（ａ）、２個の半導体素子３を銀含有エポキシ樹脂系ダ
イボンディング剤で接着，搭載する（ｂ）。これら実装
用のマルチチップを搭載したリードフレームをモールド
金型４内に配置し、実施例１と同様に封止樹脂５によっ
て樹脂封止する（ｃ）。その後、１７５℃，５時間の樹
脂の後硬化を行ない（ｄ）、さらに、はんだボール６を
用いて、半導体素子の電極パッド部分に外部回路と接続
するためのバンプを形成する（ｅ）。(A) Two semiconductor elements 3 are bonded and mounted on a die pad 2 of a copper lead frame 1 with a silver-containing epoxy resin die bonding agent (b). The lead frame on which the mounting multi-chip is mounted is placed in the mold 4 and is sealed with the sealing resin 5 as in the first embodiment (c). Thereafter, post-curing of the resin is performed at 175 ° C. for 5 hours (d), and further, a bump for connecting to an external circuit is formed on the electrode pad portion of the semiconductor element using the solder ball 6 (e).
【００７９】上記バンプ配置面に実施例１と同様にし
て、半硬化状態のエポキシ樹脂組成物からなる樹脂層８
をバンプ高さ以上の厚さに形成する（ｆ）。In the same manner as in Example 1, a resin layer 8 made of a semi-cured epoxy resin composition
Is formed to a thickness equal to or greater than the bump height (f).
【００８０】以上の製造工程によって、銅製の放熱プレ
ート７と、バンプ形成面に固形のエポキシ樹脂組成物か
らなる半硬化状態の熱硬化性樹脂層８を有する実装用マ
ルチチップ半導体装置を得た。Through the above manufacturing steps, a mounting multi-chip semiconductor device having a copper heat dissipation plate 7 and a semi-cured thermosetting resin layer 8 made of a solid epoxy resin composition on the bump formation surface was obtained.
【００８１】〔実施例 １０〕実施例１〜９で得られた
本発明の実装用半導体装置のはんだ接続部の温度サイク
ル信頼性と耐湿信頼性を調べた。信頼性の条件は下記の
とおりである。Example 10 The reliability of temperature cycling and the reliability of humidity resistance of the solder joints of the mounting semiconductor device of the present invention obtained in Examples 1 to 9 were examined. The reliability conditions are as follows.
【００８２】なお、はんだ接続部の温度サイクル信頼性
は線膨張係数１.５×１０~5／℃のエキシ樹脂系ＦＲ−
４プリント基板への実装後の評価であり、耐湿信頼性は
半導体装置としての評価である。評価結果を表１に示
す。Incidentally, the temperature cycle reliability of the solder connection portion is determined by using an excimer resin FR-series having a linear expansion coefficient of 1.5 × 10 5 / ° C.
4 Evaluation after mounting on a printed circuit board, and moisture resistance reliability is evaluation as a semiconductor device. Table 1 shows the evaluation results.
【００８３】 はんだ接続部の温度サイクル信頼性：
１２５℃⇔−５５℃のヒートサイクルを１０００サイク
ル行ない、断線がないものを○、１０００サイクルに満
たないで断線したものを×で表す。Temperature cycle reliability of solder joints:
A heat cycle of 125 ° C.⇔−55 ° C. was performed for 1000 cycles, and those without disconnection are represented by ○, and those that were disconnected for less than 1,000 cycles are represented by x.
【００８４】 耐湿信頼性：６５℃／９５％ＲＨの雰
囲気中に５００時間放置し、アルミ電極部分またはバン
プ接続部分に腐食が認められないものを○、５００時間
未満で腐食が認められたものを×で表す。[0084] Humidity reliability: Leave in an atmosphere of 65 ° C./95% RH for 500 hours. If no corrosion was observed in the aluminum electrode portion or the bump connection portion, mark ○. If corrosion was observed in less than 500 hours. Represented by x.
【００８５】[0085]
【表１】 [Table 1]
【００８６】〔比較例 １〕図１に示す実装用半導体装
置の製造工程において、図１（ａ）〜（ｅ）の工程まで
で得られた半導体素子のバンプ形成面に半硬化状態の熱
硬化性樹脂層が形成されていない半導体装置を用いて、
実施例１０と同じ条件ではんだ接続部の温度サイクル信
頼性と耐湿信頼性を評価した。評価結果を表１に併せて
示す。COMPARATIVE EXAMPLE 1 In the manufacturing process of the mounting semiconductor device shown in FIG. 1, a semi-cured thermosetting state is formed on the bump forming surface of the semiconductor element obtained through the steps of FIGS. 1 (a) to 1 (e). Using a semiconductor device on which the conductive resin layer is not formed,
Under the same conditions as in Example 10, the temperature cycle reliability and the moisture resistance reliability of the solder connection were evaluated. The evaluation results are also shown in Table 1.
【００８７】〔比較例 ２〕図１４（ｂ）に示す半導体
素子が樹脂封止されていない構造半導体装置を用いて、
実施例１０と同じ条件ではんだ接続部の温度サイクル信
頼性と耐湿信頼性を評価した。なお、プリント基板への
実装は半導体装置とプリント基板との間に樹脂充填を行
なった。評価結果を表１に併せて示す。Comparative Example 2 Using a structural semiconductor device in which the semiconductor element shown in FIG.
Under the same conditions as in Example 10, the temperature cycle reliability and the moisture resistance reliability of the solder connection were evaluated. In addition, resin was filled between the semiconductor device and the printed board for mounting on the printed board. The evaluation results are also shown in Table 1.
【００８８】表１から明らかなように、本発明の実装用
半導体装置は、耐湿信頼性が優れており、プリント基板
への実装後のはんだ接続部の信頼性も優れている。As is clear from Table 1, the semiconductor device for mounting according to the present invention has excellent moisture resistance reliability, and also has excellent reliability of the solder connection portion after mounting on a printed circuit board.
【００８９】比較例１のものは、耐湿信頼性は優れてい
るが、プリント基板への実装後のはんだ接続部の応力が
大きくなり接続信頼性が劣る。[0099] The device of Comparative Example 1 is excellent in the moisture resistance reliability, but the stress of the solder connection portion after mounting on the printed circuit board is large and the connection reliability is inferior.
【００９０】比較例２のものは、はんだ接続信頼性は確
保できるもののプリント基板への実装後、半導体素子と
プリント基板との間の樹脂充填の工程が必要であり、さ
らに、耐湿信頼性に問題がある。In the case of Comparative Example 2, although the solder connection reliability can be ensured, a resin filling step between the semiconductor element and the printed board is required after mounting on the printed board, and furthermore, there is a problem with the moisture resistance reliability. There is.
【００９１】[0091]
【発明の効果】本発明によれば、半導体素子の電極表面
と接合する金属柱体またはバンプの形成面に半硬化状態
の熱硬化性樹脂層、または、１００℃以上で成形可能な
樹脂フィルム層を設けたことにより、金属柱体またはバ
ンプに生ずる応力を分散できる均一絶縁層をプリント基
板への実装時に容易に形成でき、はんだ接続信頼性を向
上させる実装用半導体装置を得ることができる。According to the present invention, a semi-cured thermosetting resin layer or a resin film layer moldable at a temperature of 100 ° C. or more is formed on a surface on which a metal pillar or bump to be bonded to an electrode surface of a semiconductor element is formed. Is provided, a uniform insulating layer capable of dispersing the stress generated in the metal pillars or bumps can be easily formed at the time of mounting on a printed circuit board, and a mounting semiconductor device with improved solder connection reliability can be obtained.
【００９２】また、半導体素子全体が封止樹脂（または
封止樹脂と放熱プレート）と前記半硬化状態の熱硬化性
樹脂層、または、１００℃以上で成形可能な樹脂フィル
ム層により完全に密閉された構造となっているので、耐
湿信頼性に優れている。Further, the entire semiconductor element is completely sealed by a sealing resin (or a sealing resin and a heat dissipation plate) and the thermosetting resin layer in the semi-cured state, or a resin film layer moldable at 100 ° C. or more. It has excellent moisture resistance reliability because of its structure.
【００９３】さらにまた、半導体素子表面に放熱プレー
トを配置することにより、大容量，高速のデバイスに適
用できる実装用半導体装置を提供することができる。Further, by disposing a heat dissipation plate on the surface of the semiconductor element, it is possible to provide a mounting semiconductor device applicable to a large-capacity, high-speed device.
【図１】実施例１の実装用半導体装置の製造工程を示す
断面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing process of a mounting semiconductor device of Example 1.
【図２】実施例２の実装用半導体装置のバンプ配置を示
す模式断面図である。FIG. 2 is a schematic cross-sectional view illustrating a bump arrangement of a mounting semiconductor device according to a second embodiment.
【図３】実施例３の実装用半導体装置のバンプ配置を示
す模式断面図である。FIG. 3 is a schematic cross-sectional view illustrating a bump arrangement of a mounting semiconductor device according to a third embodiment.
【図４】実施例４の実装用半導体装置の製造工程の模式
断面図である。FIG. 4 is a schematic cross-sectional view of a manufacturing process of the mounting semiconductor device of Example 4.
【図５】実施例４の実装用半導体装置のプリント基板へ
の実装例を示す模式断面図である。FIG. 5 is a schematic cross-sectional view showing an example of mounting a mounting semiconductor device of Example 4 on a printed circuit board.
【図６】実施例５の実装用半導体装置の製造工程を示す
模式断面図である。FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the mounting semiconductor device of Example 5;
【図７】実施例６の実装用半導体装置の製造工程を示す
模式断面図である。FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the mounting semiconductor device of Example 6.
【図８】実施例７の実装用半導体装置のプリント基板へ
の実装例を示す模式断面図である。FIG. 8 is a schematic cross-sectional view showing an example of mounting a mounting semiconductor device of Example 7 on a printed circuit board.
【図９】実施例８の実装用半導体装置のプリント基板へ
の実装例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of mounting the mounting semiconductor device of Example 8 on a printed circuit board.
【図１０】実施例９の実装用マルチチップ半導体装置の
製造工程を示す模式断面図である。FIG. 10 is a schematic sectional view showing a manufacturing process of the mounting multi-chip semiconductor device of Example 9;
【図１１】従来の半導体装置とプリント基板への実装例
を示す模式断面図である。FIG. 11 is a schematic cross-sectional view showing an example of mounting on a conventional semiconductor device and a printed circuit board.
【図１２】他の従来の半導体装置とプリント基板への実
装例を示す模式断面図である。FIG. 12 is a schematic cross-sectional view showing another conventional semiconductor device and an example of mounting on a printed circuit board.
【図１３】従来のバンプを有する半導体装置とプリント
基板への実装例を示す模式断面図である。FIG. 13 is a schematic cross-sectional view showing a conventional semiconductor device having bumps and an example of mounting on a printed circuit board.
【図１４】従来のフリップチップ方式の半導体素子のプ
リント基板への実装例を示す模式断面図である。FIG. 14 is a schematic cross-sectional view showing an example of mounting a conventional flip-chip type semiconductor element on a printed circuit board.
１…リードフレーム、２…ダイパッド、３…半導体素
子、４…モールド金型、５…封止樹脂、６…はんだボー
ル、７…放熱プレート、８…半硬化状態の熱硬化性樹脂
層、９…プリント基板、１０…配線パターン、１１…加
圧用プレート、１２…完全硬化状態の樹脂層、１３…金
属キャップ、１４…液状封止樹脂、１５…液状の熱硬化
性樹脂層、１６…支持フィルム、１８…はんだボール挿
入用穴、１９…熱硬化性樹脂塗布フィルム、２１…熱可
塑性樹脂ラミネートフィルム、２２…熱可塑性樹脂、２
３…ボンディングワイヤ、２４…ボンディングパッド、
２５…接続はんだ、２６…接着テープ、２７…応力緩和
プレート、２８…注入樹脂。DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... Die pad, 3 ... Semiconductor element, 4 ... Mold, 5 ... Sealing resin, 6 ... Solder ball, 7 ... Heat dissipation plate, 8 ... Semi-cured thermosetting resin layer, 9 ... Printed circuit board, 10: wiring pattern, 11: pressure plate, 12: resin layer in a completely cured state, 13: metal cap, 14: liquid sealing resin, 15: liquid thermosetting resin layer, 16: support film, Reference numeral 18 denotes a hole for inserting a solder ball, 19 denotes a thermosetting resin applied film, 21 denotes a thermoplastic resin laminated film, 22 denotes a thermoplastic resin, 2
3 ... bonding wire, 24 ... bonding pad,
25: connection solder, 26: adhesive tape, 27: stress relaxation plate, 28: injected resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小角 博義 茨城県日立市大みか町七丁目１番１号 株式会社日立製作所 日立研究所内 (72)発明者 瀬川 正則 茨城県日立市大みか町七丁目１番１号 株式会社日立製作所 日立研究所内 (72)発明者 荻野 雅彦 茨城県日立市大みか町七丁目１番１号 株式会社日立製作所 日立研究所内 (72)発明者 服部 理恵 茨城県日立市大みか町七丁目１番１号 株式会社日立製作所 日立研究所内 (56)参考文献 特開 平３−16148（ＪＰ，Ａ) 特開 平３−177034（ＪＰ，Ａ) 特開 平５−63027（ＪＰ，Ａ) 特開 平３−12942（ＪＰ，Ａ) 特開 平６−342794（ＪＰ，Ａ) 特開 昭57−188852（ＪＰ，Ａ) 特開 平６−37127（ＪＰ，Ａ) 特開 平５−41407（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 - 23/31 H01L 21/56,21/60 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyoshi Osumi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Masanori Segawa 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Masahiko Ogino 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Rie Hattori 7, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1-1 Hitachi Research Laboratory, Hitachi Research Laboratory (56) References JP-A-3-16148 (JP, A) JP-A-3-177034 (JP, A) JP-A-5-63027 (JP, A) JP-A-3-12942 (JP, A) JP-A-6-342794 (JP, A) JP-A-57-188852 (JP, A) JP-A-6-37127 (JP, A) JP-A-5-188127 41407 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 23/28-23/31 H01L 21/56, 21/60
Claims (6)
はバンプを備えた半導体素子が樹脂封止されている半導
体装置であって、前記金属柱体またはバンプが形成され
ている面に、樹脂フィルムの両面にそれぞれの溶融温度
の異なる熱可塑性樹脂層を有する樹脂フィルム層が形成
されており、該樹脂フィルム層の厚さが、前記金属柱体
またはバンプの高さ以上の厚さに形成されていることを
特徴とする実装用半導体装置。1. A semiconductor device in which a semiconductor element having a metal column or bump for external connection on a surface on which an electrode is formed is resin-sealed. A resin film layer having a thermoplastic resin layer having a different melting temperature on each side of the resin film is formed, and the thickness of the resin film layer is formed to a thickness equal to or greater than the height of the metal pillar or the bump. A mounting semiconductor device characterized by being performed.
はバンプを備えた半導体素子が樹脂封止されている半導
体装置であって、前記金属柱体またはバンプが形成され
ている面に、樹脂フィルムの両面の少なくとも一方の面
に半硬化状態の熱硬化性樹脂層を有する樹脂フィルム層
が形成されており、該樹脂フィルム層の厚さが、前記金
属柱体またはバンプの高さ以上の厚さに形成されている
ことを特徴とする実装用半導体装置。2. A semiconductor device in which a semiconductor element having a metal column or a bump for external connection on a surface on which an electrode is formed is resin-sealed. A resin film layer having a thermosetting resin layer in a semi-cured state is formed on at least one surface of both surfaces of the resin film, and the thickness of the resin film layer is equal to or greater than the height of the metal pillar or bump. A mounting semiconductor device formed to have a thickness.
はバンプを備えた半導体素子が、前記金属柱体またはバ
ンプを露出させて樹脂封止されている半導体装置であっ
て、前記金属柱体またはバンプが形成されている封止樹
脂面に樹脂フィルムの両面にそれぞれの溶融温度の異な
る熱可塑性樹脂層を有する樹脂フィルムが形成されてお
り、該樹脂フィルム層の厚さが、前記金属柱体またはバ
ンプの高さ以上の厚さに形成されていることを特徴とす
る実装用半導体装置。3. A semiconductor device in which a semiconductor element having a metal column or bump for external connection on an electrode forming surface is resin-sealed by exposing the metal column or bump, and A resin film having thermoplastic resin layers having different melting temperatures on both surfaces of the resin film is formed on the sealing resin surface on which the body or bumps are formed, and the thickness of the resin film layer is the same as that of the metal column. A mounting semiconductor device formed to have a thickness equal to or greater than the height of a body or a bump.
度が２５０℃以上の樹脂フィルムから成る請求項１，２
または３に記載の実装用半導体装置。Wherein said resin film, according to claim 1 in which the glass transition temperature is formed of a resin film above 250 ° C.
Or mounting a semiconductor device according to 3.
はバンプを備えた半導体素子が前記金属柱体またはバン
プを露出させて樹脂封止されている半導体装置であっ
て、前記金属柱体またはバンプが形成されている封止樹
脂面に樹脂フィルムの両面に溶融温度の異なる熱可塑性
樹脂層を有する樹脂フィルム層を、前記金属柱体または
バンプの高さ以上の厚さに形成する工程、 プリント基板上に形成された所定の回路上に、前記半導
体装置の金属柱体またはバンプ形成面が接触するように
搭載，配置し、加圧しながら前記樹脂フィルム層の熱可
塑性樹脂層を所定温度で加熱溶融し、金属柱体またはバ
ンプを前記プリント基板面に密着させる工程、 加圧したままで前記金属柱体またはバンプのリフロー温
度に上昇させ、金属柱体またはバンプを一部溶融させる
ことにより前記プリント基板上の回路と電気的接続を行
う工程、 を含むことを特徴とする実装用半導体装置の実装方法。5. A semiconductor device in which a semiconductor element having a metal pillar or bump for external connection on an electrode forming surface is resin-sealed by exposing the metal pillar or bump, wherein the metal pillar is provided. Or forming a resin film layer having a thermoplastic resin layer having a different melting temperature on both surfaces of the resin film on the sealing resin surface on which the bumps are formed, to a thickness equal to or greater than the height of the metal pillars or bumps, The semiconductor device is mounted and arranged on a predetermined circuit formed on a printed circuit board such that the metal column or bump formation surface of the semiconductor device is in contact with the circuit, and the thermoplastic resin layer of the resin film layer is pressed at a predetermined temperature while pressing. Heating and melting the metal pillars or bumps to adhere to the surface of the printed circuit board; raising the metal pillars or bumps to the reflow temperature of the metal pillars or bumps while pressurizing the metal pillars or bumps; Implementation method of mounting a semiconductor device characterized by comprising the steps of performing circuit and electrical connections on the printed circuit board by melting.
はバンプを備えた半導体素子が前記金属柱体またはバン
プを露出させて樹脂封止されている半導体装置であっ
て、前記金属柱体またはバンプが形成されている封止樹
脂面に、樹脂フィルムの両面の少なくとも一方の面に半
硬化状態の熱硬化性樹脂層を有する樹脂フィルム層を、
前記金属柱体またはバンプの高さ以上の厚さに形成する
工程、 プリント基板上に形成された所定の回路上に、前記半導
体装置の金属柱体またはバンプ形成面が接触するように
搭載，配置し、加圧しながら前記樹脂フィルム層の樹脂
層を所定温度で加熱溶融または硬化し、金属柱体または
バンプを前記プリント基板面に密着させる工程、 加圧したままで前記金属柱体またはバンプのリフロー温
度に上昇させ、金属柱体またはバンプを一部溶融させる
ことにより前記プリント基板上の回路と電気的接続を行
う工程、 を含むことを特徴とする実装用半導体装置の実装方法。6. A semiconductor device in which a semiconductor element having a metal column or bump for external connection on an electrode forming surface is resin-sealed by exposing the metal column or bump, wherein the metal column is Or on the sealing resin surface on which the bumps are formed, a resin film layer having a thermosetting resin layer in a semi-cured state on at least one of both surfaces of the resin film,
Forming the metal pillars or bumps to a thickness equal to or greater than the height of the metal pillars or bumps; mounting and disposing the metal pillars or bumps on a predetermined circuit formed on a printed circuit board so that the metal pillars or bumps forming surface of the semiconductor device are in contact with the predetermined circuit. Heating and melting or curing the resin layer of the resin film layer at a predetermined temperature while applying pressure, and bringing the metal pillars or bumps into close contact with the printed circuit board surface; reflowing the metal pillars or bumps while keeping the pressure applied Raising the temperature to partially melt the metal pillars or bumps, thereby making electrical connection with the circuit on the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21173195A JP3205686B2 (en) | 1995-08-21 | 1995-08-21 | Semiconductor device for mounting and its mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21173195A JP3205686B2 (en) | 1995-08-21 | 1995-08-21 | Semiconductor device for mounting and its mounting method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001127903A Division JP2001313315A (en) | 2001-04-25 | 2001-04-25 | Semiconductor device for mounting and its mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0964237A JPH0964237A (en) | 1997-03-07 |
| JP3205686B2 true JP3205686B2 (en) | 2001-09-04 |
Family
ID=16610667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21173195A Expired - Fee Related JP3205686B2 (en) | 1995-08-21 | 1995-08-21 | Semiconductor device for mounting and its mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3205686B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6790473B2 (en) | 1995-10-26 | 2004-09-14 | International Business Machines Corporation | Lead protective coating composition, process and structure thereof |
| SG48462A1 (en) * | 1995-10-26 | 1998-04-17 | Ibm | Lead protective coating composition process and structure thereof |
| US6063646A (en) * | 1998-10-06 | 2000-05-16 | Japan Rec Co., Ltd. | Method for production of semiconductor package |
| JP3277996B2 (en) | 1999-06-07 | 2002-04-22 | 日本電気株式会社 | Circuit device and method of manufacturing the same |
| KR100862343B1 (en) * | 2007-05-29 | 2008-10-13 | 삼성전기주식회사 | Light emitting diode module for lighting and fabrication method thereof |
| JP2011091327A (en) * | 2009-10-26 | 2011-05-06 | Sharp Corp | Solar cell module and method of manufacturing solar cell module |
| JP5140133B2 (en) | 2010-10-29 | 2013-02-06 | シャープ株式会社 | Method for manufacturing solar cell with wiring sheet, method for manufacturing solar cell module, solar cell with wiring sheet and solar cell module |
| JP2012099853A (en) * | 2012-02-03 | 2012-05-24 | Sharp Corp | Manufacturing method of solar cell with wiring sheet, manufacturing method of solar cell module, solar cell with wiring sheet, and solar cell module |
| JP2012099854A (en) * | 2012-02-03 | 2012-05-24 | Sharp Corp | Manufacturing method of solar cell with wiring sheet, manufacturing method of solar cell module, solar cell with wiring sheet, and solar cell module |
| US10403594B2 (en) * | 2018-01-22 | 2019-09-03 | Toyota Motor Engineering & Manufacturing North America, Inc. | Hybrid bonding materials comprising ball grid arrays and metal inverse opal bonding layers, and power electronics assemblies incorporating the same |
| CN115050653B (en) * | 2022-08-16 | 2022-12-30 | 宁波芯健半导体有限公司 | Wafer level packaging method and system of SOI chip and storage medium |
-
1995
- 1995-08-21 JP JP21173195A patent/JP3205686B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0964237A (en) | 1997-03-07 |
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