JP2001135662A - Semiconductor element and method for manufacturing semiconductor device - Google Patents

Semiconductor element and method for manufacturing semiconductor device

Info

Publication number
JP2001135662A
JP2001135662A JP31365199A JP31365199A JP2001135662A JP 2001135662 A JP2001135662 A JP 2001135662A JP 31365199 A JP31365199 A JP 31365199A JP 31365199 A JP31365199 A JP 31365199A JP 2001135662 A JP2001135662 A JP 2001135662A
Authority
JP
Japan
Prior art keywords
resin film
conductive
semiconductor device
post
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31365199A
Other languages
Japanese (ja)
Inventor
Yoshitake Hayashi
林  祥剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31365199A priority Critical patent/JP2001135662A/en
Publication of JP2001135662A publication Critical patent/JP2001135662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element for flip-chip mounting which allows a small manufacturing cost and high reliability and productivity and a method for manufacturing a semiconductor device. SOLUTION: A semiconductor element 1 comprising a conductive post 4 formed in an I/O electrode terminal part 2 on the semiconductor element and a resin film 3 semi-hardened (B-staged) on the surface of the semiconductor element in the conductive post side is flip-chip mounted with face down on a circuit board by pressing and heat treating.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子構造お
よび半導体装置の製造方法に関し、特に、フリップチッ
プ実装用の半導体素子、およびその半導体素子を回路基
板上にフリップチップ実装する半導体装置の製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element structure and a method of manufacturing a semiconductor device, and more particularly to a semiconductor element for flip-chip mounting and a method of manufacturing a semiconductor device for mounting the semiconductor element on a circuit board by flip-chip mounting. It is about.

【0002】[0002]

【従来の技術】近年、携帯用電子機器等の小型化や高性
能化に伴い、半導体素子の集積度が高くなり、半導体装
置の小型化および接続端子間の狭ピッチ化が進んでい
る。このため、フリップチップ実装技術を用いた半導体
装置の開発が盛んに行われている。以下、前記フリップ
チップ実装技術を用いた従来の半導体装置の一例につい
て説明する。
2. Description of the Related Art In recent years, with the miniaturization and high performance of portable electronic devices and the like, the degree of integration of semiconductor elements has increased, and the miniaturization of semiconductor devices and the narrow pitch between connection terminals have been progressing. For this reason, development of semiconductor devices using flip-chip mounting technology has been actively conducted. Hereinafter, an example of a conventional semiconductor device using the flip chip mounting technique will be described.

【0003】従来、半導体実装技術としては、特開昭6
3−275127号公報に記載されたものが知られてい
る。
Conventionally, as a semiconductor mounting technology, Japanese Patent Application Laid-Open
The thing described in 3-275127 gazette is known.

【0004】図7および図8に、従来の半導体装置の製
造プロセスの一例を示す。
FIGS. 7 and 8 show an example of a conventional semiconductor device manufacturing process.

【0005】図7は、バンプ111が形成された半導体
素子101を異方導電性シート112が貼り付けられた
回路基板109上にフェースダウンにて実装した後、加
圧加熱ヘッド108にて加圧及び加熱処理を行う工程を
示し、この工程により、半導体素子101に設けたバン
プ111と回路基板109側の電極端子110とを電気
的に接合するとともに、異方導電性シート112を介し
て半導体素子101と回路基板109を接着して半導体
装置を完成させる。
FIG. 7 shows that the semiconductor element 101 on which the bumps 111 are formed is mounted face down on a circuit board 109 to which an anisotropic conductive sheet 112 is adhered, and then pressed by a pressure heating head 108. And a step of performing a heat treatment. In this step, the bumps 111 provided on the semiconductor element 101 are electrically connected to the electrode terminals 110 on the circuit board 109 side, and the semiconductor element is connected via the anisotropic conductive sheet 112. The semiconductor device is completed by bonding the substrate 101 and the circuit board 109.

【0006】図8は、バンプ111が形成された半導体
素子101を回路基板109上にフェースダウンにて実
装した後、半導体素子101と回路基板109の隙間に
封止材113を毛細管現象を利用して充填している工程
を示す。この工程の後、充填された封止材113を加熱
硬化して半導体装置を完成させる。
FIG. 8 shows that the semiconductor element 101 on which the bumps 111 are formed is mounted face down on a circuit board 109, and then a sealing material 113 is provided in a gap between the semiconductor element 101 and the circuit board 109 by utilizing a capillary phenomenon. This shows the filling process. After this step, the filled sealing material 113 is cured by heating to complete the semiconductor device.

【0007】[0007]

【発明が解決しようとする課題】図7に示す従来例で
は、予め回路基板109側に異方導電性シート112を
貼付しておく必要があることや、低熱膨張係数にするた
めに異方導電性シート112に含有させてあるシリカ等
の粒径が導電性粒子より大きい等の問題により、初期接
続状態や信頼性に課題を有している。
In the conventional example shown in FIG. 7, the anisotropic conductive sheet 112 needs to be pasted on the circuit board 109 side in advance, and the anisotropic conductive sheet 112 has a low thermal expansion coefficient. There is a problem in the initial connection state and reliability due to the problem that the particle size of silica or the like contained in the conductive sheet 112 is larger than the conductive particles.

【0008】製造コストについても、異方導電性シート
112が高価であることや、図7および図8に示す従来
例では共に、バンプ111をバンプボンダーにより個々
に形成する必要がある等の課題を有している。
[0008] The manufacturing cost is also disadvantageous in that the anisotropic conductive sheet 112 is expensive, and in the conventional examples shown in FIGS. 7 and 8, it is necessary to individually form the bumps 111 using a bump bonder. Have.

【0009】図8に示す従来例では、半導体素子サイズ
が10×10mm、半導体素子101と回路基板109
の隙間を0.05mm、封止材113を充填する際の基
板温度を40〜70℃、充填時の傾斜角度を15°と設
定した場合、封止材113の充填開始からフィレットが
形成されるまで3〜15分の時間を要し、封止材113
の加熱硬化に30〜400分もの時間を要するととも
に、製造設備として充填装置や硬化装置が必要となる。
In the conventional example shown in FIG. 8, the semiconductor element size is 10 × 10 mm, and the semiconductor element 101 and the circuit board 109 are mounted.
Is set to 0.05 mm, the substrate temperature when filling the sealing material 113 is set to 40 to 70 ° C., and the inclination angle at the time of filling is set to 15 °, a fillet is formed from the start of the filling of the sealing material 113. It takes 3 to 15 minutes until the sealing material 113
It takes 30 to 400 minutes to heat and cure, and a filling device and a curing device are required as manufacturing equipment.

【0010】したがって、本発明の目的は、製造コスト
が安く信頼性および生産性の高い、フリップチップ実装
用の半導体素子および半導体装置の製造方法を提供する
ことにある。
Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor element and a semiconductor device for flip-chip mounting, which has low manufacturing cost and high reliability and productivity.

【0011】[0011]

【課題を解決するための手段】前記の目的を達成するた
め、本発明の半導体素子は、回路基板上にフェースダウ
ンにてフリップチップ実装する半導体素子であって、前
記半導体素子の入出力電極端子部に形成した導電性ポス
トと、前記導電性ポストが形成された側の前記半導体素
子表面上に形成した半硬化(Bステージ化)させた樹脂
膜とを備えたことを特徴とする。
In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a semiconductor device which is flip-chip mounted face-down on a circuit board, and an input / output electrode terminal of the semiconductor device. And a semi-cured (B-staged) resin film formed on the surface of the semiconductor element on the side where the conductive posts are formed.

【0012】本発明の前記半導体素子において、前記樹
脂膜は、前記半導体素子を前記回路基板上に実装する際
に、前記半導体素子と前記回路基板との隙間を埋める封
止材であることが好ましい。
In the semiconductor element of the present invention, it is preferable that the resin film is a sealing material that fills a gap between the semiconductor element and the circuit board when mounting the semiconductor element on the circuit board. .

【0013】本発明の前記半導体素子において、前記樹
脂膜に無機絶縁物粒子を混合することが好ましい。
In the semiconductor device according to the present invention, it is preferable that inorganic insulating particles are mixed in the resin film.

【0014】また、本発明の前記半導体素子において、
前記樹脂膜は、感光性樹脂からなり、フォトリソグラフ
ィーによって、前記入出力電極端子部に対応する部分に
形成された開口部を有し、前記開口部に形成される前記
導電性ポストは、電気鍍金または無電解鍍金で形成され
た金属ポストであることが好ましい。
Further, in the semiconductor device of the present invention,
The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and the conductive post formed in the opening is formed by electroplating. Alternatively, the metal post is preferably formed by electroless plating.

【0015】また、本発明の前記半導体素子において、
前記樹脂膜は、感光性樹脂からなり、フォトリソグラフ
ィーによって、前記入出力電極端子部に対応する部分に
形成された開口部を有し、前記開口部に形成される前記
導電性ポストは、導電性粒子を含んだ樹脂で形成された
導電性樹脂ポストであることが好ましい。
In the semiconductor device according to the present invention,
The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and the conductive post formed in the opening has a conductive property. The conductive resin post is preferably formed of a resin containing particles.

【0016】また、本発明の前記半導体素子において、
前記樹脂膜は、感光性樹脂からなり、フォトリソグラフ
ィーによって、前記入出力電極端子部に対応する部分に
形成された開口部を有し、前記開口部に形成される前記
導電性ポストは、鍍金で形成された金属ポストと導電性
粒子を含んだ樹脂で形成された導電性樹脂ポストの2段
構造であることが好ましい。
In the semiconductor device of the present invention,
The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and the conductive post formed in the opening is formed by plating. It is preferable to have a two-stage structure of the formed metal post and a conductive resin post formed of a resin containing conductive particles.

【0017】さらに、本発明の前記半導体素子におい
て、前記導電性ポストは、感光性導電性樹脂からなる導
電性樹脂ポストを含むことが好ましい。
Further, in the semiconductor device according to the present invention, it is preferable that the conductive post includes a conductive resin post made of a photosensitive conductive resin.

【0018】前記の目的を達成するため、本発明の第1
の半導体装置の製造方法は、回路基板上に半導体素子を
フェースダウンにてフリップチップ実装する半導体装置
の製造方法であって、前記半導体素子が多数個形成され
たウェーハ上に感光性の樹脂膜を形成し、フォトリグラ
フィーにより、前記半導体素子上に設けられた入出力電
極端子部に対応する開口部を前記感光性樹脂膜に形成
し、前記形成された感光性樹脂膜をマスクとして、前記
感光性樹脂膜の開口部に対応した前記半導体素子の入出
力電極端子部に鍍金にて金属ポストを形成し、前記ウェ
ーハを分割して個別の半導体素子に分離し、前記個別の
半導体素子をフェースダウンにて、回路基板の所定の位
置に加圧及び加熱処理を行って実装することを特徴とす
る。
In order to achieve the above object, the first aspect of the present invention is described.
Is a method for manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Forming, by photolithography, forming openings in the photosensitive resin film corresponding to the input / output electrode terminal portions provided on the semiconductor element, and using the formed photosensitive resin film as a mask, A metal post is formed by plating on the input / output electrode terminal portion of the semiconductor element corresponding to the opening of the resin film, the wafer is divided and separated into individual semiconductor elements, and the individual semiconductor elements are face-down. And pressurizing and heating at a predetermined position on the circuit board for mounting.

【0019】前記の目的を達成するため、本発明の第2
の半導体装置の製造方法は、回路基板上に半導体素子を
フェースダウンにてフリップチップ実装する半導体装置
の製造方法であって、前記半導体素子が多数個形成され
たウェーハ上に感光性の樹脂膜を形成し、フォトリグラ
フィーにより、前記半導体素子上に設けられた入出力電
極端子部に対応する開口部を前記感光性樹脂膜に形成
し、前記感光性樹脂膜の開口部に対応した前記半導体素
子の入出力電極端子部に導電性樹脂ポストを形成し、前
記ウェーハを分割して個別の半導体素子に分離し、前記
個別の半導体素子をフェースダウンにて、回路基板の所
定の位置に加圧及び加熱処理を行って実装することを特
徴とする。
In order to achieve the above object, the second aspect of the present invention
Is a method for manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Forming, by photolithography, forming openings in the photosensitive resin film corresponding to the input / output electrode terminals provided on the semiconductor element, and forming the openings of the semiconductor element corresponding to the openings in the photosensitive resin film. A conductive resin post is formed at the input / output electrode terminal, the wafer is divided into individual semiconductor elements, and the individual semiconductor elements are pressed down and heated at predetermined positions on a circuit board face down. It is characterized by processing and implementation.

【0020】前記の目的を達成するため、本発明の第3
の半導体装置の製造方法は、回路基板上に半導体素子を
フェースダウンにてフリップチップ実装する半導体装置
の製造方法であって、前記半導体素子が多数個形成され
たウェーハ上に感光性の樹脂膜を形成し、フォトリグラ
フィーにより、前記半導体素子上に設けられた入出力電
極端子部に対応する開口部を前記感光性樹脂膜に形成
し、前記感光性樹脂膜の開口部に対応した前記半導体素
子の入出力電極端子部に、第1層として鍍金にて金属ポ
ストを形成した後、その上に第2層として導電性樹脂ポ
ストを形成することにより、2層構造の導電性ポストを
形成し、前記ウェーハを分割して個別の半導体素子に分
離し、前記半導体素子をフェースダウンにて、回路基板
の所定の位置に加圧及び加熱処理を行って実装すること
を特徴とする。
In order to achieve the above object, a third aspect of the present invention is provided.
Is a method for manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Forming, by photolithography, forming openings in the photosensitive resin film corresponding to the input / output electrode terminals provided on the semiconductor element, and forming the openings of the semiconductor element corresponding to the openings in the photosensitive resin film. A metal post is formed as a first layer on the input / output electrode terminal portion by plating, and a conductive resin post is formed thereon as a second layer, thereby forming a conductive post having a two-layer structure. The wafer is divided into individual semiconductor elements, and the semiconductor elements are mounted face down in a predetermined position on a circuit board by applying pressure and heat.

【0021】前記第2及び第3の半導体装置の製造方法
において、前記導電性樹脂ポストは、導電性ペーストを
印刷充填して形成することが好ましい。
In the second and third methods of manufacturing a semiconductor device, the conductive resin post is preferably formed by printing and filling a conductive paste.

【0022】前記第2及び第3の半導体装置の製造方法
において、前記導電性ポストは、感光性の導電性樹脂を
フォトリソ加工によりパターン形成することが好まし
い。
In the second and third methods of manufacturing a semiconductor device, it is preferable that the conductive post is formed by patterning a photosensitive conductive resin by photolithography.

【0023】前記第1から第3の半導体装置の製造方法
において、前記感光性樹脂膜は、半硬化(Bステージ
化)させた樹脂膜であることが好ましい。
In the first to third methods of manufacturing a semiconductor device, the photosensitive resin film is preferably a semi-cured (B-staged) resin film.

【0024】この構成において、前記Bステージ化させ
た樹脂膜は、酸無水物系またはフェノール系のエポキシ
樹脂を主体として構成されることが好ましい。
In this configuration, it is preferable that the B-staged resin film is mainly composed of an acid anhydride-based or phenol-based epoxy resin.

【0025】前記の目的を達成するため、本発明の第4
の半導体装置の製造方法は、回路基板上に半導体素子を
フェースダウンにてフリップチップ実装する半導体装置
の製造方法であって、前記半導体素子が多数個形成され
たウェーハ上の入出力電極端子部に突起電極を形成し、
前記ウェーハ上に半硬化(Bステージ化)させた樹脂膜
を形成し、前記ウェーハを分割して個別の半導体素子に
分離し、前記半導体素子をフェースダウンにて、回路基
板の所定の位置に加圧及び加熱処理を行って実装するこ
とを特徴とする。
In order to achieve the above object, the fourth aspect of the present invention
Is a method of manufacturing a semiconductor device in which a semiconductor element is flip-chip mounted face-down on a circuit board, and the semiconductor element is provided on an input / output electrode terminal portion on a wafer on which a large number of the semiconductor elements are formed. Forming protruding electrodes,
A semi-cured (B-stage) resin film is formed on the wafer, the wafer is divided and separated into individual semiconductor elements, and the semiconductor elements are applied face-down to predetermined positions on a circuit board. It is characterized by mounting by performing pressure and heat treatment.

【0026】上記の構成および方法によれば、半導体素
子を回路基板側に実装する際または実装した後に加圧及
び加熱処理することで、半導体素子表面のBステージ化
させた樹脂膜が、一旦軟化した後再び硬化して接着する
ため、半導体素子と回路基板の隙間を埋める封止材とし
て機能する。したがって、従来のような、封止材の充填
工程あるいは異方導電性フィルムの貼付工程を無くすこ
とができ、作業性が大幅に向上する。
According to the above configuration and method, when the semiconductor element is mounted on the circuit board side or after the mounting, pressure and heat treatment are performed, so that the B-staged resin film on the semiconductor element surface is once softened. After that, it is cured and adhered again, so that it functions as a sealing material for filling the gap between the semiconductor element and the circuit board. Therefore, the step of filling the sealing material or the step of attaching the anisotropic conductive film as in the related art can be eliminated, and the workability is greatly improved.

【0027】また、従来半導体実装工程で行っていた、
バンプ形成や封止材充填といた工程を、半導体素子製造
プロセス中において、封止材となる樹脂膜と導電性ポス
ト(バンプ)を一括形成できるため、生産性を向上させ
ることができ、半導体装置を低コストで製造することが
可能となる。
In addition, conventionally, it has been performed in a semiconductor mounting process.
In the process of forming a bump and filling a sealing material, a resin film serving as a sealing material and conductive posts (bumps) can be collectively formed in a semiconductor element manufacturing process, so that productivity can be improved and a semiconductor device can be improved. Can be manufactured at low cost.

【0028】さらに、従来の異方導電性フィルムを用い
た場合の欠点である、無機物充填材(SiO2等)が導
電性ポストと回路基板側電極との間に入り込んで、電気
的接合を阻害するといったことは大幅に減少し、信頼性
が大幅に向上する。
Further, an inorganic filler (such as SiO 2 ), which is a drawback when using the conventional anisotropic conductive film, enters between the conductive post and the electrode on the circuit board side, and hinders electrical connection. Is greatly reduced and reliability is greatly improved.

【0029】[0029]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面に基づいて説明する。但し、本発明は、以下に
具体的に示す実施形態に限定されるものではない。
Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments specifically described below.

【0030】(第1の実施形態)本発明の第1の実施形
態による半導体素子および半導体装置の製造方法につい
て、図1、図2および図5に基づき、以下に説明する。
(First Embodiment) A method for fabricating a semiconductor device and a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS.

【0031】図1は、本発明の第1の実施形態による半
導体素子の構成を示す断面図である。図2は図1の部分
拡大図である。図5は半導体装置の製造プロセス図であ
る。なお、図1、図2および図5において、同一部分に
は同一符号を付している。
FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a partially enlarged view of FIG. FIG. 5 is a manufacturing process diagram of the semiconductor device. 1, 2, and 5, the same portions are denoted by the same reference numerals.

【0032】図示のように、この半導体素子1は、入出
力電極端子2の部分を除いて半硬化(以降、Bステージ
化と称する)させた樹脂膜3を有し、Bステージ化させ
た樹脂膜3の開口部に、導電性ポスト4(図1)とし
て、鍍金による金属ポスト5(図2)が構成されてい
る。
As shown in the figure, the semiconductor element 1 has a resin film 3 which has been semi-cured (hereinafter referred to as B-stage) except for the input / output electrode terminals 2, and has a B-stage resin. In the opening of the film 3, a metal post 5 (FIG. 2) is formed by plating as a conductive post 4 (FIG. 1).

【0033】以上のように構成された半導体素子を用い
た半導体装置は、例えば図5(a)〜図5(f)に示す
ようにして製造できる。
A semiconductor device using the semiconductor element configured as described above can be manufactured, for example, as shown in FIGS. 5 (a) to 5 (f).

【0034】まず、図5(a)に示すウェーハ上に多数
形成された半導体素子1(図5では1素子のみ示す)の
表面に、樹脂膜3として、例えば感光性エポキシ樹脂を
塗布形成して、プリベークを行いBステージ化させた後
(図5(b))、露光、現像処理により、半導体素子1
の入出力電極端子部2に対応して樹脂膜3に開口部7を
形成する(図5(c))。Bステージ化させた樹脂膜を
マスクとして、開口部7に電気鍍金または無電解鍍金に
よって金属ポスト5を形成する(図5(d))。感光性
の樹脂膜3を構成する樹脂としては、カチオン系、酸無
水物系またはフェノール系のエポキシ樹脂、BT樹脂、
シリコーン樹脂等が使用でき、特に好ましくは、熱硬化
性エポキシ樹脂である。なお、樹脂は、一種類とは限ら
ず、二種類以上を併用して樹脂膜3を形成してもよい。
First, for example, a photosensitive epoxy resin is applied and formed as a resin film 3 on the surface of the semiconductor elements 1 (only one element is shown in FIG. 5) formed on a large number of wafers shown in FIG. After pre-baking to form a B stage (FIG. 5 (b)), the semiconductor element 1 is exposed and developed.
An opening 7 is formed in the resin film 3 corresponding to the input / output electrode terminal 2 (FIG. 5C). Using the B-staged resin film as a mask, a metal post 5 is formed in the opening 7 by electroplating or electroless plating (FIG. 5D). Examples of the resin constituting the photosensitive resin film 3 include cationic, acid anhydride or phenolic epoxy resins, BT resins,
A silicone resin or the like can be used, and a thermosetting epoxy resin is particularly preferable. The resin is not limited to one type, and the resin film 3 may be formed by using two or more types in combination.

【0035】金属ポスト5としては、例えば、Au、C
u、Pd、Ni、Sn、In等の導電性金属が使用でき
る。電気鍍金を行う場合の共通電極としては、半導体素
子間の切断スペースに共通バイアス電極ライン(図示せ
ず)を設け、そこから半導体素子1の入出力電極端子2
に接続する等の方法がある。
As the metal post 5, for example, Au, C
A conductive metal such as u, Pd, Ni, Sn, and In can be used. As a common electrode when performing electroplating, a common bias electrode line (not shown) is provided in a cutting space between the semiconductor elements, and an input / output electrode terminal 2 of the semiconductor element 1 is provided therefrom.
There is a method such as connection to the Internet.

【0036】次に、ウェーハを分割して半導体素子1を
個別に切り出し、図5(e)に示すように、半導体素子
をフェースダウンにて加圧加熱ヘッド8面に吸着保持さ
せた後、半導体素子1に形成された金属ポスト5と、回
路基板側端子10との位置合わせを行い回路基板9の上
に配置する。この状態で加圧加熱ヘッド8に圧力と熱を
加えることにより、Bステージ化させた樹脂3が軟化し
て回路基板9と接着結合される。これにより、半導体素
子1の入出力電極端子2と回路基板側端子10は、金属
ポスト5を介して電気的に接続される。この処理条件
は、半導体素子1の大きさやBステージ化させた樹脂膜
3の特性等により適宜決定されるが、通常、圧力9.8
×104〜490×104Pa、温度150〜350℃、
時間1〜60秒である。
Next, the wafer is divided and the semiconductor elements 1 are individually cut out. As shown in FIG. 5 (e), the semiconductor elements are sucked and held face down on the surface of the pressurizing and heating head 8, and The metal posts 5 formed on the element 1 are aligned with the circuit board side terminals 10 and arranged on the circuit board 9. By applying pressure and heat to the pressurizing and heating head 8 in this state, the B-staged resin 3 is softened and bonded to the circuit board 9. Thus, the input / output electrode terminal 2 of the semiconductor element 1 and the circuit board side terminal 10 are electrically connected via the metal post 5. The processing conditions are appropriately determined depending on the size of the semiconductor element 1 and the characteristics of the resin film 3 which has been B-staged.
× 10 4 to 490 × 10 4 Pa, temperature 150 to 350 ° C.,
The time is 1 to 60 seconds.

【0037】以上のようにして、本実施形態の半導体素
子および半導体装置が製造できる。
As described above, the semiconductor element and the semiconductor device of this embodiment can be manufactured.

【0038】なお、導電性ポスト4として鍍金形成され
る金属ポスト5の高さは、図示ではBステージ化させた
樹脂膜厚と同じであるが、導電性ポスト4の材質や樹脂
膜3の材料特性によって、異なることがあっても問題は
ない。
The height of the metal post 5 formed by plating as the conductive post 4 is the same as the resin film thickness formed in the B stage in the drawing, but the material of the conductive post 4 and the material of the resin film 3 are shown. There is no problem if the characteristics are different.

【0039】(第2の実施形態)本実施形態による半導
体素子および半導体装置の製造方法について、図3に基
づいて説明する。図3は、本発明の第2の実施形態によ
る半導体素子の部分断面図である。
(Second Embodiment) The method for fabricating the semiconductor element and the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 3 is a partial sectional view of a semiconductor device according to a second embodiment of the present invention.

【0040】図示のように、この半導体素子1の表面上
には、入出力電極端子2の部分を除いてBステージ化さ
せた樹脂膜3が形成されている。前記Bステージ化させ
た樹脂膜3の開口部7(図5(c))に導電性樹脂ポス
ト6が構成されている。
As shown in the figure, on the surface of the semiconductor element 1, a resin film 3 which is B-staged except for the portion of the input / output electrode terminal 2 is formed. A conductive resin post 6 is formed in the opening 7 (FIG. 5C) of the B-staged resin film 3.

【0041】以上のように構成された半導体素子を用い
た半導体装置は、例えば以下のように製造できる。第1
の実施形態と同様に、半導体素子1上に、開口部7を有
したBステージ化させた樹脂膜3を形成する。導電性樹
脂ポスト6の形成する方法としては、例えば、樹脂膜3
をマスクとして導電性樹脂ペーストを印刷または転写す
ることによって、開口部7に導電性樹脂ペーストを充填
した後に加熱硬化または乾燥する方法がある。導電性樹
脂ペーストとしては、樹脂バインダーにAg、Cu、A
gPd、Au、AgPt、Pd、Ni等の導電性金属材
料、または前記金属類でコーティング処理した樹脂粉材
料等を添加している。樹脂バインダーとしては、熱硬化
性および熱可塑性の何れを用いても問題はない。
A semiconductor device using the semiconductor element configured as described above can be manufactured, for example, as follows. First
As in the first embodiment, the B-staged resin film 3 having the opening 7 is formed on the semiconductor element 1. As a method of forming the conductive resin post 6, for example, the resin film 3
There is a method of printing or transferring a conductive resin paste using as a mask, filling the opening 7 with the conductive resin paste, and then heating or curing the paste. As the conductive resin paste, Ag, Cu, A
A conductive metal material such as gPd, Au, AgPt, Pd, and Ni, or a resin powder material coated with the metal is added. There is no problem in using either thermosetting or thermoplastic as the resin binder.

【0042】導電性樹脂ポスト6の形成方法として、感
光性導電性樹脂およびフォトリソグラフィー技術を用い
て、Bステージ化させた樹脂膜3の開口部7にパターン
形成してもよい。
As a method of forming the conductive resin post 6, a pattern may be formed in the opening 7 of the B-staged resin film 3 by using a photosensitive conductive resin and a photolithography technique.

【0043】以上のようにして製造された半導体素子1
を、第1の実施形態と同様の方法にて回路基板9上に実
装する。
The semiconductor device 1 manufactured as described above
Is mounted on the circuit board 9 in the same manner as in the first embodiment.

【0044】(第3の実施形態)本実施形態による半導
体素子および半導体装置の製造方法について、図4に基
づいて説明する。図4は、本発明の第3の実施形態によ
る半導体素子の部分断面図である。
(Third Embodiment) The method for fabricating the semiconductor element and the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 4 is a partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

【0045】図示のように、この半導体素子1の表面上
には、入出力電極端子2の部分を除いてBステージ化さ
せた樹脂膜3が形成され、この樹脂膜3の開口部7(図
5(c))に、鍍金による金属ポスト5と導電性樹脂ポ
スト6が構成されている。
As shown in the figure, on the surface of the semiconductor element 1, a resin film 3 which is B-staged except for the portion of the input / output electrode terminal 2 is formed, and an opening 7 (see FIG. 5 (c)), a metal post 5 and a conductive resin post 6 are formed by plating.

【0046】以上のように構成された半導体素子を用い
た半導体装置は、例えば以下のように製造できる。第1
の実施形態と同様に、半導体素子1上に、開口部を有し
たBステージ化させた樹脂膜3を形成した後、鍍金によ
り金属ポスト5を樹脂膜3の膜厚より薄く形成し、残り
の部分に第2の実施形態の方法を用いて、導電性樹脂ポ
スト6を形成して、2段構造の導電性ポストを形成す
る。
A semiconductor device using the semiconductor element configured as described above can be manufactured, for example, as follows. First
Similarly to the embodiment, after forming the B-staged resin film 3 having an opening on the semiconductor element 1, the metal post 5 is formed to be thinner than the resin film 3 by plating, and the remaining metal post 5 is formed. The conductive resin post 6 is formed on the portion by using the method of the second embodiment to form a conductive post having a two-stage structure.

【0047】以上のようにして製造された半導体素子1
を、第1の実施形態と同様の方法にて回路基板9上に実
装する。
The semiconductor device 1 manufactured as described above
Is mounted on the circuit board 9 in the same manner as in the first embodiment.

【0048】(第4の実施形態)本実施形態による半導
体装置の製造方法について、図6に基づいて説明する。
図6は、本発明の第4の実施形態による半導体装置の製
造プロセス図である。
(Fourth Embodiment) The method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIG.
FIG. 6 is a manufacturing process diagram of the semiconductor device according to the fourth embodiment of the present invention.

【0049】図示のように、ウェーハ上に多数個形成さ
れた半導体素子1の入出力電極端子2上に、例えばバン
プボンダーや鍍金等によってバンプ11(導電性ポス
ト)を形成し(図6(a))、前記半導体素子1の全面
に封止材となる樹脂膜12を塗布し、プリベークを行い
樹脂膜12をBステージ化させる(図6(b))。
As shown in the figure, bumps 11 (conductive posts) are formed on input / output electrode terminals 2 of a large number of semiconductor elements 1 formed on a wafer by, for example, a bump bonder or plating (FIG. 6 (a)). )), A resin film 12 serving as a sealing material is applied to the entire surface of the semiconductor element 1, and prebaked to make the resin film 12 into the B stage (FIG. 6B).

【0050】次に、第1の実施形態と同様に、ウェーハ
を分割して半導体素子1を個別に切り出し、半導体素子
1をフェースダウンにて加圧加熱ヘッド8面に吸着保持
させた後、半導体素子1に形成されたバンプ11と、回
路基板側端子10との位置合わせを行い回路基板9の上
に配置する。この状態で加圧加熱ヘッド8に圧力と熱を
加えることにより、Bステージ化させた樹脂膜3が軟化
して回路基板9と接着結合される。半導体素子1の入出
力電極端子2と回路基板側端子10とは、バンプ11を
介して電気的に接続される。
Next, similarly to the first embodiment, the wafer is divided and the semiconductor elements 1 are individually cut out, and the semiconductor elements 1 are sucked and held face-down on the surface of the pressure heating head 8. The bumps 11 formed on the element 1 are aligned with the circuit board side terminals 10 and are arranged on the circuit board 9. By applying pressure and heat to the pressure heating head 8 in this state, the B-staged resin film 3 is softened and adhesively bonded to the circuit board 9. The input / output electrode terminal 2 of the semiconductor element 1 and the circuit board side terminal 10 are electrically connected via a bump 11.

【0051】バンプ11は、Bステージ化させた樹脂膜
3の厚みと同等以上の高さであることが好ましく、樹脂
膜3を形成した後、バンプ11の先端を研磨して平坦化
させてもよい。
It is preferable that the height of the bump 11 is equal to or greater than the thickness of the resin film 3 which has been made into the B-stage. Even after the resin film 3 is formed, the tip of the bump 11 may be polished and flattened. Good.

【0052】[0052]

【発明の効果】以上のように、本発明の半導体素子およ
び半導体装置の製造方法によれば、予め、Bステージ化
させた樹脂膜を半導体素子表面に形成することにより、
半導体素子を回路基板に実装する際に、加圧および加熱
を行うことによって半導体素子と回路基板を接着結合で
きる。これにより、従来の封止材充填工程あるいは異方
導電性フィルム貼付工程を無くすることができ作業性が
大幅に向上する。
As described above, according to the method of manufacturing a semiconductor element and a semiconductor device of the present invention, a resin film which has been B-staged is formed on the surface of the semiconductor element in advance.
When the semiconductor element is mounted on the circuit board, the semiconductor element and the circuit board can be adhesively bonded by applying pressure and heating. Thereby, the conventional sealing material filling step or the anisotropic conductive film sticking step can be eliminated, and workability is greatly improved.

【0053】また、従来は、半導体実装工程で行ってい
たバンプ形成や封止材充填といた工程を、半導体素子製
造プロセス中において、半導体素子表面に形成したBス
テージ化させた樹脂膜をマスクとして、金属鍍金や導電
性樹脂膜の印刷や転写あるいはフォトリソ等により導電
性ポストを形成し、または、導電性ポスト(バンプ)を
先に形成した後、Bステージ化させた樹脂膜を形成する
ことで、封止材となる樹脂膜と導電性ポスト(バンプ)
をウェーハ上に容易に一括形成できるため、生産性を向
上させることができ、半導体装置を低コストで製造する
ことが可能となる。
Further, the steps of forming a bump and filling a sealing material, which were conventionally performed in the semiconductor mounting step, are replaced by a B-staged resin film formed on the surface of the semiconductor element as a mask during the semiconductor element manufacturing process. By forming a conductive post by metal plating, printing or transfer of a conductive resin film or photolithography, or by forming a conductive post (bump) first and then forming a B-staged resin film. , Resin film and conductive post (bump) as sealing material
Can be easily and collectively formed on a wafer, so that productivity can be improved and a semiconductor device can be manufactured at low cost.

【0054】さらに、異方導電性フィルムを用いた場合
の欠点である、無機物充填材(SiO2等)が導電性ポ
ストと回路基板側電極との間に入り込んで、電気的接合
を阻害するといったことは大幅に減少し、信頼性が大幅
に向上する。
Furthermore, a drawback of using an anisotropic conductive film is that an inorganic filler (such as SiO 2 ) enters between the conductive post and the electrode on the circuit board side to hinder electrical connection. Is greatly reduced and reliability is greatly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の半導体素子の構成を示す断面図FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device of the present invention.

【図2】 本発明の第1の実施形態による半導体素子の
構造を示す部分断面図
FIG. 2 is a partial sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention;

【図3】 本発明の第2の実施形態による半導体素子の
構造を示す部分断面図
FIG. 3 is a partial sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

【図4】 本発明の第3の実施形態による半導体素子の
構造を示す部分断面図
FIG. 4 is a partial sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention;

【図5】 本発明の第1から第3の実施形態による半導
体素子を用いた半導体装置の製造方法を示す工程図
FIG. 5 is a process chart showing a method for manufacturing a semiconductor device using the semiconductor element according to the first to third embodiments of the present invention;

【図6】 本発明の第4の実施形態による半導体素子を
用いた半導体装置の製造方法を示す工程図
FIG. 6 is a process chart showing a method for manufacturing a semiconductor device using a semiconductor element according to a fourth embodiment of the present invention;

【図7】 従来例による半導体装置の製造方法を示す部
分工程図
FIG. 7 is a partial process view showing a method for manufacturing a semiconductor device according to a conventional example.

【図8】 他の従来例による半導体装置の製造方法を示
す部分工程図
FIG. 8 is a partial process chart showing a method for manufacturing a semiconductor device according to another conventional example.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 入出力電極端子 3、12 樹脂膜 4 導電性ポスト 5 金属ポスト 6 導電性樹脂ポスト 7 開口部 8 加圧加熱ヘッド 9 回路基板 10 回路基板側端子 11 バンプ REFERENCE SIGNS LIST 1 semiconductor element 2 input / output electrode terminal 3, 12 resin film 4 conductive post 5 metal post 6 conductive resin post 7 opening 8 pressure heating head 9 circuit board 10 circuit board side terminal 11 bump

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/92 603C 604B 604E 23/12 L ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/92 603C 604B 604E 23/12 L

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】 回路基板上にフェースダウンにてフリッ
プチップ実装する半導体素子であって、 前記半導体素子の入出力電極端子部に形成した導電性ポ
ストと、 前記導電性ポストが形成された側の前記半導体素子表面
上に形成した半硬化(Bステージ化)させた樹脂膜とを
備えたことを特徴とする半導体素子。
1. A semiconductor element to be flip-chip mounted face-down on a circuit board, comprising: a conductive post formed on an input / output electrode terminal of the semiconductor element; and a conductive post formed on a side on which the conductive post is formed. A semi-cured (B-staged) resin film formed on the surface of the semiconductor element.
【請求項2】 前記樹脂膜は、前記半導体素子を前記回
路基板上に実装する際に、前記半導体素子と前記回路基
板との隙間を埋める封止材である請求項1記載の半導体
素子。
2. The semiconductor element according to claim 1, wherein the resin film is a sealing material that fills a gap between the semiconductor element and the circuit board when mounting the semiconductor element on the circuit board.
【請求項3】 前記樹脂膜に無機絶縁物粒子を混合した
請求項1または2記載の半導体素子。
3. The semiconductor device according to claim 1, wherein said resin film is mixed with inorganic insulating particles.
【請求項4】 前記樹脂膜は、感光性樹脂からなり、フ
ォトリソグラフィーによって、前記入出力電極端子部に
対応する部分に形成された開口部を有し、前記開口部に
形成される前記導電性ポストは、鍍金で形成された金属
ポストである請求項1から3のいずれか一項記載の半導
体素子。
4. The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and has a conductive film formed in the opening. The semiconductor device according to claim 1, wherein the post is a metal post formed by plating.
【請求項5】 前記樹脂膜は、感光性樹脂からなり、フ
ォトリソグラフィーによって、前記入出力電極端子部に
対応する部分に形成された開口部を有し、前記開口部に
形成される前記導電性ポストは、導電性粒子を含んだ樹
脂で形成された導電性樹脂ポストである請求項1から3
のいずれか一項記載の半導体素子。
5. The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and has the conductive film formed in the opening. The post is a conductive resin post formed of a resin containing conductive particles.
The semiconductor device according to any one of the above.
【請求項6】 前記樹脂膜は、感光性樹脂からなり、フ
ォトリソグラフィーによって、前記入出力電極端子部に
対応する部分に形成された開口部を有し、前記開口部に
形成される前記導電性ポストは、鍍金で形成された金属
ポストと導電性粒子を含んだ樹脂で形成された導電性樹
脂ポストの2段構造である請求項1から3のいずれか一
項記載の半導体素子。
6. The resin film is made of a photosensitive resin, has an opening formed in a portion corresponding to the input / output electrode terminal portion by photolithography, and has a conductive film formed in the opening. 4. The semiconductor device according to claim 1, wherein the post has a two-stage structure of a metal post formed by plating and a conductive resin post formed of a resin containing conductive particles.
【請求項7】 前記導電性ポストは、感光性導電性樹脂
からなる導電性樹脂ポストを含む請求項1から3、5、
および6のいずれか一項記載の半導体素子。
7. The method according to claim 1, wherein the conductive post includes a conductive resin post made of a photosensitive conductive resin.
The semiconductor device according to any one of claims 6 and 7.
【請求項8】 回路基板上に半導体素子をフェースダウ
ンにてフリップチップ実装する半導体装置の製造方法に
おいて、 前記半導体素子が多数個形成されたウェーハ上に感光性
の樹脂膜を形成し、 フォトリグラフィーにより、前記半導体素子上に設けら
れた入出力電極端子部に対応する開口部を前記感光性樹
脂膜に形成し、 前記形成された感光性樹脂膜をマスクとして、前記感光
性樹脂膜の開口部に対応した前記半導体素子の入出力電
極端子部に鍍金にて金属ポストを形成し、 前記ウェーハを分割して個別の半導体素子に分離し、 前記個別の半導体素子をフェースダウンにて、回路基板
の所定の位置に加圧及び加熱処理を行って実装すること
を特徴とする半導体装置の製造方法。
8. A method for manufacturing a semiconductor device in which a semiconductor element is flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Thus, an opening corresponding to the input / output electrode terminal provided on the semiconductor element is formed in the photosensitive resin film, and the opening of the photosensitive resin film is formed using the formed photosensitive resin film as a mask. Forming metal posts by plating on the input / output electrode terminals of the semiconductor elements corresponding to the above, dividing the wafer into individual semiconductor elements, and face-down the individual semiconductor elements to form a circuit board. A method for manufacturing a semiconductor device, comprising: performing mounting by applying pressure and heat to a predetermined position.
【請求項9】 回路基板上に半導体素子をフェースダウ
ンにてフリップチップ実装する半導体装置の製造方法に
おいて、 前記半導体素子が多数個形成されたウェーハ上に感光性
の樹脂膜を形成し、 フォトリグラフィーにより、前記半導体素子上に設けら
れた入出力電極端子部に対応する開口部を前記感光性樹
脂膜に形成し、 前記感光性樹脂膜の開口部に対応した前記半導体素子の
入出力電極端子部に導電性樹脂ポストを形成し、 前記ウェーハを分割して個別の半導体素子に分離し、 前記個別の半導体素子をフェースダウンにて、回路基板
の所定の位置に加圧及び加熱処理を行って実装すること
を特徴とする半導体装置の製造方法。
9. A method of manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Accordingly, an opening corresponding to the input / output electrode terminal provided on the semiconductor element is formed in the photosensitive resin film, and the input / output electrode terminal of the semiconductor element corresponding to the opening of the photosensitive resin film. Forming a conductive resin post on the substrate, dividing the wafer into individual semiconductor elements, and mounting the individual semiconductor elements by applying pressure and heat to predetermined positions on a circuit board face down. A method of manufacturing a semiconductor device.
【請求項10】 回路基板上に半導体素子をフェースダ
ウンにてフリップチップ実装する半導体装置の製造方法
において、 前記半導体素子が多数個形成されたウェーハ上に感光性
の樹脂膜を形成し、 フォトリグラフィーにより、前記半導体素子上に設けら
れた入出力電極端子部に対応する開口部を前記感光性樹
脂膜に形成し、 前記感光性樹脂膜の開口部に対応した前記半導体素子の
入出力電極端子部に、第1層として鍍金にて金属ポスト
を形成した後、その上に第2層として導電性樹脂ポスト
を形成することにより、2層構造の導電性ポストを形成
し、 前記ウェーハを分割して個別の半導体素子に分離し、 前記半導体素子をフェースダウンにて、回路基板の所定
の位置に加圧及び加熱処理を行って実装することを特徴
とする半導体装置の製造方法。
10. A method of manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a photosensitive resin film is formed on a wafer on which a large number of the semiconductor elements are formed. Accordingly, an opening corresponding to the input / output electrode terminal provided on the semiconductor element is formed in the photosensitive resin film, and the input / output electrode terminal of the semiconductor element corresponding to the opening of the photosensitive resin film. After forming a metal post by plating as a first layer, a conductive resin post is formed thereon as a second layer, thereby forming a conductive post having a two-layer structure, and dividing the wafer. Manufacturing a semiconductor device, wherein the semiconductor device is separated into individual semiconductor elements, and the semiconductor elements are mounted face to face at predetermined positions on a circuit board by applying pressure and heat. Method.
【請求項11】 前記導電性樹脂ポストは、導電性ペー
ストを印刷充填して形成する請求項9または10記載の
半導体装置の製造方法。
11. The method according to claim 9, wherein the conductive resin post is formed by printing and filling a conductive paste.
【請求項12】 前記導電性ポストは、感光性の導電性
樹脂をフォトリソ加工によりパターン形成する請求項9
または10記載の半導体装置の製造方法
12. The conductive post is formed by patterning a photosensitive conductive resin by photolithography.
Or the method of manufacturing a semiconductor device according to item 10.
【請求項13】 前記感光性樹脂膜は、半硬化(Bステ
ージ化)させた樹脂膜である請求項8から12のいずれ
か一項記載の半導体装置の製造方法。
13. The method of manufacturing a semiconductor device according to claim 8, wherein the photosensitive resin film is a semi-cured (B-staged) resin film.
【請求項14】 前記Bステージ化させた樹脂膜は、酸
無水物系またはフェノール系のエポキシ樹脂を主体とし
て構成される請求項13記載の半導体装置の製造方法。
14. The method according to claim 13, wherein the B-staged resin film is mainly composed of an acid anhydride-based or phenol-based epoxy resin.
【請求項15】 回路基板上に半導体素子をフェースダ
ウンにてフリップチップ実装する半導体装置の製造方法
において、 前記半導体素子が多数個形成されたウェーハ上の入出力
電極端子部に突起電極を形成し、 前記ウェーハ上に半硬化(Bステージ化)させた樹脂膜
を形成し、 前記ウェーハを分割して個別の半導体素子に分離し、 前記半導体素子をフェースダウンにて、回路基板の所定
の位置に加圧及び加熱処理を行って実装することを特徴
とする半導体装置の製造方法。
15. A method of manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted face-down on a circuit board, wherein a projecting electrode is formed on an input / output electrode terminal on a wafer on which a large number of the semiconductor elements are formed. Forming a semi-cured (B-staged) resin film on the wafer, dividing the wafer into individual semiconductor elements, and placing the semiconductor elements face down to predetermined positions on a circuit board. A method for manufacturing a semiconductor device, wherein the semiconductor device is mounted by performing pressure and heat treatments.
JP31365199A 1999-11-04 1999-11-04 Semiconductor element and method for manufacturing semiconductor device Pending JP2001135662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2001135662A true JP2001135662A (en) 2001-05-18

Family

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Country Status (1)

Country Link
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JP2002343904A (en) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd Semiconductor device
JP2004289113A (en) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp Metal electrode and bonding method using same
JP2006120716A (en) * 2004-10-19 2006-05-11 Rohm Co Ltd Semiconductor device
JP2008004968A (en) * 2007-09-25 2008-01-10 Seiko Epson Corp Terminal electrode, semiconductor device and module
JP2011091327A (en) * 2009-10-26 2011-05-06 Sharp Corp Solar cell module and method of manufacturing solar cell module
US9159892B2 (en) 2010-07-01 2015-10-13 Citizen Holdings Co., Ltd. LED light source device and manufacturing method for the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343904A (en) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd Semiconductor device
JP2004289113A (en) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp Metal electrode and bonding method using same
JP2006120716A (en) * 2004-10-19 2006-05-11 Rohm Co Ltd Semiconductor device
JP4567410B2 (en) * 2004-10-19 2010-10-20 ローム株式会社 Semiconductor device
JP2008004968A (en) * 2007-09-25 2008-01-10 Seiko Epson Corp Terminal electrode, semiconductor device and module
JP2011091327A (en) * 2009-10-26 2011-05-06 Sharp Corp Solar cell module and method of manufacturing solar cell module
US9159892B2 (en) 2010-07-01 2015-10-13 Citizen Holdings Co., Ltd. LED light source device and manufacturing method for the same

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