JP2004193297A - Wafer level package and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer level package which is different from one equipped with a conventional metal post, and which is manufactured by a short-time process and has high productivity, and also to provide a method of manufacturing the same. <P>SOLUTION: The wafer level package comprises a plurality of semiconductor chips 2 wherein a plurality of bonding pads 3 which are connection terminals are formed on a wafer, conductive bumps 5 connected to the bonding pads 3 via a heat-cured prepreg 4 stacked on the semiconductor chips 2, and solder balls 6 which are formed into copper foils 8 located immediately above the conductive bumps 5. In this package, there is no need of forming bumps for bonding pads of Al electrodes or the like of a semiconductor element on the wafer, and the conductive bumps are directly connected to the Al electrodes via the insulating prepreg. Consequently, the wafer level package is not restricted by the type of wafer and can be applied to various kinds of wafers. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wafer-level package for forming a package at a wafer level in mounting a semiconductor integrated circuit and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, as electronic devices have become more sophisticated, smaller, and lighter, the demand for high-density mounting of semiconductor integrated circuits has been increasing. Accordingly, there is a demand for miniaturization of semiconductor packages, increase in the number of pins, and fine pitch of external terminals.
Conventionally, a semiconductor package is polished on the back side of a wafer that has undergone a wafer process, then diced, cut and separated into chips, and then subjected to die bonding, wire bonding, resin sealing, etc. for each chip. A semiconductor device has been assembled, and a semiconductor element and a lead frame have been electrically connected by a wire bonding method.
In recent years, flip-chip connection using bumps of a chip which is superior to wire bonding in terms of high-speed signal processing and miniaturization has come to be used. For flip-chip connection, a semiconductor device with bumps is desirable in terms of ease of handling and reliability, and a package using a CSP (Chip Scale Package) method has been put to practical use.
[0003]
More recently, a so-called wafer-level package system has emerged as a package developed from a package at the chip size level, in which a plurality of semiconductor chips are collectively packaged at the wafer level. , Patent Documents 2 and 3).
[0004]
An example of a conventional method of manufacturing a wafer level package will be described with reference to FIG. As shown in FIG. 7, a conductive layer 73 for electroplating is provided by a vacuum film forming method such as vacuum evaporation or sputtering on a wafer 72 on which a semiconductor element having a bonding pad 71 such as an Al electrode is formed. 7 (a)) Next, a thick photosensitive resist is applied on the conductive layer 73, and the photosensitive resist is patterned by photolithography to form a predetermined resist pattern 75 having an opening 74 (FIG. 7A). 7 (b)). Next, the opening 74 of the resist pattern 75 is electroplated with a conductive metal such as copper or gold to form an element electrode metal post 76 of a semiconductor element (FIG. 7C). After peeling off, the metal layer 76 is formed on the bonding pad 71 of the semiconductor element by removing unnecessary portions of the conductive layer 73 by soft etching (FIG. 7D). Next, the surface of the semiconductor element on which the metal posts 76 are formed is sealed with a sealing resin 77 ′ such as an epoxy resin by compression molding or transfer molding (FIG. 7E). The surface of the metal post 76 is polished to expose the top of the metal post 76 (FIG. 7 (f)), and the solder ball 78 is formed on the exposed top of the metal post 76 (FIG. 7 (g)). 70 are manufactured.
[0005]
As shown in FIG. 7 (g), in the wafer level package 70 according to the conventional manufacturing method, a semiconductor element is formed on a wafer, and a metal wiring is formed on a main surface of the semiconductor element. A bonding pad 71 such as an Al electrode of a semiconductor element is provided on one end of the semiconductor chip, and a metal post 76 made of a metal column such as copper is formed on the bonding pad 71. At the upper end of the metal post 76, a connection electrode for connecting to a circuit board made of a solder ball 78 or the like is formed. Further, an insulating sealing resin 77 layer is formed between the plurality of metal posts 76.
The semiconductor chip is mounted on a circuit board by polishing and dicing the back surface of the wafer 72 on which the wafer level package 70 is formed, forming a solder paste on the circuit board by printing or the like, and then placing the semiconductor in a predetermined position on the circuit board. This is performed by aligning the chips with a chip mounter, placing the chips, and reflowing the chips.
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-353762 [Patent Document 2]
JP 2001-176909 A [Patent Document 3]
JP 2001-267455 A
[Problems to be solved by the invention]
However, the conventional wafer-level package provided with the metal posts as described above has a long and complicated manufacturing process and is inferior in productivity, and has a vacuum film forming apparatus and a plating bath for forming a plating layer, and a sealing resin. However, since it is necessary to use a mold for forming the substrate, there is a problem that the equipment cost is increased. In addition, since the height of the metal post is about 100 μm, it exceeds the exposure limit of 20 to 30 μm, which is a normal photosensitive resist, and even if a 100 μm photosensitive resist layer is applied and formed, multiple exposures are required. And there is a problem that productivity is poor. Further, even after the metal posts are formed by electrolytic plating, there is a problem that inefficient and complicated operations such as soft etching of the conductive layer and polishing of excess sealing resin have to be performed.
[0008]
Therefore, the present invention has been made to solve such a problem. An object of the present invention is to provide a low-cost, high-quality wafer-level package and a method for manufacturing the same, which have a short manufacturing process, do not require an expensive vacuum film forming apparatus, and do not require metal posts.
[0009]
[Means for Solving the Problems]
In order to solve the above problem, a wafer level package according to the invention of claim 1 includes a plurality of semiconductor chips provided with a plurality of bonding pads serving as connection terminals on a wafer, and stacked on the semiconductor chip. A conductive bump connected to the bonding pad via a thermoset prepreg, and a solder ball formed on a conductive metal foil provided immediately above the conductive bump.
[0010]
According to a second aspect of the present invention, the conductive bump has a truncated cone shape.
[0011]
According to a third aspect of the present invention, in the wafer level package, the solder ball is formed so as to cover a conductive metal foil in contact with the conductive bump.
[0012]
The wafer level package according to the invention of claim 4 is characterized in that the thermoset prepreg laminated on the semiconductor chip is two or more layers, and the prepreg is provided with at least one wiring layer. is there.
[0013]
According to a fifth aspect of the present invention, there is provided a method of manufacturing a wafer-level package, comprising: forming a plurality of conical conductive bumps on a conductive metal foil; and insulating the conductive bumps formed on the conductive metal foil. Laminating with a conductive prepreg, penetrating the conductive bumps through the prepreg, and positioning the conductive bumps penetrating the prepreg on a wafer having a plurality of semiconductor chips having a plurality of bonding pads formed on a surface thereof. Laminating, connecting the conductive bumps and the bonding pads via a thermoset prepreg, pattern-etching the conductive metal foil into a predetermined shape by photolithography, Forming a solder ball on the conductive metal foil on which the conductive bumps have been formed.
Since the manufacturing method of the present invention does not form bumps on the bonding pads on the wafer, it can be applied to various wafers without depending on the wafer maker and the type of the wafer. Further, as compared with the conventional manufacturing method using metal posts, the manufacturing process is shorter, the method is more productive, and a low-cost, high-density wafer-level package can be obtained.
[0014]
According to a sixth aspect of the present invention, there is provided a method of manufacturing a wafer-level package, comprising: forming a plurality of conical conductive bumps on a conductive metal foil; and insulating the conductive bumps formed on the conductive metal foil. Laminating with a conductive prepreg and allowing the conductive bump to penetrate the prepreg; and laminating and pressing a conductive metal foil on the tip side of the conductive bump that has penetrated the prepreg, and forming the laminated conductive metal foil. Forming a wiring by pattern etching into a predetermined shape by photolithography, forming a plurality of conical conductive bumps on the conductive metal foil on which the wiring is formed, Laminating the conductive bump formed thereon with an insulating prepreg, and allowing the conductive bump to penetrate the prepreg; and a conductive bump penetrating the prepreg. After positioning a plurality of bonding pads on a wafer having a plurality of semiconductor chips formed on the surface, stacking and pressing, connecting the conductive bumps and the bonding pads via a thermoset prepreg; A step of pattern-etching the conductive metal foil on which a conductive bump is first formed into a predetermined shape by a photolithography method, and a step of forming a solder ball on the conductive metal foil. It is.
According to the manufacturing method of the present invention, a multilayer wiring board can be provided on a wafer and packaged.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
The wafer level package of the present invention does not need to provide a metal post connected to a bonding pad such as an Al electrode which is an input / output terminal of a semiconductor element, and does not need to use a sealing resin.
The wafer level package of the present invention is not manufactured by a method in which members constituting the package are sequentially stacked on a wafer on which semiconductor elements are formed, unlike a conventional wafer level package, but is formed on a copper foil in a separate process. The conductive bumps prepared in the above are directly laminated with the semiconductor element via the prepreg, and the conductive bumps are pressure-bonded to the bonding pads to make electrical connection.The copper foil, the insulating base, and the a configuration using a plurality of conductive bumps formed through the insulating substrate ^B 2 it (registered trademark, Buried bump InterconnectionTechnology, (Inc.) developed by Toshiba B- called square-it) method It is an application of technology.
[0016]
(Wafer level package)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a wafer level package 1 of the present invention, in which a plurality of bonding pads 3 serving as connection terminals are formed on a surface of a wafer 2 via a plurality of semiconductor chips and a thermosetting prepreg 4 on the semiconductor chip. And a plurality of conductive bumps 5 connected to the bonding pads 3 and a solder ball 6 formed over a conductive metal foil such as a copper foil immediately above the conductive bumps 5. is there.
[0017]
Conductive bump 5 and the prepreg 4 of the present invention has been created in B ² it method, on a conductive metal foil such as copper foil as the conductive bump 5, the conductive powder and an epoxy resin such as silver particles Screen printing of conductive paste containing resin and solvent as main components, etc., and drying, forming cone-shaped conductive bumps through semi-cured glass cloth epoxy resin prepreg, etc. After the top of the conductive bump is projected from the prepreg, the wafer 2 having the semiconductor chip provided with the bonding pad and the prepreg provided with the conductive bump are aligned and pressed by lamination, so that the top of the conductive bump is connected to the connection on the wafer. Direct pressure contact bonding with an Al electrode forming the bonding pad 3 as a terminal. Due to the pressure bonding, the top of the conductive bump protruding from the prepreg is crushed, and the conductive bump 5 has a truncated cone shape.
[0018]
In the present invention, the thickness of the glass cloth-containing prepreg 4 can be arbitrarily set, but is used in the range of 0.06 to 0.1 mm in order to penetrate the conductive bumps 5 and secure insulation. Is preferred.
In the present invention, since the conductive bumps are formed by a screen printing method, the semiconductor bumps of the present invention are preferably applied to a terminal pitch of a semiconductor element of 120 μm or more. In addition, the height of the conductive bumps after screen printing and drying is required to penetrate the prepreg, so that the height is at least larger than the thickness of the prepreg to be used, penetrates the prepreg, and is press-bonded to the bonding pad 3. Preferably has a sufficient height.
[0019]
The thickness of a conductive metal foil such as a copper foil on which the conductive bumps 5 are printed can also be set arbitrarily. For example, a copper foil having a general thickness of 18 μm can be exemplified. In the example of FIG. 1, the copper foil shows a case where a circular portion where a conductive bump is printed and formed is left, and the other portion is etched and removed, and a solder ball is formed so as to cover the copper foil of the bump forming portion. Have been.
Of course, a desired copper wiring layer can be formed in a region other than the solder ball forming region.
[0020]
FIG. 2 is a drawing showing another embodiment of the wafer level package of the present invention.
In a wafer level package 21 shown in FIG. 2, a plurality of semiconductor chips having a plurality of bonding pads 23 serving as connection terminals formed on a surface of a wafer 22 and a thermosetting prepreg 24b on the semiconductor chip are used to form the semiconductor chip. A plurality of conductive bumps 25b connected to the bonding pad 3 and a wiring layer 27b are provided, and the copper foil immediately above the conductive bumps 25a is covered via a thermosetting prepreg 24a laminated on an upper layer. And a solder ball 26 formed. Thus, the wafer level package of the present invention, on a wafer on which a semiconductor chip is provided, it is possible to provide a wiring layer at least one layer by B 2 ^it method, high-density wiring layer further desired during implementation Can be obtained.
[0021]
(Wafer level package manufacturing method)
(1st Embodiment)
FIG. 3 is a process chart showing a method of manufacturing the wafer level package 1 according to an example of the embodiment of the present invention shown in FIG. Before describing the manufacturing method of the present invention with reference to FIG. 3, the B ² it method used in the present invention will be briefly described.
[0022]
6 is a process schematic diagram for explaining a method of manufacturing a wiring board according to B ² it method.
As shown in FIG. 6A, a conductive paste is printed on the copper foil 61a by a screen printing method, dried, and a conductive bump 62 is formed at a predetermined position on the copper foil 61a. The conductive bump 62 is formed in a conical shape with a sharp tip so as to penetrate the prepreg 63 which is an insulating layer.
[0023]
Next, under a temperature condition of about 95 to 115 ° C., the formed conductive bumps 62 are laminated on a prepreg 63 made of epoxy resin containing glass cloth, and the conductive bumps are penetrated. Penetrate through. Subsequently, the abutting copper foil 61b is overlaid and laminated and pressed at a temperature and pressure at which the prepreg 63 is cured, thereby forming a conductive substrate 64 in which predetermined portions are electrically connected by conductive bumps, as shown in FIG. I do. Thereafter, as shown in FIG. 6 (c), the front and back of the copper foil pattern - and down etched wiring pattern - to form a plane 65, to obtain a double-sided wiring board 66 according to B 2 ^it method.
Hereinafter, by performing the same steps as necessary, a multilayer wiring board having a further multilayer structure can be obtained.
The manufacturing method of the present invention will be described with reference to FIG. The conductive metal foil used in the present invention is preferably a copper foil in terms of conductivity, affinity with solder, price, and the like. A conductive paste mainly composed of a conductive powder such as silver particles, a resin such as an epoxy resin, and a solvent is printed on a copper foil 7 having a predetermined thickness at a predetermined position by a screen printing method and dried. Thus, a conical conductive bump 5 'is formed (FIG. 3A). The positions of the conductive bumps 5 'are printed at positions corresponding to bonding pads serving as connection terminals on the wafer to be joined.
[0025]
Subsequently, the conductive bumps 5 'are laminated on the glass cloth-containing prepreg 4' having a predetermined thickness by a dedicated machine and penetrated, so that the tips of the conductive bumps 5 'protrude onto the prepreg 4' (FIG. b)).
[0026]
Next, after the conductive bumps 5 'penetrating through the prepreg 4' are aligned with the wafer 2 having the semiconductor chips having the bonding pads 3 formed on the surface thereof, the conductive bumps 5 'are laminated, pressurized and heated, and heat-cured prepreg. The conductive bumps 5 and the bonding pads 3 are electrically connected to each other by press-bonding via the wires 4 (FIG. 3C). At this time, even if there is an oxide film on the Al electrode of the bonding pad 3, the protrusion at the tip of the conductive bump 5 breaks the oxide film by pressure welding and forms a sufficient electrical connection.
[0027]
Next, the conductive bumps 5 are formed by photo-etching, and the copper foil in other portions is removed by etching, leaving the copper foil 8 forming the solder balls (FIG. 3D).
[0028]
Next, the solder ball 6 is formed by covering the copper foil 8 of the solder ball forming portion having a predetermined shape by etching to form the wafer level package 1 (FIG. 3E). The solder ball forming portion is formed of copper having a good affinity for solder, and the solder ball may be formed by a printing method or a forming method using a bonder or the like.
[0029]
(Second embodiment)
A second embodiment of the manufacturing method of the present invention will be described with reference to FIG. 4 and FIG.
As in the first embodiment, a conductive paste mainly composed of a conductive powder, a resin such as an epoxy resin, and a solvent is placed in a predetermined position on a copper foil 28 having a predetermined thickness by a screen printing method. It is applied and dried to form a first conductive bump 25'a having a conical shape (FIG. 4A). The position of the conductive bump 25'a is printed at a position corresponding to the bonding position of the wiring board for bonding the wafer level package with the solder balls.
[0030]
Subsequently, the first conductive bump 25'a is made to penetrate the glass cloth-containing prepreg 24a of a predetermined thickness by a special-purpose machine, and then the first conductive bump 25'a is placed on the abutting side of the tip of the penetrated conductive bump 25'a. A copper foil 27 'having a thickness is stacked, and a laminating press is performed at a predetermined temperature and pressure (FIG. 4B).
[0031]
Next, the copper foil on the abutting side subjected to the lamination pressing is subjected to pattern etching to form a region 27a for printing the second conductive bump and a desired wiring 27b (FIG. 4C).
[0032]
Next, a second conductive bump 25'b is printed on the area 27a for printing the second conductive bump, and after drying, the second prepreg 24'b is penetrated (FIG. 4 ( d)).
[0033]
Next, after the bonding pads 23 of the wafer 22 on which the plurality of semiconductor chips provided with the bonding pads of the plurality of Al electrodes are formed and the conductive bumps 25'b protruding from the prepreg 24'b are accurately aligned, the vacuum Lamination pressing is performed at a predetermined temperature and pressure by a hot press machine, and each conductive bump 25b is press-contacted to a predetermined bonding pad 23 via a thermosetting prepreg 24b (FIG. 4E).
[0034]
Next, a photoresist is applied to the copper foil 28 on the opposite side of the wafer 22 with the prepreg therebetween, dried, exposed using a photomask, developed, and the exposed copper foil is subjected to an aqueous ferric chloride solution. To form a plurality of circular pattern copper foils 29 having dimensions to cover the conductive bumps (FIG. 4F).
Next, a solder ball 26 is formed on each of the plurality of circular pattern copper foils 29 serving as a solder ball forming portion, and a wafer level package 21 having a multilayer wiring board provided with an internal wiring 27b on a wafer 22 is formed. It is formed (FIG. 4G).
[0035]
【Example】
(Example 1)
A silver paste mainly composed of silver powder and melamine resin, phenol resin and epoxy resin (melamine resin: phenol resin: epoxy resin = 5: 5: 1 weight ratio), curing agent, diethylene glycol monobutyl ether acetate, and 18 μm thick copper A predetermined position on the foil was printed by a screen printing method and dried to form a plurality of conical conductive bumps having a bottom and a sharp tip with a diameter of 200 μm. Then, using a FR-4 (NEMA: National Electrical Manufacturing Associations standard) type prepreg containing glass cloth with a thickness of 100 μm, the conductive bumps were penetrated using a special machine, and the conductive bumps contained glass cloth. The prepreg was cut or scraped and penetrated, and its tip protruded above the prepreg.
[0036]
Next, after accurately aligning the bonding pad portion of the wafer on which a plurality of semiconductor chips provided with the bonding pads of the plurality of Al electrodes are formed with the conductive bumps protruding from the prepreg through the prepreg, a vacuum heat press machine is used. At a temperature of 100 ° C. under a predetermined pressure, and each conductive bump was connected to a predetermined bonding pad.
[0037]
Next, a photoresist is applied to the copper foil on the opposite side of the wafer with the prepreg therebetween, dried, and then exposed using a photomask having a plurality of circular patterns of 250 μm in diameter covering the conductive bumps of 200 μm in diameter. Then, the developed and exposed copper foil was removed by etching with an aqueous ferric chloride solution to form a copper foil having a plurality of circular patterns having a diameter of 250 μm.
Next, a solder ball was formed on each of the plurality of circular patterns of copper to obtain a wafer-level package.
[0038]
(Example 2)
Using the same silver paste as in Example 1, it was applied to a predetermined position on a copper foil having a thickness of 18 μm by a screen printing method, dried in an oven at 100 ° C., and a plurality of conical first conductive bumps having a diameter of 200 μm were formed. Formed. Subsequently, conductive bumps were made to penetrate the 100 μm-thick glass cloth-containing epoxy prepreg using a special-purpose machine. Subsequently, a copper foil of 18 μm was laminated on the bump forming copper foil on the side of the bumping bump with the through bump, and a laminating press was performed at a predetermined temperature and pressure.
After the lamination press, the copper foil on the abutting side was pattern-etched to form wiring and a second conductive bump printing area.
[0039]
Next, a plurality of conical conductive bumps having a diameter of 200 μm are formed on the copper foil in the second conductive bump printing area by the same method as described above, and then a 100 μm thick epoxy containing glass cloth is formed. The conductive bumps were made to penetrate the prepreg using a dedicated machine.
[0040]
Next, after accurately aligning the bonding pad portion of the wafer on which the plurality of semiconductor chips provided with the bonding pads of the plurality of Al electrodes are formed with the conductive bumps protruding from the prepreg through the prepreg, a vacuum heat press machine is used. , And the conductive bumps were connected to predetermined bonding pads, respectively.
[0041]
Next, a photoresist is applied to the copper foil on the opposite side of the wafer with the prepreg therebetween, dried, and then exposed using a photomask having a plurality of circular patterns of 250 μm in diameter covering the conductive bumps of 200 μm in diameter. Then, the developed and exposed copper foil was removed by etching with an aqueous ferric chloride solution to form a copper foil having a plurality of circular patterns having a diameter of 250 μm.
Next, a solder ball was formed on each of the plurality of copper circular patterns to obtain a wafer-level package having an internal wiring substrate on a wafer.
[0042]
【The invention's effect】
In the present invention, the process of forming a bump is not required for a bonding pad such as an Al electrode of a semiconductor element on a wafer, and a method of directly connecting a conductive bump to an Al electrode via an insulating prepreg is used. There is an advantage that the present invention is not limited to a wafer and can be applied to various wafers. In addition, by applying the B ² it method as needed, a multilayer wiring board having internal wiring can be stacked on a wafer, so that the wafer level package can be further added value.
[0043]
In addition, the method for manufacturing a wafer level package of the present invention does not need to form a metal post unlike the conventional manufacturing method, so that a step of patterning a thick photosensitive resist is unnecessary, and the method for forming a plating layer is not required. Neither a vacuum film forming apparatus nor equipment using a mold for forming the sealing resin is required, and the manufacturing can be performed in a short process. Further, there is no need for a step of performing inefficient polishing and obtaining electrical connection as in the conventional method of forming metal posts. Therefore, the manufacturing method of the present invention is a method of manufacturing a wafer-level package that has high productivity, high cost reduction effect, and high density. Further, since the solder ball forming portion of the present invention is formed of copper having a good affinity for solder, high quality solder balls can be easily formed.
[Brief description of the drawings]
FIG. 1 is a partial longitudinal sectional view showing one embodiment of a wafer level package of the present invention; FIG. 2 is a partial longitudinal sectional view showing another embodiment of a wafer level package of the present invention; FIG. FIG. 4 is a process cross-sectional view illustrating a method of manufacturing a package. FIG. 4 is a process cross-sectional view illustrating a method of manufacturing a wafer-level package according to another embodiment of the present invention. FIG. 5 is another embodiment of the present invention following FIG. process overviews illustrating a method of manufacturing a wiring board according to B ² it technique used in the production method of a wafer level package of sectional views [6] the present invention for explaining a manufacturing method of a wafer level package according to FIG. 7 prior Cross-sectional view for explaining a method of manufacturing a wafer level package of the present invention [Description of reference numerals]
1, 21 Wafer level package 2, 22 Wafer 3, on which semiconductor elements are formed, 23 Bonding pad 4 ', 24'b Prepreg 4, 24a, 24b Thermoset prepreg 5', 25'a, 25'b Conductive bump 5 , 25a, 25b Conductive bumps 6, 26 Solder balls 7, 27 ', 28 Copper foil 8, 29 Copper foil 27a in solder ball forming area Copper foil 27b in conductive bump print area Wiring 61a, 61b Copper foil 62 Conductive bump 63 prepreg 64 conductive substrate 65 wiring pattern 66 wiring substrate 70 wafer level package 71 bonding pad 72 wafer 73 conductive layer 74 opening 75 resist pattern 76 metal post 77 sealing resin 78 solder ball

Claims (6)

A plurality of semiconductor chips provided with a plurality of bonding pads serving as connection terminals on the wafer,
A conductive bump connected to the bonding pad via a thermoset prepreg laminated on the semiconductor chip,
A solder ball formed on a conductive metal foil provided immediately above the conductive bump. The wafer level package according to claim 1, wherein the conductive bump has a truncated cone shape. 3. The wafer level package according to claim 1, wherein the solder ball is formed so as to cover a conductive metal foil in contact with the conductive bump. The wafer according to any one of claims 1 to 3, wherein the thermosetting prepreg laminated on the semiconductor chip has two or more layers, and the prepreg has at least one wiring layer. Level package. Forming a plurality of conical conductive bumps on the conductive metal foil,
Laminating a conductive bump formed on the conductive metal foil with an insulating prepreg, and penetrating the conductive bump through the prepreg;
After aligning the conductive bumps penetrating the prepreg with a wafer having a plurality of semiconductor chips having a plurality of bonding pads formed on the surface, a laminate press is performed, and the conductive bumps and the aforesaid via a thermoset prepreg are pressed. A step of connecting to a bonding pad;
A step of pattern-etching the conductive metal foil into a predetermined shape by photolithography,
Forming a solder ball on the conductive metal foil on which the conductive bumps are formed. Forming a plurality of conical conductive bumps on the conductive metal foil,
Laminating a conductive bump formed on the conductive metal foil with an insulating prepreg, and penetrating the conductive bump through the prepreg;
A step of laminating and pressing a conductive metal foil on the tip side of the conductive bump penetrating the prepreg and pattern-etching the laminated conductive metal foil into a predetermined shape by photolithography to form wiring; and ,
Forming a plurality of conical conductive bumps on the conductive metal foil on which the wiring is formed,
Laminating a conductive bump formed on the conductive metal foil with an insulating prepreg, and penetrating the conductive bump through the prepreg;
After aligning the conductive bumps penetrating the prepreg with a wafer having a plurality of semiconductor chips having a plurality of bonding pads formed on the surface, a laminate press is performed, and the conductive bumps and the aforesaid via a thermoset prepreg are pressed. A step of connecting to a bonding pad;
A step of pattern-etching the conductive metal foil on which the conductive bumps are first formed into a predetermined shape by photolithography,
Forming a solder ball on the conductive metal foil.

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