KR101340348B1 - Embedded chip package board using mask pattern and method for manufacturing the same - Google Patents

Abstract

An improved chip embedded package substrate and a method of manufacturing the same are provided. In the method for manufacturing a chip embedded package substrate of the present invention, forming a mask pattern exposing a region where a junction portion connecting a chip and a printed circuit pattern to be formed is formed on a lower carrier, and forming a conductive junction portion between the mask patterns. Mounting a semiconductor chip on the conductive junction, forming an insulating layer on the lower carrier on which the chip is mounted, introducing an upper carrier on the insulating layer, and embedding the chip in the insulating layer. Bonding the lower carrier and the upper carrier, removing remaining layers other than the base metal layers of the lower carrier and the upper carrier, forming printed circuit patterns on the upper and lower surfaces of the insulating layer, and removing the mask pattern. And forming a solder mask between the conductive junctions and between the printed circuit patterns.

Description

Embedded chip package board using mask pattern and manufacturing method thereof {Embedded chip package board using mask pattern and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit devices, and more particularly, to an embedded chip package substrate in which an integrated circuit chip is embedded in a package substrate and a method of manufacturing the same.

In general, a semiconductor package is a technology for packaging a chip in order to easily draw various electrical input / output signals of the semiconductor chip to the outside. In recent years, a semiconductor package has been reduced in size close to the chip size, heat dissipation performance and electrical performance of the semiconductor chip In order to realize a structure capable of maximizing the structure, various members such as lead frames, printed circuit boards, and circuit films are manufactured.

In the semiconductor industry, such packaging technology continues to evolve to meet the demand for miniaturization and thinning, and mounting reliability. For example, the demand for miniaturization and thinning is accelerating the development of technology for packages close to chip size, and the demand for mounting reliability is important for packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. Is highlighted. One example of miniaturization and thinning of such a package is a ball grid array package (hereinafter referred to as BGA). According to the BGA package, the semiconductor chip is attached on the substrate, the bonding pad of the semiconductor chip and the bond finger of the substrate are interconnected by a bonding wire, and the top surface of the substrate including the semiconductor chip and the bonding wire is sealed with an encapsulation member. Solder balls are attached to the ball lands of the substrate as mounting means to external circuits.

1 is a cross-sectional view showing an example of a BGA package.

Referring to FIG. 1, a semiconductor chip 120 is mounted on an insulating substrate 110 on which a printed circuit pattern is formed through a solder ball 130. The underfill layer 140 made of an insulating material such as epoxy is filled in the space between the semiconductor chip 120 and the insulating substrate 110, and a molding layer 150 is formed to surround and protect the semiconductor chip 120. do.

Since the overall size of the BGA package is similar to the chip size, the mounting area can be minimized. In particular, since the electrical connection with the external circuit is made by the solder ball, the advantage of the improved electrical characteristics is minimized through the minimization of the electrical signal transmission path. have.

However, in manufacturing a BGA package, the solder ball mounting process is conventionally performed, and when the ball size becomes smaller or the ball pitch becomes smaller, it is difficult to implement a corresponding device. In addition, poor coplanarity may occur depending on the size difference between the mounted balls. In addition, an underfilling layer is formed to protect the solder ball, which serves as an electrical passage between the insulating substrate 110 and the semiconductor chip 120, which results in an increase in production cost and a long process time.

The problem to be solved by the present invention can simplify the process, eliminate the disadvantages by omitting the solder ball mounting process, and can prevent the damage of the chip during the thermocompression process in the chip embedded package substrate manufacturing Disclosed is a chip embedded package substrate having a structure and a method of manufacturing the same.

In order to solve the above problems, a chip embedded package substrate according to an exemplary embodiment of the present invention may include an insulating layer having a chip embedded therein, printed circuit patterns formed on upper and lower surfaces of the insulating layer, and a chip passing through the insulating layer. And a plurality of joints connecting the printed circuit pattern to each other, and a solder mask to isolate the neighboring joints from each other.

In one example, the chip may be an active device including an integrated circuit (IC) device or any one passive device selected from the group including a capacitor, an inductor, and a resistor.

In order to solve the above problems, a method of manufacturing a chip embedded package substrate according to an exemplary embodiment may include forming a mask pattern on a lower carrier, exposing a region where a junction portion connecting a chip and a printed circuit pattern is to be formed. Forming a conductive junction between the mask pattern, mounting a semiconductor chip on the conductive junction, forming an insulating layer on the lower carrier on which the chip is mounted, and forming an insulating layer on the insulating layer. Introducing an upper carrier, adhering the lower carrier and the upper carrier so that the chip is embedded in the insulating layer, removing remaining layers other than the base metal layers of the lower carrier and the upper carrier, and Forming printed circuit patterns on the upper and lower surfaces of the layer, removing the mask pattern, and the conductive bonding portion And forming a solder mask between the printed circuit patterns and the printed circuit patterns.

The lower carrier may comprise a copper base metal layer.

The mask pattern may be formed at the same height as a conductive junction connecting the chip and the printed circuit pattern.

In the step of forming the conductive junction, the solder paste may be formed using a solder paste, a solder on pad (SOP), an anisotropic conductive film (ACF), or a conductive bump.

The chip may be an active device including an integrated circuit (IC) device or any one passive device selected from a group including a capacitor, an inductor, and a resistor.

Forming printed circuit patterns on the upper and lower surfaces of the insulating layer may include forming printed circuit patterns by plating using metal layers of the upper and lower carriers as seed layers, and using the printed circuit patterns. And etching the exposed base metal layer.

The etching of the base metal layer may be performed by a flash etching process.

According to the chip embedded package substrate of the present invention and a method of manufacturing the same, since the mask pattern and the conductive joint serve as a support under the chip in the process of heat pressing after chip mounting, it is possible to prevent chip breakage. In addition, since the mask pattern is removed after the chip mounting and the solder mask is formed in the space, the process of filling the space between the chip and the package substrate with the underfill material after the chip mounting can be omitted, thereby simplifying the process and reducing the process time. Can reduce the manufacturing cost.

1 is a cross-sectional view showing an example of a BGA package.
2 is a cross-sectional view illustrating a chip embedded package substrate according to an exemplary embodiment of the present invention.
3 to 10 are cross-sectional views illustrating a method of manufacturing a chip embedded package substrate according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of a semiconductor package and a method of manufacturing the same according to an aspect of the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and a duplicate description thereof will be omitted.

2 is a cross-sectional view illustrating a chip embedded package substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the chip embedded package substrate 200 may include an insulating layer 250 having a chip 240 therein and a printed circuit pattern formed on upper and lower surfaces of the insulating layer 250. (213 + 270a, 263 + 270b), a plurality of junctions 230 connecting the chip 240 and the printed circuit pattern through the insulating layer 250, and between the adjacent junctions and the printed circuit patterns It includes a solder mask (280a, 280b) to isolate the.

In one example, the chip 240 is an active device including an integrated circuit (IC) device, or any one passive device selected from the group including a capacitor, an inductor and a resistor device. Can be.

The junction part 230 electrically connects the chip 240 and the package substrate, and includes a solder paste, a solder on pad (SOP), an anisotropic conductive film (ACF), or a conductive bump. It can be formed using.

According to the chip embedded package substrate 200 of the present invention illustrated in FIG. 2, the chip 240 is embedded in the insulating layer 250, and a junction portion is formed between the chip 240 and the printed circuit pattern instead of the underfill layer. 230 and solder masks 280a and 280b are provided. Therefore, the package substrate structure can be simplified, and a process of forming the underfill layer between the chip 240 and the printed circuit pattern can be omitted.

3 to 10 are cross-sectional views illustrating a method of manufacturing a chip embedded package substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3, first, a lower carrier 210 having a base metal layer 213 on which a pattern plating is to be performed is formed. The lower carrier 210 may use a commercial copper clad laminate such as CCL, and a substrate made of a material such as a stainless substrate may be used if necessary. The lower carrier 210 is not a part substantially related to the chip scale package substrate, but only needs to temporarily support the conductive pattern layer to function as a bonding structure, and thus the present invention is not limited by the material or the material. .

For example, the lower carrier 210 may include a base metal layer 213 on which pattern plating is to be performed, a carrier metal layer 212 supporting the base metal layer 213, and an insulating layer 211 made of an insulating material such as resin. It may be a stacked structure. In this case, the base metal layer 213 may be formed of, for example, a copper (Cu) layer. The carrier metal layer 212 supporting the base metal layer 213 is a layer to be removed in a subsequent process, and may be formed of a material equivalent to the base metal layer 213, for example, a copper layer. The insulating layer 211 may be formed of an insulating material as a carrier body to be peeled off and removed in a subsequent process.

Next, a mask pattern 220 is formed on the base metal layer 213 of the lower carrier 210 to form a junction portion electrically connecting the printed circuit pattern and the chip. In this case, the mask pattern 220 may be formed to expose a region where the printed circuit pattern of the lower carrier is to be formed. The mask pattern 220 supports the semiconductor chip together with the conductive joint in the process of mounting the semiconductor chip, introducing the insulating layer and the upper carrier, and heating and compressing the semiconductor chip to embed the semiconductor chip. Can be formed.

The mask pattern 220 may be formed by exposing an image of a printed circuit pattern by forming a photosensitive material on the base metal layer 213 and performing an exposure and development process. Patterning the photosensitive material reduces the time required for the entire imaging process.

Referring to FIG. 4, the conductive junction 230 is formed in the exposed areas between the mask patterns 220. The conductive junction 230 serves to electrically connect the semiconductor chip mounted on the top and the printed circuit pattern.

The conductive junction 230 may be formed by electroplating using the base metal layer 213 as a seed layer. Alternatively, a conductive material such as solder paste may be used to form a silk screen, and may be formed using a solder on pad (SOP), anisotropic conductive film (ACF), or conductive bumps. Can be formed.

Referring to FIG. 5, the semiconductor chip 240 is mounted on the mask pattern 220 and the conductive junction 230. The semiconductor chip 240 may be an active device such as an integrated circuit (IC) device, or may be a passive device such as a capacitor, an inductor, or a resistor.

Referring to FIG. 6, the insulating layer 250 is formed to have a predetermined thickness so as to cover the semiconductor chip 240 mounted on the conductive junction 230. The insulating layer 250 may be formed to completely cover the semiconductor chip 240 by forming a predetermined thickness from the surface of the lower carrier 210 to act as a package substrate body while protecting the semiconductor chip 240. In the present invention, the semiconductor chip 240 is mounted on the conductive junction 230 and the mask pattern 220, and the insulating layer 250 is formed to embed the semiconductor chip, thereby underfilling the space between the package substrate and the semiconductor chip. The process of filling the material can be omitted.

After the insulating layer 250 is formed to completely embed the semiconductor chip 240 in the insulating layer, the carrier metal layer 261 and the base metal layer 263 of the upper carrier 260 are disposed on the insulating layer 250. Introduce. After the opening, the upper carrier 260 is compressed and heated to bond the upper carrier 260 and the lower carrier 210 to each other, and the semiconductor chip 240 is embedded in the insulating layer 250. By such compression and heating, an insulating material such as resin constituting the insulating layer 250 is cured to bond the upper carrier 260 and the lower carrier 210. In the process of embedding the semiconductor chip for pressing and heating the upper carrier 260, the semiconductor chip 240 is damaged because the mask pattern 220 and the conductive junction 230 formed on the upper carrier serve as a support. The problem does not occur.

Referring to FIG. 7, the insulating layer of the lower carrier, the carrier metal layer, and the carrier metal layer of the upper carrier are peeled off, respectively. The surfaces of the base metal layers 213 and 263 of the lower carrier and the upper carrier are then exposed, respectively.

Referring to FIG. 8, printed circuit patterns 270a and 279b are formed on the base metal layer of the lower carrier and the upper carrier, respectively, for electrical connection. The printed circuit patterns 270a and 270b may be formed by plating using the base metal layers 213 and 263 as seed layers. For example, a dry film may be formed on the base metal layers 213 and 263, and a pattern for exposing an image of a printed circuit pattern may be formed by performing exposure and development processes. By patterning the dry film, the time required for the entire imaging process can be reduced. Next, after forming a printed circuit pattern 270a and 270b by performing a pattern plating process such as copper plating on portions of the base metal layers 213 and 263 exposed to the dry film, the dry film is peeled off and removed.

As another example, the printed circuit patterns 270a and 270b may be formed using solder paste, solder balls, solder bumps, anisotropic conductive films (ACFs) or wire bonding. Can be formed.

Referring to FIG. 9, flash etching may be performed to remove the base metal layers 213 and 263 remaining between the printed circuit patterns. As a result, the upper surface of the insulating layer 250 and the surface of the mask pattern are exposed. Subsequently, when the exposed mask pattern is etched and removed, the semiconductor chip 240 between the conductive junctions 230 is exposed as shown.

Referring to FIG. 10, a solder mask 280a is formed in the space between the conductive junctions 230. In this case, a solder mask 280b is formed on the exposed upper surface of the insulating layer 250, that is, between the printed circuit patterns 263 and 270b. The solder masks 280a and 280b may be formed by applying a solder resist and developing. The solder masks 280a and 280b serve to isolate the printed circuit patterns 270a and 270b. In particular, the solder mask 280a also supports the semiconductor chip while isolating the conductive junctions 230.

According to the present invention, a mask pattern exposing a printed circuit pattern region is formed on a carrier including a copper base metal layer, a conductive junction is formed between the mask patterns, and then a semiconductor chip is mounted and an insulating layer is formed. To be built. Therefore, since the mask pattern and the conductive joint serve as a support under the chip in the process of heat pressing after chip mounting, it is possible to prevent breakage of the chip.

In addition, since the mask pattern is removed after the chip mounting and the solder mask is formed in the space, the process of filling the space between the chip and the package substrate with the underfill material after the chip mounting can be omitted, thereby simplifying the process and reducing the process time. Can reduce the manufacturing cost.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Such changes and modifications are intended to fall within the scope of the present invention unless they depart from the scope of the present invention. Therefore, the scope of the present invention will be determined by the claims described below.

100, 200 ..... Package 210 ..... Lower Carrier
230 ..... junction 240 ..... semiconductor chip
250 ..... insulating layer 260 ..... top carrier
270a, 270b..printed circuit pattern 280a, 280b ..... solder mask

Claims (9)

An insulation layer having chips embedded therein;
Printed circuit patterns formed on upper and lower surfaces of the insulating layer;
A plurality of junctions disposed to extend from a bottom surface of the chip through the insulating layer and to connect the chip and the printed circuit pattern; And
And a solder mask disposed to extend from a bottom surface of the chip and filling side spaces between the junctions. The method of claim 1,
The chip is a chip embedded package substrate, characterized in that any one of a passive element selected from the group including an active element including an integrated circuit (IC) element, or a capacitor, an inductor and a resistance element. Forming a mask pattern on the lower carrier, the mask pattern exposing a region where a junction portion connecting the chip and the printed circuit pattern is to be formed;
Forming a conductive junction between the mask patterns;
Mounting a semiconductor chip on the conductive junction;
Forming an insulating layer on the lower carrier to cover the semiconductor chip mounted on the conductive junction;
Introducing an upper carrier on the insulating layer;
Adhering the lower carrier and the upper carrier so that the chip is embedded in the insulating layer;
Removing the remaining layer except for the base metal layer of the lower carrier and the upper carrier;
Forming printed circuit patterns on upper and lower surfaces of the insulating layer;
Removing the mask pattern; And
And forming a solder mask between the conductive joints and the printed circuit patterns. The method of claim 3,
The lower carrier is a chip embedded package substrate manufacturing method comprising a copper base metal layer. The method of claim 3,
The mask pattern is a chip embedded package substrate manufacturing method, characterized in that formed at the same height as the conductive junction connecting the chip and the printed circuit pattern. The method of claim 3,
Forming the conductive junction,
Method for manufacturing a chip embedded package substrate, characterized in that formed using a solder paste, a solder on pad (SOP), an anisotropic conductive film (ACF) or conductive bumps. The method of claim 3,
The chip is a method for manufacturing a chip embedded package substrate, characterized in that any one of a passive device selected from the group consisting of an active device including an integrated circuit (IC) device, or a capacitor, an inductor and a resistor. The method of claim 3,
Forming a printed circuit pattern on the upper and lower surfaces of the insulating layer,
Forming a printed circuit pattern by plating using metal layers of the upper and lower carriers as seed layers, and
And etching the exposed base metal layer using the printed circuit pattern. 9. The method of claim 8,
The etching of the base metal layer may include a flash etching process.

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