KR20090130605A - Chip embedded printed circuit board and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A chip-embedded printed circuit board and a manufacturing method thereof are provided to simplify a process by laminating a copper clad layer including an insulation layer. CONSTITUTION: A chip including a plurality of pads is embedded to a core substrate(10). The core substrate includes a circuit pattern. An insulation layer(34) is laminated to a top part and a bottom part of the core substrate. A plurality of conductive bumps connected to the circuit pattern and the pads is formed to the insulation layer. A copper clad pattern is formed to a surface of the insulation layer in order to be connected to the conductive bumps. A filler(22) is filled between the chip and a cavity, and fixes the chip.

Description

Chip embedded printed circuit board and manufacturing method thereof

The present invention relates to a chip-embedded printed circuit board and a method of manufacturing the same, and more particularly, an insulating layer having a conductive bump corresponding to a pad of the chip and a circuit pattern of the core board penetrated above and below the core board on which the chip is embedded. The present invention relates to a chip-embedded printed circuit board and a method of manufacturing the same.

In recent years, in response to the demand for high performance and miniaturization of electronic devices, electronic components have become higher density and higher performance. Accordingly, the demand for small printed circuit boards capable of high density mounting of electronic components is increasing. In response to this demand, development of multilayer circuit boards which electrically connect wirings formed on different layers or between electronic components and wirings through via holes has been developed.

Such a multilayer circuit board not only shortens the wiring connecting the electronic components, but also has the advantage of realizing high density wiring. In addition, due to the mounting of electronic components, the surface area of the printed circuit board is not only widened, but also has excellent electrical characteristics.

In particular, an embedded printed circuit board in which an electronic component is inserted into a substrate is not mounted on the surface of the printed circuit board, but is embedded in the substrate, so that the board can be made smaller, higher in density, and higher in performance. Is gradually increasing.

Conventional chip-embedded printed circuit boards attach a perforated core substrate to a carrier film and then position the chip, and laminate an insulating layer such as a prepreg on the opposite side of the surface on which the carrier film is attached. After lamination, the carrier film is peeled off. Thereafter, the prepreg layer is also laminated on the surface from which the carrier film is peeled off.

Thereafter, via holes are formed in portions requiring electrical connection through a laser drill method, and copper plating processes are performed.

However, when the via hole is formed through the laser drill method as described above, it is difficult to process the via hole at the correct position due to the position error of the chip or the tolerance of the laser drill. There is a problem.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to penetrate the upper and lower portions of the core board in which the chip is embedded, the conductive bumps corresponding to the pads of the chip and the circuit patterns of the core board. By stacking the copper foil layer having the formed insulating layer on one surface, the via hole forming process can be omitted, thereby simplifying the process, reducing the process cost, and improving the yield and reliability of the product, and the manufacture of the chip embedded printed circuit board. To provide a method.

In accordance with another aspect of the present invention, there is provided a chip-embedded printed circuit board comprising: a core board having a chip having a plurality of pads therein and having a circuit pattern; An insulating layer stacked on upper and lower portions of the core substrate and having a plurality of conductive bumps connected to the circuit pattern and the pad therethrough; And a copper foil pattern formed on a surface of the insulating layer to be connected to the conductive bumps.

Here, a cavity is perforated in a predetermined portion of the core substrate, and the chip may be inserted into the cavity.

The apparatus may further include a filler filled between the chip and the cavity to fix the chip.

In addition, the pad and the conductive bump may be connected one-to-one.

In addition, a method for manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention for achieving the above object includes: drilling a cavity in a core substrate having a circuit pattern; Attaching a carrier film to one surface of the core substrate; Inserting a chip having a plurality of pads into the cavity and fixing the chip on the carrier film; Filling a filler between the cavity and the chip; Removing the carrier film; And first and second copper foil layers provided on one surface of an insulating layer through which a plurality of conductive bumps corresponding to the circuit pattern and the pad pass, are stacked on upper and lower portions of the core substrate. And connecting the conductive bumps to each other.

The pad and the conductive bump may correspond one-to-one.

And forming the conductive bumps on the first copper foil layer and the second copper foil layer before laminating the first copper foil layer and the second copper foil layer; And forming the insulating layer on the first copper foil layer and the second copper foil layer to penetrate the conductive bump to expose an upper end of the conductive bump.

In addition, the conductive bumps may be formed in a conical shape.

The stacking of the first and second copper foil layers may include heating the first and second copper foil layers provided on one surface of the insulating layer through which the conductive bumps are formed, and heating the upper and lower portions of the core substrate. And pressurizing.

The method may further include, after the stacking of the first and second copper foil layers, removing a portion of the first and second copper foil layers to form a copper foil pattern connected to the conductive bumps.

In addition, after the step of forming the copper foil pattern, the step of applying a solder resist on the copper foil pattern; And patterning the solder resist by a photolithography process to expose a portion of the upper surface of the copper foil pattern.

In addition, the conductive bumps may be made of any one of conductive epoxy (epoxy), Ag, Cu, Sn, Au and Sn-based alloy, the Sn-based alloy is made of any one of AuSn, SnSb, SnAg, SnPb, SnBi and SnIn. Can be.

In addition, the pad may be a ball or bump formed of any one of Au, Cu, Sn, and Sn-based alloys.

In addition, the insulating layer may be made of prepreg or Ajinomoto build-up film (ABF).

In addition, another method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention for achieving the above object includes: drilling a cavity in a core substrate having a circuit pattern; Attaching a carrier film to a lower surface of the core substrate; Inserting a chip having a plurality of pads into the cavity and fixing the chip on the carrier film; Filling a filler between the cavity and the chip; Stacking a first copper foil layer provided on one surface of an insulating layer having a plurality of conductive bumps corresponding to the circuit pattern on the top surface of the core substrate, and connecting the conductive bumps to the circuit pattern; Removing the carrier film; And a second copper foil layer provided on one surface of an insulating layer having a plurality of conductive bumps corresponding to the pad and the circuit pattern formed on a lower surface of the core substrate, thereby forming the conductive bumps on the pad and the circuit pattern. Connecting; may include.

As described above, according to the chip-embedded printed circuit board according to the present invention and a method for manufacturing the same, only a copper foil layer having one surface with an insulating layer formed with a plurality of conductive bumps formed thereon is laminated on a chip-embedded core board. Therefore, since the electrical connection between layers can be made, it is possible to provide a low-cost chip embedded printed circuit board by simplifying the process and reducing the process cost by omitting the existing via hole forming process for interlayer connection. have.

In addition, the present invention has the effect of improving the manufacturing yield and reliability of the chip embedded printed circuit board.

Matters relating to the operational effects including the technical configuration of the chip embedded printed circuit board and the manufacturing method according to the present invention for the above object will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. .

Structure of chip embedded printed circuit board

Referring to Figure 1 will be described in detail a chip embedded printed circuit board according to an embodiment of the present invention.

1 is a cross-sectional view illustrating a structure of a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a chip embedded printed circuit board according to an embodiment of the present disclosure includes a core in which a chip 20 having a plurality of pads 21 is embedded and a circuit pattern 11 is provided on a surface thereof. A plurality of substrates 10 and a plurality of stacked upper and lower portions of the core substrate 10 and connected to a circuit pattern 11 on the surface of the core substrate 10 and pads 21 on the surface of the chip 20. An insulating layer 34 through which the conductive bumps 33 are formed, and first and second copper foil patterns 31a and 32a formed on the surface of the insulating layer 34 so as to be connected to the conductive bumps 33.

A solder resist 40 is formed on the first and second copper foil patterns 31a and 32a to expose a portion of the top surface of the first and second copper foil patterns 31a and 32a.

The solder resist 40 serves as a film that covers portions of the first and second copper foil patterns 31a and 32a to prevent unwanted connection by soldering when the parts are mounted.

A cavity 12 is perforated in a predetermined portion of the core substrate 10, and the chip 20 is inserted into the cavity 12. In this case, the chip 20 may be an active device, a passive device, or an IC.

The core substrate 10 may play a role of releasing heat generated from the chip 20 to the outside, and for this purpose, the core substrate 10 may be made of a metal material such as copper (Cu) or aluminum (Al).

In addition, the circuit pattern 11 on the surface of the core substrate 10 may be made of a conductive material such as copper.

A filler 22 is filled between the cavity 12 and the chip 20 to fix the chip 20. Resin, epoxy, or prepreg may be used as the filler 22.

In particular, the chip embedded printed circuit board according to the embodiment of the present invention, as described above, the insulating layer 34 having the conductive bumps 33 penetrated through the upper and lower portions of the core substrate 10 having the chip 20 embedded therein. By laminating, the pad 21 of the chip 20 and the circuit pattern 11 of the core substrate 10 may be connected to the first and second copper foil patterns 31a and 32a which are external circuit patterns.

That is, in order to electrically connect the pad 21 of the chip 20 and the circuit pattern 11 on the surface of the core substrate 10 to an external circuit pattern or the like, the core substrate 10 having the chip 20 thereon is mounted on the core substrate 10. After the lamination of the insulating layer 34 such as prepreg and the like, the via holes are formed by laser drilling or the like. Therefore, it is difficult to process the via holes at the correct positions when the via holes are formed. Although there was a problem, in the embodiment of the present invention, only the insulating layer 34 on which the conductive bumps 33 are formed is laminated on the core substrate 10 having the chip 20 therein, so that electrical connection necessary between layers is achieved. By eliminating the existing via hole forming process, simplifying the process and reducing the process cost, it is possible to provide a low cost chip embedded printed circuit board and improve the manufacturing yield and reliability of the product.

In this case, the conductive bumps 33 may be formed to be connected in a one-to-one manner with the pad 21 provided in the chip 20.

The conductive bumps 33 may be made of a conductive epoxy, Ag, Cu, Sn, Au, or a Sn-based alloy having a low melting point. Here, AuSn, SnSb, SnAg, SnPb, SnBi, SnIn, or the like may be used as the Sn-based alloy.

The pad 21 may be formed of Au, Cu, Sn, a low melting point or high melting point Sn-based alloy, or the like, and may be formed in a ball or bump form.

In addition, the insulating layer 34 having the conductive bumps 33 penetrated therein may be made of a prepreg or an Ajinomoto build-up film (ABF).

Manufacturing method of chip embedded printed circuit board

Hereinafter, a method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 14.

2 to 11 are cross-sectional views sequentially illustrating a method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2, the cavity 12 is drilled in the core substrate 10 provided with the circuit pattern 11. The cavity 12 may be formed by various methods such as pressing, drilling, or laser machining.

Then, as shown in FIG. 3, the carrier film 100 is attached to one surface of the core substrate 10.

Next, as shown in FIG. 4, the chip 20 having the plurality of pads 21 is inserted into the cavity 12 to be fixed to the carrier film 100.

The carrier film 100 is for fixing the chip 20 inserted into the cavity 12, and a double-sided tape may be used.

Next, as shown in FIG. 5, the filler 22 is filled between the cavity 12 and the chip 20. The filler 22 may generally be made of resin, epoxy, or prepreg.

Thereafter, as shown in FIG. 6, the carrier film 100 is removed.

Next, as shown in FIG. 7, first copper foil layers and second copper foil layers 31 and 32 are prepared, respectively, and then one surface of the first and second copper foil layers 31 and 32 is prepared. A plurality of conductive bumps 33 are formed in the grooves.

The conductive bump 33 is for connecting the circuit pattern 11 of the core substrate 10 and the pad 21 of the chip 20 with an external circuit pattern, and thus the circuit pattern 11 and the pad ( It may be formed at a position corresponding to 21). In particular, the conductive bumps 33 to be connected to the pads 21 of the chip 20 may be formed to correspond one-to-one with the pads 21.

Then, an insulating layer 34 is formed on the first and second copper foil layers 31 and 32 to expose the upper end of the conductive bump 33 through the conductive bump 33. The insulating layer 34 may be formed using a prepreg, an Ajinomoto build-up film (ABF), or the like. In addition, the insulating layer 34 may be formed on the first and second copper foil layers 31 and 32 using a sheet type.

Here, the conductive bumps 33 have a pointed shape, for example, so that the insulating layer 34 penetrates the conductive bumps 33 and is formed on the first and second copper foil layers 31 and 32. It may be formed in a conical shape or the like.

Next, as shown in FIG. 8, the first and second surfaces having an insulating layer 34 formed on one surface of the core substrate 10 through which the plurality of conductive bumps 33 penetrate. Copper foil layers 31 and 32 are arrange | positioned. In this case, the exposed upper end of the conductive bumps 33 are disposed to face the core substrate 10.

Then, as illustrated in FIG. 9, the core substrate 10, the conductive bumps 33, and the first and second copper foil layers 31 and 32 on which the insulating layer 34 are formed are collectively stacked. After that, heating and pressurization are performed to connect the conductive bumps 33 to the circuit pattern 11 and the pad 21.

As described above, according to the exemplary embodiment of the present invention, the upper and lower portions of the core substrate 10 in which the chip 20 is embedded, the copper foil layers having the insulating layer 34 formed therethrough with the conductive bumps 33 formed on one surface thereof ( 31, 32) only by the process of stacking the electrical connection can be made between the layers, there is an advantage that can simplify the manufacturing process of the chip embedded printed circuit board.

Next, as shown in FIG. 10, portions of the first and second copper foil layers 31 and 32 are removed to connect the first and second copper foil patterns 31 a and second to the conductive bumps 33. The copper foil pattern 32a is formed.

Thereafter, as shown in FIG. 11, the solder resist 40 is coated on the first and second copper foil patterns 31 a and 32 a, and then the first and second copper foil patterns 31 a and 32 a are removed. The solder resist 40 is patterned by a photolithography process to expose a portion of the top surface.

Meanwhile, as described above, instead of stacking the core substrate 10 and the first and second copper foil layers 31 and 32 at the same time, it is possible to stack them sequentially. This will be described with reference to FIGS. 2 to 5 and 12 to 14.

12 to 14 are cross-sectional views sequentially illustrating a method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2, the cavity 12 is drilled in the core substrate 10 having the circuit pattern 11, and as shown in FIG. 3, a carrier is formed on the lower surface of the core substrate 10. The film 100 is attached.

Then, as shown in FIG. 4, the plurality of pads 21 are inserted into the cavity 12 by the chip 20 provided on the lower surface and fixed on the carrier film 100. As shown, the filler 22 is filled between the cavity 12 and the chip 20.

Next, as shown in FIG. 12, an insulating layer having a plurality of conductive bumps 33 penetrated through the upper surface of the core substrate 10 and corresponding to the circuit pattern 11 formed on the upper surface of the core substrate 10. The first copper foil layer 31 provided on one surface of 34 is laminated, heated, and pressed to connect the conductive bumps 33 to the circuit pattern 11.

Thereafter, as shown in FIG. 13, the carrier film 100 is removed.

Then, as shown in Figure 14, the carrier film 100 is removed to expose the lower surface of the core substrate 100, the pad 21 of the chip 20 and the lower surface of the core substrate 10 The pad 21 and the second copper foil layer 32 provided on one surface of the insulating layer 34 through which the plurality of conductive bumps 33 are formed. The conductive bumps 33 are connected to the circuit pattern 11.

In the stacking order of the copper foil layers 31 and 32, as described above, the first copper foil layer 31 is first stacked on the core substrate 10, and then, the first copper foil layer 31 is stacked on the bottom of the core substrate 10. 2 may be laminated on the copper foil layer 32. On the contrary, the second copper foil layer 32 may be stacked below the core substrate 10, and then the first copper foil layer 31 may be stacked on the core substrate 10. The process may be carried out in the order of lamination on the top). However, when the second copper foil layer 32 is first stacked on the lower portion of the core substrate 10, the carrier film 100 may be attached to the upper surface of the core substrate 10.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 is a cross-sectional view showing the structure of a chip embedded printed circuit board according to an embodiment of the present invention.

2 to 11 are cross-sectional views sequentially illustrating a method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

12 to 14 are process cross-sectional views sequentially shown to explain another method for manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: core substrate 11: circuit pattern

12: cavity 20: chip

21: Pad 22: Filler

31: first copper foil layer 31a: first copper foil pattern

32: second copper foil layer 32a: second copper foil pattern

33: conductive bump 34: insulating layer

40: solder resist 100: carrier film

Claims (17)

A core board having a chip having a plurality of pads therein and provided with a circuit pattern; An insulating layer stacked on upper and lower portions of the core substrate and having a plurality of conductive bumps connected to the circuit pattern and the pad therethrough; And A copper foil pattern formed on a surface of the insulating layer to be connected to the conductive bumps; Chip embedded printed circuit board comprising a. The method of claim 1, A cavity is formed in a predetermined portion of the core substrate, the chip embedded printed circuit board in which the chip is inserted into the cavity. The method of claim 2, A filler filling between the chip and the cavity to fix the chip; Chip embedded printed circuit board further comprising. The method of claim 1, And the pad and the conductive bump are connected one-to-one. Drilling a cavity in a core substrate provided with a circuit pattern; Attaching a carrier film to one surface of the core substrate; Inserting a chip having a plurality of pads into the cavity and fixing the chip on the carrier film; Filling a filler between the cavity and the chip; Removing the carrier film; And On the upper and lower portions of the core substrate, first and second copper foil layers provided on one surface of an insulating layer having a plurality of conductive bumps corresponding to the circuit patterns and the pads are stacked thereon, and the first and second copper foil layers are formed on the circuit patterns and the pads. Connecting the conductive bumps; Manufacturing method of a chip embedded printed circuit board comprising a. The method of claim 5, The pad and the conductive bump corresponds to a one-to-one manufacturing method of a chip embedded printed circuit board. The method of claim 5, Before laminating the first copper foil layer and the second copper foil layer, Forming the conductive bumps on the first copper foil layer and the second copper foil layer; And Forming the insulating layer on the first copper foil layer and the second copper foil layer to expose the upper end of the conductive bump through the conductive bump; Manufacturing method of a chip embedded printed circuit board further comprising. The method of claim 7, wherein The conductive bump is a manufacturing method of a chip embedded printed circuit board is formed in a conical shape. The method of claim 5, Laminating the first and second copper foil layer, Fabrication of a chip embedded printed circuit board comprising the steps of heating and pressurizing the first and second copper foil layers provided on one surface of the insulating layer through which the conductive bumps penetrate the upper and lower portions of the core substrate. Way. The method of claim 5, After laminating the first and second copper foil layers, Removing portions of the first and second copper foil layers to form a copper foil pattern connected to the conductive bumps; Manufacturing method of a chip embedded printed circuit board further comprising. The method of claim 10, After forming the copper foil pattern, Applying a solder resist on the copper foil pattern; And Patterning the solder resist by a photolithography process to expose a portion of the top surface of the copper foil pattern; Manufacturing method of a chip embedded printed circuit board further comprising. The method of claim 5, The conductive bump is a manufacturing method of a chip embedded printed circuit board made of any one of a conductive epoxy (epoxy), Ag, Cu, Sn, Au and Sn-based alloy. The method of claim 12, The Sn-based alloy manufacturing method of a chip embedded printed circuit board made of any one of AuSn, SnSb, SnAg, SnPb, SnBi and SnIn. The method of claim 5, Wherein the pad is a ball (ball) or bump formed of any one of Au, Cu, Sn and Sn-based alloy manufacturing method of a chip embedded printed circuit board. The method of claim 5, The insulating layer is a method for manufacturing a chip embedded printed circuit board made of prepreg or Ajinomoto build-up film (ABF). Drilling a cavity in a core substrate provided with a circuit pattern; Attaching a carrier film to a lower surface of the core substrate; Inserting a chip having a plurality of pads into the cavity and fixing the chip on the carrier film; Filling a filler between the cavity and the chip; Stacking a first copper foil layer provided on one surface of an insulating layer having a plurality of conductive bumps corresponding to the circuit pattern on the top surface of the core substrate, and connecting the conductive bumps to the circuit pattern; Removing the carrier film; And On the lower surface of the core substrate, a second copper foil layer having a surface formed with an insulating layer through which a plurality of conductive bumps corresponding to the pad and the circuit pattern are formed is laminated, and the conductive bump is connected to the pad and the circuit pattern. Making a step; Manufacturing method of a chip embedded printed circuit board comprising a. The method of claim 16, The pad is a manufacturing method of a chip embedded printed circuit board provided on the lower surface of the chip.

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