KR20100028209A

KR20100028209A - Printed circuit board

Info

Publication number: KR20100028209A
Application number: KR1020080087132A
Authority: KR
Inventors: 하재
Original assignee: 삼성전기주식회사
Priority date: 2008-09-04
Filing date: 2008-09-04
Publication date: 2010-03-12

Abstract

PURPOSE: A printed circuit board is provided to prevent the deformation of a substrate due to thermal expansion difference between a chip and the substrate by differently forming the thermal expansion rates of insulation layers. CONSTITUTION: A first insulation layer(20) is formed on the upper side of a core layer(10). The first insulation layer is formed by stacking a plurality of insulation layers with a circuit. The first insulation layer has a preset thermal expansion rate. A second insulation layer(30) is formed on the lower side of the core layer by stacking the plurality of insulation layers with the circuit. The second insulation layer has the thermal expansion rate which is different from the first insulation layer. The thermal expansion rate is in proportion to the circuit area formed on the surface of the first and second insulation layers.

Description

Printed Circuit Board

The present invention relates to a printed circuit board, and more particularly, to a printed circuit board having different thermal expansion coefficients of insulating layers formed on upper and lower portions of a core layer.

As a technology to cope with higher density of semiconductor chips and higher signal transmission speeds, flip chip mounting in which a semiconductor is directly mounted on a substrate instead of a conventional chip size package (CSP) mounting or wire bonding mounting. The demand is growing.

High density and high reliability substrates are required for flip chip mounting. However, in reality, substrate specifications are not comparable with high density of semiconductors, so it is urgent to develop next-generation technologies for the spread of flip chip mounting in the future. The requirements for flip chip mounting boards are closely related to the high-speed, advanced, and semiconductor specifications of the electronics market, and present many challenges such as miniaturization of circuits, high electrical characteristics, high reliability, high-speed signal transmission structure, and high functionality.

In the conventional method for manufacturing a flip chip mounted printed circuit board, after through holes are formed in a thin core material, the through holes are plugged with ink or the like, and then copper plating and A circuit is formed in the core layer through an etching process or the like.

As described above, the insulating layer formation, the micro via formation, and the circuit formation are repeated on both surfaces of the core layer on which the circuit is formed, thereby manufacturing a substrate having a multilayer structure.

Here, the material used as the insulating layer formed on both sides of the core layer is the same material on both sides, the inorganic filler (dispersed) or the glass cloth (polymer glass) and the polymer resin laminated on the basis of the polymer resin Is used.

However, since the conventional printed circuit board uses a thin core, the strength of the substrate is low, and when the chip is mounted using solder on the substrate, the substrate is bent due to the difference in thermal expansion coefficient between the chip and the substrate. The reliability of the package may be degraded.

In addition, because the thin core is used as described above, when the strength of the substrate is low and there is a difference in the copper foil circuit area between the upper and lower surfaces of the substrate, the thermal expansion coefficient between the upper and lower surfaces of the substrate during solder bump reflow causes the substrate to be separated. There is a problem that the mounting failure of the chip occurs by bending.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to prevent the warpage of the substrate generated during the heat treatment of the substrate due to the difference in thermal expansion coefficient according to the difference in the copper foil circuit area of the upper and lower core layer, and the chip It is to provide a printed circuit board that can improve the mounting failure caused by the bending of the substrate at the time of mounting.

A printed circuit board according to an embodiment of the present invention for achieving the above object, the core layer; A first insulating layer formed on the core layer and having a plurality of insulating layers having a circuit formed on the surface thereof, the first insulating layer having a predetermined coefficient of thermal expansion; And a second insulating layer formed under the core layer and having a plurality of insulating layers having a circuit formed on the surface thereof, and having a thermal expansion coefficient different from that of the first insulating layer.

Here, when the circuit formed on the surface of the first insulating layer has a smaller area than the circuit formed on the surface of the second insulating layer, the first insulating layer may have a lower coefficient of thermal expansion than the second insulating layer.

In addition, some or all of the insulating layers constituting the first insulating layer may have a lower coefficient of thermal expansion than the second insulating layer.

In addition, the first insulating layer may be made of an insulating resin having a lower coefficient of thermal expansion than the second insulating layer.

In addition, a first filler and a second filler are respectively filled in the first insulating layer and the second insulating layer, and the first filler may have a lower coefficient of thermal expansion than the second filler.

In addition, the first filler and the second filler are filled in the first filler and the second filler, respectively, and the first filler may be filled at a higher filling rate than the second filler.

In addition, the first insulating layer may be impregnated with resin in the inorganic fiber to have a lower coefficient of thermal expansion than the second insulating layer.

In addition, the first insulating layer may be impregnated with a resin in the nonwoven fabric to have a lower coefficient of thermal expansion than the second insulating layer.

In addition, the first circuit and the second circuit may be made of copper foil.

The semiconductor device may further include a chip mounted on the first insulating layer, and the first insulating layer may have a lower coefficient of thermal expansion than the second insulating layer.

In addition, a printed circuit board according to another embodiment of the present invention for achieving the above object, the core layer; A first insulating layer formed on one surface of the core layer and having a circuit formed on the surface thereof and having a predetermined coefficient of thermal expansion; And a second insulating layer formed on the first insulating layer and having a circuit formed on a surface thereof, the second insulating layer having a coefficient of thermal expansion different from that of the first insulating layer.

The semiconductor device may further include a chip mounted on the second insulating layer.

As described above, according to the printed circuit board according to the present invention, the thermal expansion coefficients of the first insulating layer and the second insulating layer, which are respectively stacked on the upper and lower portions of the core layer, are different from each other, so that the first and second insulating layers are different from each other. Due to the difference in thermal expansion coefficients of the upper and lower substrates according to the difference in the area of the copper foil circuit formed on the surface of the layer, it is possible to prevent the bending deformation occurring during the heat treatment of the substrate.

In addition, as described above, by varying the thermal expansion coefficient of each insulating layer constituting the upper and lower portions of the substrate, the bending deformation of the substrate caused by the difference in thermal expansion coefficient between the chip and the substrate when mounting the chip on the substrate is eliminated. You can prevent it.

In addition, in the present invention, the thermal expansion coefficients of the first and second insulating layers laminated on one surface of the core layer are different from each other, so that the thermal expansion coefficient difference according to the circuit area difference formed on the surfaces of the first and second insulating layers is different. Therefore, it is possible to prevent the bending deformation generated during the heat treatment of the substrate.

Therefore, the present invention can improve the flatness of a printed circuit board, thereby reducing the mounting failure rate of various components such as chips, and can improve the reliability of the product.

Matters relating to the operational effects including the technical configuration of the printed circuit board according to the present invention will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

1 to 4 will be described in detail with respect to the printed circuit board according to an embodiment of the present invention.

First, Figures 1 and 2 are cross-sectional views showing a printed circuit board according to an embodiment of the present invention.

As shown in FIG. 1, the printed circuit board 100 according to the exemplary embodiment of the present invention is formed on the core layer 10 and on the core layer 10, and has a first circuit 20a on the surface thereof. First insulating layer 20 formed by stacking a plurality of insulating layers 21 and 22 formed thereon, and a plurality of insulating layers formed under the core layer 10 and having a second circuit 30a formed on a surface thereof. The second insulating layer 30 is formed by laminating (31,32).

The first circuit 20a and the second circuit 30a may be made of copper foil or the like.

The core layer 10 may be formed of a copper clad laminate (CCL) in which copper foil 10a is laminated on both surfaces of the insulating layer 10b.

The copper clad laminated board is a laminated board in which a copper foil 10a is coated on an insulating layer 10b, which is generally a printed circuit board, and is made of glass / epoxy copper clad laminate, heat-resistant resin copper clad laminate, and paper / phenol copper clad laminate according to its use. There are many kinds of high-frequency copper-clad laminates, flexible copper-clad laminates (polyimide films), and composite copper-clad laminates, but glass / epoxy copper-clad laminates are mainly used for the production of double-sided printed circuit boards and multilayer printed circuit boards.

The glass / epoxy copper clad laminate is made of a reinforcing base material and copper foil in which an epoxy resin is infiltrated into the glass fiber. Glass / epoxy copper clad laminates are classified according to reinforcement materials. Generally, grades according to reinforcement materials and heat resistance are determined by standards set by the National Electrical Manufacturers Association (NEMA) such as FR-1 to FR-5. have. Among these grades, FR-4 is most commonly used, but in recent years, the demand for FR-5, which has improved the glass transition temperature (Tg) characteristics of resins, has also increased.

In the core layer 10 formed of the copper-clad laminate, a through hole 15 for interlayer connection is formed. The through hole 15 may be formed by mechanical drilling, or may be formed by a YAG laser, a CO ₂ laser, or the like.

The paste 15a is filled in the through hole 15. At this time, before the paste 15a is filled, the copper plating layer 15b may be formed on the inner surface of the through hole 15. The copper plating layer 15b may be formed by sequentially performing electroless copper plating and electrolytic copper plating.

Here, the paste 15a generally uses an insulating ink material, but a conductive paste may also be used according to the purpose of using the printed circuit board. In this case, the conductive paste may be a main component of the metal, such as Cu, Ag, Au, Sn and Pb mixed with an organic adhesive in the form of a single or alloy.

Vias 25 and 35 for interlayer circuit connection are formed in the insulating layers 21, 22, 31, and 32 constituting the first insulating layer 20 and the second insulating layer 30.

On the first insulating layer 20 and the second insulating layer 30, a circuit portion to be used as a mounting pad of a chip (see "50" in FIG. 4), for example, the surface of the first insulating layer 20 A solder resist layer 60 exposing a portion of the upper surface of the first circuit 20a formed therein is formed.

And the solder bump 40 connected with the said 1st circuit 20a is formed on the said 1st circuit 20a in which the said soldering resist layer 60 was not formed.

On the solder bumps 40, the chips 50 are mounted by flip chip bonding or the like.

In particular, in the printed circuit board 100 according to the embodiment of the present invention, the first insulating layer 20 has a predetermined thermal expansion rate, for example, a thermal expansion rate of 20 to 100 ppm / ° C., and the second insulating layer 30 preferably has a different coefficient of thermal expansion from the first insulating layer 20.

At this time, the first and second circuits 20a and 30a made of copper foil are formed on both surfaces of the printed circuit board 100, and the copper foils of the first and second circuits 20a and 30a are formed. This area occupies most cases where the upper surface and the lower surface of the board | substrate 100 are not mutually the same and different.

For example, as shown in FIG. 1, the first circuit 20a formed on the surface of the first insulating layer 20 on the core layer 10 is the second insulating layer under the core layer 10. The area may be smaller than that of the second circuit 30a formed on the surface of the substrate 30.

In this case, the first insulating layer 20 preferably has a lower coefficient of thermal expansion than the second insulating layer 30.

In this case, the entirety of the plurality of insulating layers 21 and 22 constituting the first insulating layer 20 may have a lower coefficient of thermal expansion than the second insulating layer 30, but the first insulating layer 20 Some insulating layers among the plurality of insulating layers 21 and 22 may have a lower coefficient of thermal expansion than the second insulating layer 30.

In order for the first insulating layer 20 to have a lower thermal expansion rate than the second insulating layer 30, insulating resins having different thermal expansion rates may be used. That is, as the first insulating layer 20, an insulating resin having a lower coefficient of thermal expansion than the second insulating layer 30 can be used.

In addition, as a method for making the first insulating layer 20 have a lower coefficient of thermal expansion than the second insulating layer 30, there are the following methods in addition to the use of different types of insulating resins as described above. .

First, a filler is generally filled in the first and second insulating layers 20 and 30 stacked on the printed circuit board 100. In this case, as shown in FIG. 2, the first insulating layer ( 20 is referred to as a first filler 23 and a second filler 33 to be filled in the second insulating layer 30, the first and second fillers 23, 33 are mutually The first filler 23 may be made of a filler having a lower coefficient of thermal expansion than the second filler 33, rather than the same filler.

That is, the first insulating layer 20 is different from the second insulating layer 30 by using different types of fillers as the fillers 23 and 33 constituting the first and second insulating layers 20 and 30. To have a low coefficient of thermal expansion.

In addition, instead of using different types of fillers for the first and second fillers 23 and 33, the same fillers may be used as the first and second fillers 23 and 33, but the first insulating layer ( The filling rate of the first filler 23 filled in 20 may be higher than the filling rate of the second filler 33 filled in the second insulating layer 30.

In general, the purpose of using the filler to be filled in the insulating resin is to reduce the thermal expansion rate and curing shrinkage rate of the resin, and to control the heat generation during curing, and the like, so that the first and second insulating layers 20, In the case of using the same filler 30), the thermal expansion rate of the first insulating layer 20 may be reduced as the filling rate of the first filler 23 is increased.

In addition, the first insulating layer 10 may have a thermal expansion coefficient lower than that of the second insulating layer 20 by impregnating a resin in an inorganic fiber such as a glass cloth or a resin in a nonwoven fabric. Can be.

According to the printed circuit board 100 according to the embodiment of the present invention, among the first and second insulating layers 20 and 30 formed on the upper and lower portions of the substrate 100, the copper foil circuit area formed on the surface is further increased. The smaller the first insulating layer 20 has a lower coefficient of thermal expansion than the second insulating layer 30, thereby reflowing the solder bumps 40 formed on the printed circuit board 100. There is an effect that can prevent the warpage phenomenon.

Figure 3 is a schematic diagram showing that the bending is suppressed during solder bump reflow of the printed circuit board according to an embodiment of the present invention, the length of the arrow shown in Figure 3 shows the relative magnitude of the thermal expansion coefficient.

As described above, the area of the first circuit 20a formed on the surface of the first insulating layer 20 on the printed circuit board 100 is formed on the surface of the second insulating layer 30 below the printed circuit board 100. When the area of the second circuit 30a is smaller than the area of the second circuit 30a, since the thermal expansion coefficient of the upper portion of the printed circuit board 100 is large, as shown in FIG. 3, the warpage of the substrate 100 may occur due to heat during the reflow of the solder bumps 40. May occur.

Therefore, in the exemplary embodiment of the present invention, the first insulating layer 20 constituting the upper portion of the printed circuit board 100 has a lower thermal expansion coefficient than the second insulating layer 30, so that the printed circuit board 100 The thermal expansion coefficient balance of the upper surface and the lower surface of the c) may be matched, and thus the curvature of the substrate 100 may be suppressed.

In addition, Figure 4 is a schematic diagram showing that the curvature is suppressed when mounting the chip on a printed circuit board according to an embodiment of the present invention.

As shown in FIG. 4, when the chip 50 is mounted on the first insulating layer 20 of the printed circuit board 100, the thermal expansion coefficient of the printed circuit board 100 may be reduced. Since the thermal expansion coefficient is greater than that, when the chip 50 is mounted and subjected to heat treatment, warpage of the substrate 100 may occur.

In order to suppress such warpage, in the embodiment of the present invention, the first insulating layer 20 on which the chip 50 is mounted has a lower coefficient of thermal expansion than the second insulating layer 30 so that the chip 50 and In addition, the thermal expansion coefficient balance of the upper and lower surfaces of the printed circuit board 100 may be adjusted.

As described above, according to the exemplary embodiment of the present invention, the thermal expansion coefficients of the first and second insulating layers 20 and 30 stacked on the upper and lower portions of the core layer 10 are different from each other, so that the upper and lower portions of the core layer 10 are different. Due to the difference in thermal expansion coefficient due to the circuit area difference formed on the surfaces of the first and second insulating layers 20 and 30, the bending deformation of the substrate 100 generated during heat treatment of the substrate 100 or the substrate 100 When mounting the chip 50 on the surface, it is possible to prevent the bending deformation of the substrate 100 due to the difference in thermal expansion coefficient between the chip 50 and the substrate 100.

Therefore, according to the exemplary embodiment of the present invention, the flatness of the substrate 100 may be improved to reduce mounting failure rates of various components such as chips, thereby improving reliability of the product.

Next, a printed circuit board according to another exemplary embodiment of the present invention will be described in detail with reference to FIG. 5.

5 is a cross-sectional view illustrating a printed circuit board according to another exemplary embodiment of the present invention.

As shown in FIG. 5, the printed circuit board according to another embodiment of the present invention has the same configuration as that of the printed circuit board according to the embodiment of the present invention, except that the insulating layer of the printed circuit board 200 ( 20 and 30 are different from the embodiment of the present invention only in that they are laminated on one surface of the core layer 10 and not on the top and bottom of the core layer 10.

That is, in the printed circuit board 200 according to another embodiment of the present invention, the core layer 10 and the core layer 10 are formed on one surface, and the first circuit 20a is formed on the surface thereof. It is formed on the first insulating layer 20 and the first insulating layer 20 having a coefficient of thermal expansion, the second circuit 30a is formed on the surface and different from the first insulating layer 20 And a second insulating layer 30 having.

In the first insulating layer 20 and the second insulating layer 30, vias 25 and 35 for interlayer circuit connection are formed, respectively.

On the second insulating layer 30, a portion of a circuit to be used as a mounting pad of the chip 50, for example, a portion of the upper surface of the second circuit 30a formed on the surface of the second insulating layer 30 is exposed. A solder resist layer 60 is formed. The solder resist 60 may also be formed under the core layer 10.

On the second circuit 30a exposed by the solder resist layer 60, a solder bump 40 connected to the second circuit 30a is formed.

The chip 50 may be mounted on the solder bump 40 by a flip chip bonding method.

In particular, in the printed circuit board 200 according to another embodiment of the present invention, the first circuit 20a and the second circuit formed on the surface of the first insulating layer 20 and the second insulating layer 30, respectively. The areas of the circuit 30a may not be the same and may be different from each other. For example, when the area of the first circuit 20a is smaller than that of the second circuit 30a, the first insulating layer 20 may be formed. It is preferable to have a thermal expansion coefficient lower than the 2 insulating layer 30.

The printed circuit board 200 according to another embodiment of the present invention may have the same effect as the printed circuit board 100 according to the embodiment of the present invention.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 and 2 are cross-sectional views showing a printed circuit board according to an embodiment of the present invention.

Figure 3 is a schematic diagram showing that the bending is suppressed during solder bump reflow of the printed circuit board according to the embodiment of the present invention.

Figure 4 is a schematic diagram showing that the bending is suppressed when mounting the chip on a printed circuit board according to an embodiment of the present invention.

5 is a cross-sectional view showing a printed circuit board according to another embodiment of the present invention.

10: core layer 10a: copper foil

10b: insulation layer 15: through hole

15a: paste 15b: copper plating layer

20: first insulating layer 30: second insulating layer

20a: first circuit 30a: second circuit

21,22,31,32: Insulation layer 25,35: Via

23,33: filler 40: solder bumps

50: chip 60: solder resist layer

100,200: printed circuit board

Claims

Core layer;

A first insulating layer formed on the core layer and having a plurality of insulating layers having a circuit formed on the surface thereof, the first insulating layer having a predetermined coefficient of thermal expansion; And

A second insulating layer formed under the core layer and having a plurality of insulating layers having a circuit formed on the surface thereof, the second insulating layer having a coefficient of thermal expansion different from that of the first insulating layer;

Printed circuit board comprising a.

The method of claim 1,

And a circuit formed on the surface of the first insulating layer having a smaller area than a circuit formed on the surface of the second insulating layer, wherein the first insulating layer has a lower coefficient of thermal expansion than the second insulating layer.

The method of claim 2,

A printed circuit board having a part or whole of the insulating layer constituting the first insulating layer has a lower coefficient of thermal expansion than the second insulating layer.

The method of claim 3,

The first insulating layer is a printed circuit board made of an insulating resin having a lower coefficient of thermal expansion than the second insulating layer.

The method of claim 3,

The first insulating layer and the second insulating layer is filled in the first filler (filler) and the second filler, respectively, wherein the first filler has a lower thermal expansion coefficient than the second filler.

The method of claim 3,

And a first filler and a second filler respectively filled in the first insulating layer and the second insulating layer, and the first filler is filled at a higher filling rate than the second filler.

The method of claim 3,

The first insulating layer is a printed circuit board having a thermal expansion coefficient lower than the second insulating layer by impregnating the resin into the inorganic fiber.

The method of claim 3,

The first insulating layer is a printed circuit board having a non-woven fabric resin impregnated with a lower coefficient of thermal expansion than the second insulating layer.

The method of claim 1,

The first circuit and the second circuit is a printed circuit board made of copper foil.

The method of claim 1,

And a chip mounted on the first insulating layer, wherein the first insulating layer has a lower coefficient of thermal expansion than the second insulating layer.

Core layer;

A first insulating layer formed on one surface of the core layer and having a circuit formed on the surface thereof and having a predetermined coefficient of thermal expansion; And

A second insulating layer formed on the first insulating layer and having a circuit formed on a surface thereof, the second insulating layer having a coefficient of thermal expansion different from that of the first insulating layer;

Printed circuit board comprising a.

The method of claim 11,

The printed circuit board further comprises a chip mounted on the second insulating layer.