TWI832839B - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
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- TWI832839B TWI832839B TW108104700A TW108104700A TWI832839B TW I832839 B TWI832839 B TW I832839B TW 108104700 A TW108104700 A TW 108104700A TW 108104700 A TW108104700 A TW 108104700A TW I832839 B TWI832839 B TW I832839B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- insulating layer
- pad
- circuit board
- printed circuit
- Prior art date
Links
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000011810 insulating material Substances 0.000 claims description 45
- 229910000679 solder Inorganic materials 0.000 claims description 31
- 238000002844 melting Methods 0.000 claims description 28
- 230000008018 melting Effects 0.000 claims description 28
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 5
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 5
- 239000012779 reinforcing material Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 description 63
- 229910052751 metal Inorganic materials 0.000 description 59
- 239000002184 metal Substances 0.000 description 59
- 239000010949 copper Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 239000000758 substrate Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 239000003822 epoxy resin Substances 0.000 description 15
- 229920000647 polyepoxide Polymers 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 14
- 238000007747 plating Methods 0.000 description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000002787 reinforcement Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 229920001940 conductive polymer Polymers 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000004744 fabric Substances 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- 239000011152 fibreglass Substances 0.000 description 3
- 239000004843 novolac epoxy resin Substances 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004844 aliphatic epoxy resin Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004841 bisphenol A epoxy resin Substances 0.000 description 2
- 239000004842 bisphenol F epoxy resin Substances 0.000 description 2
- 229930003836 cresol Natural products 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 239000005007 epoxy-phenolic resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- -1 Au) Chemical class 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/101—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by casting or moulding of conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明是有關於一種印刷電路板。 The invention relates to a printed circuit board.
當要求用於封裝的印刷電路板薄且小時,亦要求該些印刷電路板上形成有精密節距的佈線。可透過無芯法(coreless method)或藉由使用薄的材料來將印刷電路板的厚度控制到最小。此外,可透過經過修改的半加成製程(modified Semi-Additive Process,MSAP)或半加成製程(Semi-Additive Process,SAP)來將佈線的寬度及空間控制成具有精密的節距。 When printed circuit boards used for packaging are required to be thin and small, there is also a requirement to form fine-pitch wiring on these printed circuit boards. The thickness of the printed circuit board can be controlled to a minimum through a coreless method or by using thin materials. In addition, the width and space of the wiring can be controlled to have a precise pitch through a modified Semi-Additive Process (MSAP) or a Semi-Additive Process (SAP).
韓國專利第10-1593280號(2016年2月11日)中闡述了相關技術。 Related technology is described in Korean Patent No. 10-1593280 (February 11, 2016).
本發明旨在提供一種包括精密節距電路的印刷電路板。 The present invention is directed to a printed circuit board including precision pitch circuits.
本發明的態樣提供一種印刷電路板,所述印刷電路板包括:第一絕緣層;第二絕緣層,由撓性材料製成且層疊於所述第一絕緣層上;第一電路,形成於所述第一絕緣層的下表面上且嵌入於所述第一絕緣層中;第二電路,形成於所述第二絕緣層的下表面上且層疊於所述第一絕緣層中;以及第三電路,形成於所述 第二絕緣層的上表面上,其中所述第二電路的節距小於所述第一電路的節距。 An aspect of the present invention provides a printed circuit board, which includes: a first insulating layer; a second insulating layer made of flexible material and laminated on the first insulating layer; and a first circuit forming on the lower surface of the first insulating layer and embedded in the first insulating layer; a second circuit formed on the lower surface of the second insulating layer and laminated in the first insulating layer; and The third circuit, formed in the On the upper surface of the second insulating layer, the pitch of the second circuit is smaller than the pitch of the first circuit.
100:絕緣材料 100:Insulating materials
100a:加強材 100a: Reinforcement material
100b:貫穿通路 100b: Through passage
110:第一絕緣層 110: First insulation layer
120:第二絕緣層 120: Second insulation layer
130:第三絕緣層 130:Third insulation layer
140:第四絕緣層 140:Fourth insulation layer
210:第一電路 210:First circuit
220:第二電路 220: Second circuit
230:第三電路 230:Third circuit
240:第四電路 240: Fourth circuit
250:第五電路 250:Fifth circuit
260:第六電路 260:Sixth Circuit
310:第一通路 310:First Passage
320:第二通路 320:Second channel
330:第三通路 330:Third channel
340:第四通路 340:Fourth channel
350、360:整合式通路 350, 360: Integrated channel
410:第一接墊 410:First pad
420:第二接墊 420:Second pad
430:第三接墊 430:Third pad
440:第四接墊 440:Fourth pad
450:第五接墊 450:Fifth pad
460:第六接墊 460:Sixth pad
500:連接部件 500: Connecting parts
600:阻焊層 600: Solder mask
(a)、(b)、(c)、(d)、(e)、(f)、(g):步驟 (a), (b), (c), (d), (e), (f), (g): steps
D:拆卸型芯 D: Remove the core
M1、M2、M3:金屬層 M1, M2, M3: metal layer
P、P’:導電膏 P, P’: conductive paste
S:晶種金屬層 S: seed metal layer
VH1、VH2、VH3、VH4、VH5、VH5’、VH6、VH7、VH7’:通孔 VH1, VH2, VH3, VH4, VH5, VH5’, VH6, VH7, VH7’: through hole
圖1示出根據本發明的實施例的印刷電路板。 Figure 1 shows a printed circuit board according to an embodiment of the invention.
圖2示出根據本發明的實施例的印刷電路板。 Figure 2 shows a printed circuit board according to an embodiment of the invention.
圖3示出根據本發明的實施例的印刷電路板。 Figure 3 shows a printed circuit board according to an embodiment of the invention.
圖4及圖5示出製造根據本發明的實施例的印刷電路板的方法。 4 and 5 illustrate a method of manufacturing a printed circuit board according to an embodiment of the present invention.
圖6示出製造根據本發明的實施例的印刷電路板的方法。 Figure 6 illustrates a method of manufacturing a printed circuit board according to an embodiment of the invention.
圖7及圖8示出製造根據本發明的實施例的印刷電路板的方法。 7 and 8 illustrate a method of manufacturing a printed circuit board according to an embodiment of the present invention.
提供以下詳細說明以有助於讀者全面地理解本文中所述的方法、設備及/或系統。然而,熟習此項技術者將明瞭本文中所述的方法、設備及/或系統的各種改變、潤飾及等效形式。本文中所述的操作順序僅是實例,並不僅限於本文中所述的實例,而是如熟習此項技術者將明瞭可做出改變,但必須按照特定的次序發生的操作除外。此外,為更清楚且更簡潔起見,可省略對熟習此項技術者所熟知的功能及構造的說明。 The following detailed description is provided to assist the reader in fully understanding the methods, apparatus, and/or systems described herein. However, various modifications, modifications, and equivalents to the methods, apparatus, and/or systems described herein will be apparent to those skilled in the art. The order of operations described herein is an example only, and is not limited to the examples described herein, but as one skilled in the art will understand, changes may be made, except for operations that must occur in a specific order. In addition, descriptions of functions and structures well known to those skilled in the art may be omitted for the sake of clarity and conciseness.
本文中所述的特徵可以不同的形式體現,且不應被理解為僅限於本文中所述的實例。而是,已提供本文中所述的實例,以 使得本發明將是透徹且完整的,且將向熟習此項技術者傳達本發明的全部範疇。 Features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Instead, the examples described in this article have been provided to This disclosure will be thorough and complete, and will fully convey the full scope of the invention to those skilled in the art.
除非另有界定,否則本文中所使用的包括技術用語及科學用語在內的所有用語皆具有與熟習本發明的相關技術者通常所理解的含義相同的含義。在普通字典中受到定義的任何用語應理解為具有在相關技術的背景中的相同含義,且除非另有明確定義,否則不應將所述用語解釋為具有理想化或太過形式化的含義。 Unless otherwise defined, all terms including technical terms and scientific terms used herein have the same meaning as commonly understood by those familiar with the invention. Any term defined in a general dictionary should be understood to have the same meaning in the context of the relevant technology, and unless otherwise explicitly defined, such term should not be interpreted as having an idealized or overly formal meaning.
無論圖號如何,將賦予相同或對應的元件相同的參考編號,且將不再對相同或對應的元件進行任何贅述。在對本發明的說明通篇,當闡述某一相關傳統技術確定與本發明的觀點無關時,將省略有關的詳細說明。可使用諸如「第一」及「第二」等用語來闡述各種元件,但上述元件不應受限於上述用語。上述用語僅用於對一個元件與另一元件進行區分。在附圖中,一些元件可被放大、省略或簡要地說明,且元件的尺寸不一定反映該些元件的實際尺寸。 Regardless of the figure number, the same or corresponding elements will be assigned the same reference numbers, and the same or corresponding elements will not be described again. Throughout the description of the present invention, when the description of a certain related conventional technology is determined to be irrelevant to the viewpoint of the present invention, the relevant detailed description will be omitted. Terms such as "first" and "second" may be used to describe various elements, but the elements described above should not be limited by the above terms. The above terms are only used to distinguish one element from another element. In the drawings, some elements may be exaggerated, omitted, or briefly illustrated, and the sizes of elements do not necessarily reflect the actual sizes of the elements.
在後文中,將參考附圖詳細地闡述本發明的某些實施例。 In the following, certain embodiments of the invention will be explained in detail with reference to the accompanying drawings.
圖1示出根據本發明的實施例的印刷電路板。 Figure 1 shows a printed circuit board according to an embodiment of the invention.
參考圖1,根據本發明的實施例的印刷電路板包括第一絕緣層110、第二絕緣層120、第一電路210、第二電路220及第三電路230。 Referring to FIG. 1 , a printed circuit board according to an embodiment of the present invention includes a first insulation layer 110 , a second insulation layer 120 , a first circuit 210 , a second circuit 220 and a third circuit 230 .
第一絕緣層110是具有絕緣性質且主要由絕緣材料製成的層。第一絕緣層110可由幾乎不具有撓性的剛性材料製成。舉例 而言,環氧樹脂、酚醛樹脂或雙馬來醯亞胺三嗪(bismaleimide triazine,BT)樹脂可用作所述剛性材料。環氧樹脂可以是(但並不限於)例如:萘環氧樹脂、雙酚A型環氧樹脂、雙酚F型環氧樹脂、酚醛清漆環氧樹脂、甲酚酚醛清漆環氧樹脂、橡膠改性環氧樹脂、環型脂族環氧樹脂、矽環氧樹脂、氮環氧樹脂或磷環氧樹脂。 The first insulating layer 110 is a layer that has insulating properties and is mainly made of insulating material. The first insulation layer 110 may be made of a rigid material with little flexibility. Example For example, epoxy resin, phenolic resin or bismaleimide triazine (BT) resin can be used as the rigid material. Epoxy resins may be (but are not limited to), for example: naphthalene epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin, cresol novolac epoxy resin, rubber modified epoxy resin, cyclic aliphatic epoxy resin, silicone epoxy resin, nitrogen epoxy resin or phosphorus epoxy resin.
第一絕緣層110可以是含有纖維加強材(諸如,玻璃纖維織物)的預浸體(Prepreg,PPG)。第一絕緣層110可以是填充有無機填充物(諸如,二氧化矽)的積層膜。味之素積層膜(Ajinomoto Build-up Film,ABF)可用作此積層膜。 The first insulation layer 110 may be a prepreg (PPG) containing fiber reinforcement (such as fiberglass fabric). The first insulating layer 110 may be a laminated film filled with inorganic filler such as silicon dioxide. Ajinomoto Build-up Film (ABF) can be used as this build-up film.
第二絕緣層120是具有絕緣性質且主要由絕緣材料製成的層。第二絕緣層120層疊於第一絕緣層110上,在此種情形中第一絕緣層110與第二絕緣層120彼此接合。 The second insulating layer 120 is a layer that has insulating properties and is mainly made of insulating material. The second insulating layer 120 is stacked on the first insulating layer 110, in which case the first insulating layer 110 and the second insulating layer 120 are bonded to each other.
第二絕緣層120可由具有高撓性的撓性材料製成。聚醯亞胺(polyimide,PI)、液晶聚合物(liquid crystal polymer,LCP)等可用作所述撓性材料。 The second insulation layer 120 may be made of a flexible material with high flexibility. Polyimide (PI), liquid crystal polymer (LCP), etc. can be used as the flexible material.
第一電路210、第二電路220及第三電路230用於傳送電訊號,且可由諸如銅(Cu)、鈀(Pd)、鋁(Al)、鎳(Ni)、鈦(Ti)、金(Au)、鉑(Pt)等金屬製成,或者考慮到該些金屬的導電率而由該些金屬中的一些金屬的合金製成。 The first circuit 210 , the second circuit 220 and the third circuit 230 are used for transmitting electrical signals and may be made of copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold ( It is made of metals such as Au), platinum (Pt), or an alloy of some of these metals in consideration of the conductivity of these metals.
第一電路210、第二電路220及第三電路230可各自由導電配線製成,所述導電配線可被設置為多個。 The first circuit 210, the second circuit 220, and the third circuit 230 may each be made of conductive wiring, and the conductive wiring may be provided in plural numbers.
第一電路210形成於第一絕緣層110的下表面上且嵌入於第一絕緣層110中。由於第一電路210嵌入於第一絕緣層110中,因此第一電路210的除了第一電路210的下表面(亦即,第一電路210的在圖1中放置於下側上的表面)之外的表面皆與第一絕緣層110接觸。與此同時,第一電路210的下表面可位於第一絕緣層110的下表面的更內部。 The first circuit 210 is formed on the lower surface of the first insulation layer 110 and embedded in the first insulation layer 110 . Since the first circuit 210 is embedded in the first insulating layer 110, all other parts of the first circuit 210 except the lower surface of the first circuit 210 (ie, the surface of the first circuit 210 placed on the lower side in FIG. 1) The outer surfaces are all in contact with the first insulating layer 110 . At the same time, the lower surface of the first circuit 210 may be located further inside the lower surface of the first insulation layer 110 .
第二電路220形成於第二絕緣層120的下表面上且嵌入於第一絕緣層110中。第二電路220的上表面(亦即,第二電路220的在圖1中放置於上側上的表面)與第二絕緣層120的下表面接觸,且第二電路220的除了第二電路220的上表面之外的表面皆與第一絕緣層110接觸。 The second circuit 220 is formed on the lower surface of the second insulation layer 120 and embedded in the first insulation layer 110 . The upper surface of the second circuit 220 (that is, the surface of the second circuit 220 placed on the upper side in FIG. 1 ) is in contact with the lower surface of the second insulating layer 120 , and the second circuit 220 is in contact with the lower surface of the second circuit 220 except for the second circuit 220 . All surfaces other than the upper surface are in contact with the first insulating layer 110 .
第三電路230形成於第二絕緣層120的上表面上。第三電路230與第二絕緣層120的上表面接觸且自第二絕緣層120的上表面突出至第二絕緣層120之外。 The third circuit 230 is formed on the upper surface of the second insulation layer 120 . The third circuit 230 is in contact with the upper surface of the second insulation layer 120 and protrudes from the upper surface of the second insulation layer 120 to outside the second insulation layer 120 .
第二電路220的節距小於第一電路210的節距。此外,第二電路220的寬度可小於第一電路210的寬度,且第二電路220的空間可小於第一電路210的空間。 The pitch of the second circuit 220 is smaller than the pitch of the first circuit 210 . In addition, the width of the second circuit 220 may be smaller than the width of the first circuit 210 , and the space of the second circuit 220 may be smaller than the space of the first circuit 210 .
在此,電路的「節距」可指代組成所述電路的導線的中心之間的距離。此外,電路的「寬度」可指代組成所述電路的導線的寬度,且電路的「空間」可指代組成所述電路的導線之間的分離距離(例如,各導線的相對內側之間的距離)。 Here, the "pitch" of a circuit may refer to the distance between the centers of the conductors that make up the circuit. Additionally, the "width" of a circuit may refer to the width of the conductors that make up the circuit, and the "space" of a circuit may refer to the separation distance between the conductors that make up the circuit (e.g., the distance between the opposite inner sides of each conductor). distance).
此外,第三電路230的節距可小於第一電路210的節距。 第三電路230的寬度可小於第一電路210的寬度,且第三電路230的空間可小於第一電路210的空間。 In addition, the pitch of the third circuit 230 may be smaller than the pitch of the first circuit 210 . The width of the third circuit 230 may be smaller than the width of the first circuit 210 , and the space of the third circuit 230 may be smaller than the space of the first circuit 210 .
舉例而言,第二電路220的節距及第三電路230的節距可各自為約20微米,且第一電路210的節距可大於此節距。 For example, the pitch of the second circuit 220 and the pitch of the third circuit 230 may each be about 20 microns, and the pitch of the first circuit 210 may be greater than this pitch.
換言之,第二電路220及第三電路230可形成為較第一電路210密集。此外,第二電路220及第三電路230可形成為較第一電路210精密。 In other words, the second circuit 220 and the third circuit 230 may be formed denser than the first circuit 210 . In addition, the second circuit 220 and the third circuit 230 may be formed more precisely than the first circuit 210 .
參考圖1,根據本發明的實施例的印刷電路板可更包括第一通路310及第二通路320。 Referring to FIG. 1 , the printed circuit board according to the embodiment of the present invention may further include a first via 310 and a second via 320 .
第一通路310是穿透第一絕緣層110以電性連接第一電路210與第二電路220的導電結構。第二通路320是穿透第二絕緣層120以電性連接第二電路220與第三電路230的導電結構。 The first via 310 is a conductive structure that penetrates the first insulating layer 110 to electrically connect the first circuit 210 and the second circuit 220 . The second via 320 is a conductive structure that penetrates the second insulation layer 120 to electrically connect the second circuit 220 and the third circuit 230 .
第一通路310的熔點可低於第一電路210的熔點。第一通路310可由導電膏製成。在此,導電膏可以是含有金屬的膏,或是由導電聚合物製成但不含任何金屬的的膏。膏中所含有的金屬可以是銀(Ag)、錫(Sn)、鎳(Ni)及銅(Cu)中的一者或多者。在實例中,第一電路210可主要由銅製成,且第一通路310可主要由錫製成。導電膏的此實例被填充於通孔中且然後透過迴焊製程或加熱/冷卻製程而被金屬化以成為第一通路310。 The melting point of the first via 310 may be lower than the melting point of the first circuit 210 . The first via 310 may be made of conductive paste. Here, the conductive paste may be a paste containing metal, or a paste made of conductive polymer but not containing any metal. The metal contained in the paste may be one or more of silver (Ag), tin (Sn), nickel (Ni) and copper (Cu). In an example, first circuit 210 may be primarily made of copper, and first via 310 may be primarily made of tin. This example of conductive paste is filled in the via and then metallized through a reflow process or a heating/cooling process to become the first via 310 .
第一通路310的橫截面積可自第一絕緣層110的下表面至第一絕緣層110的上表面增大,在此種情形中第一通路310的縱截面可呈倒置梯形形狀。 The cross-sectional area of the first via 310 may increase from the lower surface of the first insulating layer 110 to the upper surface of the first insulating layer 110 , in which case the longitudinal cross-section of the first via 310 may be in the shape of an inverted trapezoid.
第一電路210可包括第一接墊410,第一接墊410可形成於第一絕緣層110的下表面上以嵌入於第一絕緣層110中,這與第一電路210類似。第一接墊410可形成於組成第一電路210的導線的端部部分處。第一接墊410的厚度可與第一電路210的厚度實質上相同,且第一接墊410的寬度可大於第一電路210的寬度,且第一接墊410的橫截面可近乎是圓形的。 The first circuit 210 may include a first pad 410 , and the first pad 410 may be formed on a lower surface of the first insulating layer 110 to be embedded in the first insulating layer 110 , similar to the first circuit 210 . The first pad 410 may be formed at an end portion of the wire constituting the first circuit 210 . The thickness of the first pad 410 may be substantially the same as the thickness of the first circuit 210 , and the width of the first pad 410 may be greater than the width of the first circuit 210 , and the cross-section of the first pad 410 may be nearly circular. of.
第一通路310可與第一接墊410接觸。具體而言,第一通路310的下表面可與第一接墊410的上表面接觸。 The first via 310 may be in contact with the first pad 410 . Specifically, the lower surface of the first via 310 may be in contact with the upper surface of the first pad 410 .
第二通路320的熔點可高於第一通路310的熔點。舉例而言,第二通路320可主要由銅製成,而第一通路310可主要由錫製成。此外,第二通路320可以是透過鍍覆形成的鍍覆通路。 The melting point of the second passage 320 may be higher than the melting point of the first passage 310 . For example, the second via 320 may be primarily made of copper, and the first via 310 may be primarily made of tin. In addition, the second via 320 may be a plated via formed by plating.
第二通路320可自第二絕緣層120的上表面至下表面穿透第二絕緣層120。第二通路320的橫截面積可(但不限於)自第二絕緣層120的上表面朝向下表面首先減小且然後增大。 The second via 320 may penetrate the second insulation layer 120 from the upper surface to the lower surface of the second insulation layer 120 . The cross-sectional area of the second via 320 may, but is not limited to, first decrease and then increase from the upper surface toward the lower surface of the second insulation layer 120 .
第二電路220可包括第二接墊420,第二接墊420可形成於第二絕緣層120的下表面上以嵌入於第一絕緣層110中,這與第二電路220類似。第二接墊420可形成於組成第二電路220的導線的端部部分處。第二接墊420的厚度可與第二電路220的厚度實質上相同,且第二接墊420的寬度可大於第二電路220的寬度,且第二接墊420的橫截面可近乎是圓形的。 The second circuit 220 may include second pads 420 , and the second pads 420 may be formed on the lower surface of the second insulating layer 120 to be embedded in the first insulating layer 110 , similar to the second circuit 220 . The second pad 420 may be formed at an end portion of the wire constituting the second circuit 220 . The thickness of the second pad 420 may be substantially the same as the thickness of the second circuit 220 , and the width of the second pad 420 may be greater than the width of the second circuit 220 , and the cross-section of the second pad 420 may be nearly circular. of.
第一通路310可與第二接墊420接觸。具體而言,第一通路310的上表面可與第二接墊420的下表面接觸。此外,第二通 路320可與第二接墊420接觸。具體而言,第二通路320的下表面可與第二接墊420的上表面接觸。 The first via 310 may be in contact with the second pad 420 . Specifically, the upper surface of the first via 310 may be in contact with the lower surface of the second pad 420 . In addition, the second pass The path 320 can be in contact with the second pad 420 . Specifically, the lower surface of the second via 320 may be in contact with the upper surface of the second pad 420 .
第三電路230可包括第三接墊430,第三接墊430可形成於第二絕緣層120的上表面上以向外突出,這與第三電路230類似。第三接墊430可形成於組成第三電路230的導線的端部部分處。第三接墊430的厚度可與第三電路230的厚度實質上相同,且第三接墊430的寬度可大於第三電路230的寬度,且第三接墊430的橫截面可近乎是圓形的。 The third circuit 230 may include third pads 430 , and the third pads 430 may be formed on the upper surface of the second insulation layer 120 to protrude outward, similar to the third circuit 230 . The third pad 430 may be formed at an end portion of the wire constituting the third circuit 230 . The thickness of the third pad 430 may be substantially the same as the thickness of the third circuit 230 , and the width of the third pad 430 may be greater than the width of the third circuit 230 , and the cross-section of the third pad 430 may be nearly circular. of.
第二通路320可與第三接墊430接觸。具體而言,第二通路320的上表面可與第三接墊430的下表面接觸。 The second via 320 may be in contact with the third pad 430 . Specifically, the upper surface of the second via 320 may be in contact with the lower surface of the third pad 430 .
在實例中,可透過以下路線傳送電訊號:第一電路210-第一接墊410-第一通路310-第二接墊420-第二電路220;或第一電路210-第一接墊410-第一通路310-第二接墊420-第二通路320-第三接墊430-第三電路230。 In an example, the electrical signal can be transmitted through the following route: first circuit 210 - first pad 410 - first via 310 - second pad 420 - second circuit 220; or first circuit 210 - first pad 410 - the first via 310 - the second pad 420 - the second via 320 - the third pad 430 - the third circuit 230.
與此同時,第一接墊410及第三接墊430可各自耦合至連接部件500。連接部件500可以是焊料凸塊或焊球。此類連接部件500被配置來電性連接印刷電路板與電子裝置(或外部板)以及實體地接合印刷電路板與電子裝置。換言之,印刷電路板與電子裝置(或外部板)藉由連接部件500彼此接合。 At the same time, the first pad 410 and the third pad 430 may each be coupled to the connection component 500 . The connection components 500 may be solder bumps or solder balls. Such connection components 500 are configured to electrically connect the printed circuit board and the electronic device (or external board) and to physically engage the printed circuit board and the electronic device. In other words, the printed circuit board and the electronic device (or external board) are joined to each other through the connection part 500 .
在實例中,放置於印刷電路板的上側上的連接部件500(亦即,耦合至第三接墊430的連接部件500)可耦合至電子裝置,且放置於印刷電路板的下側上的連接部件500(亦即,耦合至第一接 墊410的連接部件500)可耦合至外部板。在此種情形中,可透過以下路線傳送電訊號:外部板-連接部件500-第一接墊410-第一通路310-第二接墊420-第二通路320-第三接墊430-連接部件500-電子裝置。 In an example, the connecting component 500 placed on the upper side of the printed circuit board (ie, the connecting component 500 coupled to the third pad 430 ) may be coupled to the electronic device, and the connecting component 500 placed on the lower side of the printed circuit board Component 500 (i.e., coupled to the first The connection component 500) of the pad 410 may be coupled to the external board. In this case, the electrical signal can be transmitted through the following route: external board - connecting component 500 - first pad 410 - first via 310 - second pad 420 - second via 320 - third pad 430 - connection Part 500 - Electronic device.
第一絕緣層110的下表面上可層疊有阻焊層600,且第二絕緣層120的上表面上亦可層疊有阻焊層600。阻焊層600可被配置成保護第一電路210及第三電路230。與此同時,阻焊層600中可形成有開口(或通孔)以部分地暴露出第一接墊410及第三接墊430,且所述開口中可耦合有連接部件500。 The solder resist layer 600 may be laminated on the lower surface of the first insulating layer 110 , and the solder resist layer 600 may also be laminated on the upper surface of the second insulating layer 120 . The solder resist layer 600 may be configured to protect the first circuit 210 and the third circuit 230 . At the same time, an opening (or a through hole) may be formed in the solder resist layer 600 to partially expose the first pad 410 and the third pad 430, and the connecting component 500 may be coupled in the opening.
圖2示出根據本發明的實施例的印刷電路板。 Figure 2 shows a printed circuit board according to an embodiment of the invention.
參考圖2,根據本發明的實施例的印刷電路板包括:絕緣材料100、第一絕緣層110、第二絕緣層120、第三絕緣層130、第四絕緣層140、第一電路210、第二電路220、第三電路230、第四電路240、第五電路250及第六電路260。 Referring to Figure 2, a printed circuit board according to an embodiment of the present invention includes: an insulating material 100, a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a first circuit 210, a The second circuit 220 , the third circuit 230 , the fourth circuit 240 , the fifth circuit 250 and the sixth circuit 260 .
絕緣材料100是成為印刷電路板的芯且支撐印刷電路板的部分。絕緣材料100可由諸如環氧樹脂等絕緣材料製成,且絕緣材料100中可含有加強材100a。加強材100a可以是諸如玻璃纖維織物等纖維加強材。絕緣材料100可以是排除銅箔的覆銅層疊板(copper clad laminate,CCL)的部分。 The insulating material 100 is a portion that becomes the core of the printed circuit board and supports the printed circuit board. The insulating material 100 may be made of an insulating material such as epoxy resin, and the insulating material 100 may contain a reinforcing material 100a. The reinforcement 100a may be a fiber reinforcement such as fiberglass fabric. The insulating material 100 may be part of a copper clad laminate (CCL) excluding copper foil.
絕緣材料100的一個表面上可層疊有第一絕緣層110。第一絕緣層110可層疊於絕緣材料100的上表面上。在此種情形中,絕緣材料100可與第一絕緣層110的下表面接觸。此外,第二絕 緣層120可層疊於第一絕緣層110上方。 The first insulating layer 110 may be laminated on one surface of the insulating material 100 . The first insulation layer 110 may be laminated on the upper surface of the insulation material 100 . In this case, the insulating material 100 may be in contact with the lower surface of the first insulating layer 110 . In addition, the second unique The insulation layer 120 may be stacked on the first insulation layer 110 .
與此同時,絕緣材料100的另一表面上可層疊有第三絕緣層130。在此種情形中,絕緣材料100可與第三絕緣層130的上表面接觸。此外,第四絕緣層140可層疊於第三絕緣層130下方。 At the same time, a third insulating layer 130 may be laminated on the other surface of the insulating material 100 . In this case, the insulating material 100 may be in contact with the upper surface of the third insulating layer 130 . In addition, the fourth insulation layer 140 may be stacked below the third insulation layer 130 .
第一絕緣層110與第三絕緣層130彼此實質上相同,且第二絕緣層120與第四絕緣層140彼此實質上相同,且印刷電路板可關於絕緣材料100對稱。 The first insulating layer 110 and the third insulating layer 130 are substantially the same as each other, and the second insulating layer 120 and the fourth insulating layer 140 are substantially the same as each other, and the printed circuit board may be symmetrical about the insulating material 100 .
然而,本發明不一定僅限於上文所述的結構,且當(舉例而言)第一絕緣層110及第二絕緣層120層疊於絕緣材料100上方且僅第三絕緣層130層疊於絕緣材料100下方時,印刷電路板可關於絕緣材料100不對稱。此外,第一絕緣層110及第二絕緣層120層疊於絕緣材料100上方,且第三絕緣層130及第四絕緣層140層疊於絕緣材料下方,但第一絕緣層110與第三絕緣層130可彼此實質上不相同(就材料或厚度而言),且第二絕緣層120與第四絕緣層140可彼此實質上不相同(就材料或厚度而言)。 However, the present invention is not necessarily limited to the structure described above, and when (for example) the first insulating layer 110 and the second insulating layer 120 are stacked on the insulating material 100 and only the third insulating layer 130 is stacked on the insulating material Below 100, the printed circuit board may be asymmetrical with respect to the insulating material 100. In addition, the first insulating layer 110 and the second insulating layer 120 are stacked above the insulating material 100, and the third insulating layer 130 and the fourth insulating layer 140 are stacked below the insulating material, but the first insulating layer 110 and the third insulating layer 130 The second insulating layer 120 and the fourth insulating layer 140 may be substantially different from each other (in terms of material or thickness).
在後文中,將進一步闡述第一絕緣層110、第二絕緣層120、第三絕緣層130及第四絕緣層140。然而,由於上文已參考圖1闡述了第一絕緣層110及第二絕緣層120,因此本文中將不再對第一絕緣層110及第二絕緣層120予以贅述。 In the following, the first insulating layer 110, the second insulating layer 120, the third insulating layer 130 and the fourth insulating layer 140 will be further explained. However, since the first insulating layer 110 and the second insulating layer 120 have been described above with reference to FIG. 1 , the first insulating layer 110 and the second insulating layer 120 will not be described again herein.
第三絕緣層130是具有絕緣性質且主要由絕緣材料製成的層。第三絕緣層130可由幾乎不具有撓性的剛性材料製成。舉例而言,環氧樹脂、酚醛樹脂或BT樹脂可用作所述剛性材料。環氧 樹脂可以是(但不限於)例如:萘環氧樹脂、雙酚A型環氧樹脂、雙酚F型環氧樹脂、酚醛清漆環氧樹脂、甲酚酚醛清漆環氧樹脂、橡膠改質的環氧樹脂、環型脂族環氧樹脂、矽環氧樹脂、氮環氧樹脂或磷環氧樹脂。 The third insulating layer 130 is a layer that has insulating properties and is mainly made of insulating material. The third insulating layer 130 may be made of a rigid material with little flexibility. For example, epoxy resin, phenolic resin or BT resin can be used as the rigid material. Epoxy The resin may be (but is not limited to), for example: naphthalene epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin, cresol novolak epoxy resin, rubber modified epoxy resin Oxygen resin, cyclic aliphatic epoxy resin, silicone epoxy resin, nitrogen epoxy resin or phosphorus epoxy resin.
第三絕緣層130可以是含有纖維加強材(諸如,玻璃纖維織物)的預浸體(PPG)。第三絕緣層130可以是填充有無機填充物(諸如,二氧化矽)的積層膜。味之素積層膜(ABF)可用作此積層膜。 The third insulation layer 130 may be a prepreg (PPG) containing fiber reinforcement, such as fiberglass fabric. The third insulating layer 130 may be a laminated film filled with inorganic filler such as silicon dioxide. Ajinomoto laminated film (ABF) can be used as this laminated film.
第四絕緣層140是具有絕緣性質且主要由絕緣材料製成的層。第四絕緣層140可由具有高撓性的撓性材料製成。聚醯亞胺(PI)、液晶聚合物(LCP)等可用作所述撓性材料。 The fourth insulating layer 140 is a layer that has insulating properties and is mainly made of insulating material. The fourth insulation layer 140 may be made of a flexible material with high flexibility. Polyimide (PI), liquid crystal polymer (LCP), etc. can be used as the flexible material.
第一電路210、第二電路220、第三電路230、第四電路240、第五電路250及第六電路260用於傳送電訊號,且可由諸如銅(Cu)、鈀(Pd)、鋁(Al)、鎳(Ni)、鈦(Ti)、金(Au)、鉑(Pt)等金屬製成,或者考慮到該些金屬的導電率而由該些金屬中的一些金屬的合金製成。 The first circuit 210, the second circuit 220, the third circuit 230, the fourth circuit 240, the fifth circuit 250 and the sixth circuit 260 are used to transmit electrical signals, and can be made of copper (Cu), palladium (Pd), aluminum ( It is made of metals such as Al, nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), etc., or is made of alloys of some of these metals in consideration of the conductivity of these metals.
第一電路210、第二電路220、第三電路230、第四電路240、第五電路250及第六電路260可各自由導電配線製成,所述導電配線可被設置為多個。 The first circuit 210, the second circuit 220, the third circuit 230, the fourth circuit 240, the fifth circuit 250, and the sixth circuit 260 may each be made of conductive wiring, and the conductive wiring may be provided in plurality.
第一電路210形成於第一絕緣層110的下表面上且嵌入於第一絕緣層110中。由於第一電路210嵌入於第一絕緣層110中,因此第一電路210的除了第一電路210的下表面(亦即,第一電 路210的在圖2中放置於下側上的表面)之外的表面皆與第一絕緣層110接觸。 The first circuit 210 is formed on the lower surface of the first insulation layer 110 and embedded in the first insulation layer 110 . Since the first circuit 210 is embedded in the first insulating layer 110, all parts of the first circuit 210 except the lower surface of the first circuit 210 (ie, the first circuit 210 All surfaces of the path 210 (other than the surface placed on the lower side in FIG. 2 ) are in contact with the first insulating layer 110 .
此外,第一電路210形成於絕緣材料100的一個表面(亦即,上表面)上。 In addition, the first circuit 210 is formed on one surface (ie, the upper surface) of the insulating material 100 .
第二電路220形成於第二絕緣層120的下表面上且嵌入於第一絕緣層110中。第二電路220的上表面(亦即,第二電路220的在圖2中放置於上側上的表面)與第二絕緣層120的下表面接觸,且第二電路220的除了第二電路220的上表面之外的表面皆與第一絕緣層110接觸。 The second circuit 220 is formed on the lower surface of the second insulation layer 120 and embedded in the first insulation layer 110 . The upper surface of the second circuit 220 (that is, the surface of the second circuit 220 placed on the upper side in FIG. 2 ) is in contact with the lower surface of the second insulating layer 120 , and all other parts of the second circuit 220 except for the second circuit 220 All surfaces other than the upper surface are in contact with the first insulating layer 110 .
第三電路230形成於第二絕緣層120的上表面上。第三電路230與第二絕緣層120的上表面接觸且自第二絕緣層120的上表面突出至第二絕緣層120之外。 The third circuit 230 is formed on the upper surface of the second insulation layer 120 . The third circuit 230 is in contact with the upper surface of the second insulation layer 120 and protrudes from the upper surface of the second insulation layer 120 to outside the second insulation layer 120 .
第二電路220的節距小於第一電路210的節距。此外,第二電路220的寬度可小於第一電路210的寬度,且第二電路220的空間可小於第一電路210的空間。 The pitch of the second circuit 220 is smaller than the pitch of the first circuit 210 . In addition, the width of the second circuit 220 may be smaller than the width of the first circuit 210 , and the space of the second circuit 220 may be smaller than the space of the first circuit 210 .
此外,第三電路230的節距可小於第一電路210的節距。第三電路230的寬度可小於第一電路210的寬度,且第三電路230的空間可小於第一電路210的空間。 In addition, the pitch of the third circuit 230 may be smaller than the pitch of the first circuit 210 . The width of the third circuit 230 may be smaller than the width of the first circuit 210 , and the space of the third circuit 230 may be smaller than the space of the first circuit 210 .
舉例而言,第二電路220的節距及第三電路230的節距可各自為約20微米,且第一電路210的節距可大於此節距。 For example, the pitch of the second circuit 220 and the pitch of the third circuit 230 may each be about 20 microns, and the pitch of the first circuit 210 may be greater than this pitch.
換言之,第二電路220及第三電路230可形成為較第一電路210密集。此外,第二電路220及第三電路230可形成為較第 一電路210精密。 In other words, the second circuit 220 and the third circuit 230 may be formed denser than the first circuit 210 . In addition, the second circuit 220 and the third circuit 230 may be formed to be One circuit 210 precision.
第四電路240形成於絕緣材料100的另一表面(亦即,下表面)上且嵌入於第三絕緣層130中。由於第四電路240嵌入於第三絕緣層130中,因此第四電路240的除了第四電路240的上表面(亦即,第四電路240的在圖2中放置於上側上的表面)之外的表面皆與第三絕緣層130接觸。 The fourth circuit 240 is formed on the other surface (ie, the lower surface) of the insulating material 100 and embedded in the third insulating layer 130 . Since the fourth circuit 240 is embedded in the third insulating layer 130, the fourth circuit 240 except the upper surface of the fourth circuit 240 (ie, the surface of the fourth circuit 240 placed on the upper side in FIG. 2) The surfaces are all in contact with the third insulating layer 130 .
第五電路250形成於第三絕緣層130的下表面上且嵌入於第三絕緣層130中。第五電路250的除了第五電路250的下表面(亦即,第五電路250的在圖2中放置於下側上的表面)之外的表面皆與第三絕緣層130接觸。第五電路250位於第四絕緣層140的一個表面(亦即,上表面)上。 The fifth circuit 250 is formed on the lower surface of the third insulation layer 130 and embedded in the third insulation layer 130 . All surfaces of the fifth circuit 250 except the lower surface of the fifth circuit 250 (ie, the surface of the fifth circuit 250 placed on the lower side in FIG. 2 ) are in contact with the third insulating layer 130 . The fifth circuit 250 is located on one surface (ie, the upper surface) of the fourth insulating layer 140 .
第六電路260形成於第四絕緣層140的另一表面(亦即,下表面)上。第六電路260與第四絕緣層140的下表面接觸且自第四絕緣層140的另一表面(亦即,下表面)向外突出。 The sixth circuit 260 is formed on the other surface (ie, the lower surface) of the fourth insulating layer 140 . The sixth circuit 260 is in contact with the lower surface of the fourth insulating layer 140 and protrudes outward from the other surface (ie, the lower surface) of the fourth insulating layer 140 .
第五電路250的節距小於第四電路240的節距。此外,第五電路250的寬度可小於第四電路240的寬度,且第五電路250的空間可小於第四電路240的空間。 The pitch of the fifth circuit 250 is smaller than the pitch of the fourth circuit 240 . In addition, the width of the fifth circuit 250 may be smaller than the width of the fourth circuit 240 , and the space of the fifth circuit 250 may be smaller than the space of the fourth circuit 240 .
此外,第六電路260的節距可小於第四電路240的節距。第六電路260的寬度可小於第四電路240的寬度,且第六電路260的空間可小於第四電路240的空間。 In addition, the pitch of the sixth circuit 260 may be smaller than the pitch of the fourth circuit 240 . The width of the sixth circuit 260 may be smaller than the width of the fourth circuit 240 , and the space of the sixth circuit 260 may be smaller than the space of the fourth circuit 240 .
舉例而言,第五電路250的節距及第六電路260的節距可各自為約20微米,且第四電路240的節距可大於此節距。 For example, the pitch of the fifth circuit 250 and the pitch of the sixth circuit 260 may each be about 20 microns, and the pitch of the fourth circuit 240 may be greater than this pitch.
換言之,第五電路250及第六電路260可形成為較第四電路240密集。此外,第五電路250及第六電路260可形成為較第四電路240精密。 In other words, the fifth circuit 250 and the sixth circuit 260 may be formed denser than the fourth circuit 240 . In addition, the fifth circuit 250 and the sixth circuit 260 may be formed more precisely than the fourth circuit 240 .
第一電路210與第四電路240可彼此對稱,且第二電路220與第五電路250可彼此對稱,且第三電路230與第六電路260可彼此對稱。 The first circuit 210 and the fourth circuit 240 may be symmetrical to each other, the second circuit 220 and the fifth circuit 250 may be symmetrical to each other, and the third circuit 230 and the sixth circuit 260 may be symmetrical to each other.
參考圖2,根據本發明的實施例的印刷電路板可更包括貫穿通路100b、第一通路310、第二通路320、第三通路330及第四通路340。 Referring to FIG. 2 , the printed circuit board according to the embodiment of the present invention may further include a through via 100 b, a first via 310 , a second via 320 , a third via 330 and a fourth via 340 .
貫穿通路100b穿透絕緣材料100以電性連接第一電路210與第四電路240。貫穿通路100b可以是鍍覆通路且可由與第一電路210相同的金屬製成。貫穿通路100b可自絕緣材料100的一個表面至另一表面穿透絕緣材料100,且所述貫穿通路100b的橫截面積可自絕緣材料100的一個表面朝向另一表面首先減小且然後增大。貫穿通路100b的上表面可與第一電路210的第一接墊410接觸,且貫穿通路100b的下表面可與第四電路240的第四接墊440接觸。 The through via 100b penetrates the insulating material 100 to electrically connect the first circuit 210 and the fourth circuit 240. The through via 100b may be a plated via and may be made of the same metal as the first circuit 210. The through passage 100b may penetrate the insulating material 100 from one surface to another surface of the insulating material 100, and the cross-sectional area of the through passage 100b may first decrease and then increase from one surface toward the other surface of the insulating material 100. . The upper surface of the through via 100b may be in contact with the first pad 410 of the first circuit 210, and the lower surface of the through via 100b may be in contact with the fourth pad 440 of the fourth circuit 240.
第一通路310是被配置成藉由穿透第一絕緣層110來電性連接第一電路210與第二電路220的導電結構。此外,第二通路320是被配置成藉由穿透第二絕緣層120來電性連接第二電路220與第三電路230的導電結構。 The first via 310 is a conductive structure configured to electrically connect the first circuit 210 and the second circuit 220 by penetrating the first insulation layer 110 . In addition, the second via 320 is a conductive structure configured to electrically connect the second circuit 220 and the third circuit 230 by penetrating the second insulation layer 120 .
第一通路310的熔點可低於第一電路210的熔點。第一通 路310可由導電膏製成。在此,導電膏可以是含有金屬的膏,或是由導電聚合物製成但不含任何金屬的的膏。膏中所含有的金屬可以是銀(Ag)、錫(Sn)、鎳(Ni)及銅(Cu)中的一者或多者。在實例中,第一電路210可主要由銅製成,且第一通路310可主要由錫製成。導電膏的此實例被填充於通孔中且然後透過迴焊製程或加熱/冷卻製程而被金屬化以成為第一通路310。 The melting point of the first via 310 may be lower than the melting point of the first circuit 210 . first pass Path 310 may be made of conductive paste. Here, the conductive paste may be a paste containing metal, or a paste made of conductive polymer but not containing any metal. The metal contained in the paste may be one or more of silver (Ag), tin (Sn), nickel (Ni) and copper (Cu). In an example, first circuit 210 may be primarily made of copper, and first via 310 may be primarily made of tin. This example of conductive paste is filled in the via and then metallized through a reflow process or a heating/cooling process to become the first via 310 .
第一通路310的橫截面積可自第一絕緣層110的下表面至第一絕緣層110的上表面增大,在此種情形中第一通路310的縱截面可呈倒置梯形形狀。 The cross-sectional area of the first via 310 may increase from the lower surface of the first insulating layer 110 to the upper surface of the first insulating layer 110 , in which case the longitudinal cross-section of the first via 310 may be in the shape of an inverted trapezoid.
第一電路210可包括第一接墊410,第一接墊410可形成於第一絕緣層110的下表面上以嵌入於第一絕緣層110中,這與第一電路210類似。第一接墊410可形成於組成第一電路210的導線的端部部分處。第一接墊410的厚度可與第一電路210的厚度實質上相同,且第一接墊410的寬度可大於第一電路210的寬度,且第一接墊410的橫截面可近乎是圓形的。 The first circuit 210 may include a first pad 410 , and the first pad 410 may be formed on a lower surface of the first insulating layer 110 to be embedded in the first insulating layer 110 , similar to the first circuit 210 . The first pad 410 may be formed at an end portion of the wire constituting the first circuit 210 . The thickness of the first pad 410 may be substantially the same as the thickness of the first circuit 210 , and the width of the first pad 410 may be greater than the width of the first circuit 210 , and the cross-section of the first pad 410 may be nearly circular. of.
第一通路310可與第一接墊410接觸。具體而言,第一通路310的下表面可與第一接墊410的上表面接觸。此外,如上文所述,貫穿通路100b可與第一接墊410接觸。 The first via 310 may be in contact with the first pad 410 . Specifically, the lower surface of the first via 310 may be in contact with the upper surface of the first pad 410 . In addition, as mentioned above, the through via 100b may be in contact with the first pad 410.
第二通路320的熔點可高於第一通路310的熔點。舉例而言,第二通路320可主要由銅製成,而第一通路310可主要由錫製成。此外,第二通路320可以是透過鍍覆形成的鍍覆通路。 The melting point of the second passage 320 may be higher than the melting point of the first passage 310 . For example, the second via 320 may be primarily made of copper, and the first via 310 may be primarily made of tin. In addition, the second via 320 may be a plated via formed by plating.
第二通路320可自第二絕緣層120的上表面至下表面穿透 第二絕緣層120。第二通路320的橫截面積可(但不限於)自第二絕緣層120的上表面朝向下表面首先減小且然後增大。 The second via 320 can penetrate from the upper surface to the lower surface of the second insulation layer 120 second insulating layer 120. The cross-sectional area of the second via 320 may, but is not limited to, first decrease and then increase from the upper surface toward the lower surface of the second insulation layer 120 .
第二電路220可包括第二接墊420,第二接墊420可形成於第二絕緣層120的下表面上以嵌入於第一絕緣層110中,這與第二電路220類似。第二接墊420可形成於組成第二電路220的導線的端部部分處。第二接墊420的厚度可與第二電路220的厚度實質上相同,且第二接墊420的寬度可大於第二電路220的寬度,且第二接墊420的橫截面可近乎是圓形的。 The second circuit 220 may include second pads 420 , and the second pads 420 may be formed on the lower surface of the second insulating layer 120 to be embedded in the first insulating layer 110 , similar to the second circuit 220 . The second pad 420 may be formed at an end portion of the wire constituting the second circuit 220 . The thickness of the second pad 420 may be substantially the same as the thickness of the second circuit 220 , and the width of the second pad 420 may be greater than the width of the second circuit 220 , and the cross-section of the second pad 420 may be nearly circular. of.
第一通路310可與第二接墊420接觸。具體而言,第一通路310的上表面可與第二接墊420的下表面接觸。此外,第二通路320可與第二接墊420接觸。具體而言,第二通路320的下表面可與第二接墊420的上表面接觸。 The first via 310 may be in contact with the second pad 420 . Specifically, the upper surface of the first via 310 may be in contact with the lower surface of the second pad 420 . In addition, the second via 320 may be in contact with the second pad 420 . Specifically, the lower surface of the second via 320 may be in contact with the upper surface of the second pad 420 .
第三電路230可包括第三接墊430,第三接墊430可形成於第二絕緣層120的上表面上以向外突出,這與第三電路230類似。第三接墊430可形成於組成第三電路230的導線的端部部分處。第三接墊430的厚度可與第三電路230的厚度實質上相同,且第三接墊430的寬度可大於第三電路230的寬度,且第三接墊430的橫截面可近乎是圓形的。 The third circuit 230 may include third pads 430 , and the third pads 430 may be formed on the upper surface of the second insulation layer 120 to protrude outward, similar to the third circuit 230 . The third pad 430 may be formed at an end portion of the wire constituting the third circuit 230 . The thickness of the third pad 430 may be substantially the same as the thickness of the third circuit 230 , and the width of the third pad 430 may be greater than the width of the third circuit 230 , and the cross-section of the third pad 430 may be nearly circular. of.
第二通路320可與第三接墊430接觸。具體而言,第二通路320的上表面可與第三接墊430的下表面接觸。 The second via 320 may be in contact with the third pad 430 . Specifically, the upper surface of the second via 320 may be in contact with the lower surface of the third pad 430 .
第三通路330是被配置成藉由穿透第三絕緣層130來電性連接第四電路240與第五電路250的導電結構。此外,第四通路 340是被配置成藉由穿透第四絕緣層140來電性連接第五電路250與第六電路260的導電結構。 The third via 330 is a conductive structure configured to electrically connect the fourth circuit 240 and the fifth circuit 250 by penetrating the third insulating layer 130 . In addition, the fourth channel 340 is a conductive structure configured to electrically connect the fifth circuit 250 and the sixth circuit 260 by penetrating the fourth insulating layer 140 .
第三通路330的熔點可低於第四電路240的熔點。第三通路330可由導電膏製成。在此,導電膏可以是含有金屬的膏,或是由導電聚合物製成但不含任何金屬的的膏。膏中所含有的金屬可以是銀(Ag)、錫(Sn)、鎳(Ni)及銅(Cu)中的一者或多者。在實例中,第四電路240可主要由銅製成,且第三通路330可主要由錫製成。導電膏的此實例被填充於通孔中且然後透過迴焊製程或加熱/冷卻製程而被金屬化以成為第三通路330。 The melting point of the third via 330 may be lower than the melting point of the fourth circuit 240 . The third via 330 may be made of conductive paste. Here, the conductive paste may be a paste containing metal, or a paste made of conductive polymer but not containing any metal. The metal contained in the paste may be one or more of silver (Ag), tin (Sn), nickel (Ni) and copper (Cu). In an example, the fourth circuit 240 may be primarily made of copper, and the third via 330 may be primarily made of tin. This example of conductive paste is filled in the via and then metallized through a reflow process or a heating/cooling process to become the third via 330 .
第三通路330的橫截面積可自第四絕緣層140的上表面至下表面增大。在此種情形中,第三通路330的縱截面可呈梯形形狀。 The cross-sectional area of the third via 330 may increase from the upper surface to the lower surface of the fourth insulation layer 140 . In this case, the longitudinal section of the third passage 330 may have a trapezoidal shape.
第四電路240可包括第四接墊440,第四接墊440可形成於絕緣材料100的下表面上以嵌入於第三絕緣層130中,這與第四電路240類似。第四接墊440可形成於組成第四電路240的導線的端部部分處。第四接墊440的厚度可與第四電路240的厚度實質上相同,且第四接墊440的寬度可大於第四電路240的寬度,且第四接墊440的橫截面可近乎是圓形的。 The fourth circuit 240 may include fourth pads 440 , which may be formed on the lower surface of the insulating material 100 to be embedded in the third insulating layer 130 , similar to the fourth circuit 240 . The fourth pad 440 may be formed at an end portion of the wire constituting the fourth circuit 240 . The thickness of the fourth pad 440 may be substantially the same as the thickness of the fourth circuit 240 , and the width of the fourth pad 440 may be greater than the width of the fourth circuit 240 , and the cross-section of the fourth pad 440 may be nearly circular. of.
第三通路330可與第四接墊440接觸。具體而言,第三通路330的上表面可與第四接墊440的下表面接觸。此外,如上文所述,貫穿通路100b可與第四接墊440接觸。 The third via 330 may be in contact with the fourth pad 440 . Specifically, the upper surface of the third via 330 may be in contact with the lower surface of the fourth pad 440 . In addition, as mentioned above, the through via 100b may be in contact with the fourth pad 440.
第四通路340的熔點可高於第三通路330的熔點。舉例而 言,第四通路340可主要由銅製成,而第三通路330可主要由錫製成。此外,第四通路340可以是透過鍍覆形成的鍍覆通路。 The melting point of the fourth passage 340 may be higher than the melting point of the third passage 330 . For example That is, the fourth via 340 may be mainly made of copper, and the third via 330 may be mainly made of tin. In addition, the fourth via 340 may be a plated via formed by plating.
第四通路340可自第四絕緣層140的上表面至下表面穿透第四絕緣層140。第四通路340的橫截面積可(但不限於)自第四絕緣層140的上表面朝向下表面減小首先且然後增大。 The fourth via 340 may penetrate the fourth insulation layer 140 from the upper surface to the lower surface of the fourth insulation layer 140 . The cross-sectional area of the fourth via 340 may, but is not limited to, first decrease and then increase from the upper surface of the fourth insulating layer 140 toward the lower surface.
第五電路250可包括第五接墊450,第五接墊450可形成於第三絕緣層130的下表面上以嵌入於第三絕緣層130中,這與第五電路250類似。第五接墊450可形成於組成第五電路250的導線的端部部分處。第五接墊450的厚度可與第五電路250的厚度實質上相同,且第五接墊450的寬度可大於第五電路250的寬度,且第五接墊450的橫截面可近乎是圓形的。 The fifth circuit 250 may include fifth pads 450 , and the fifth pads 450 may be formed on the lower surface of the third insulating layer 130 to be embedded in the third insulating layer 130 , similar to the fifth circuit 250 . The fifth pad 450 may be formed at an end portion of the wire constituting the fifth circuit 250 . The thickness of the fifth pad 450 may be substantially the same as the thickness of the fifth circuit 250 , and the width of the fifth pad 450 may be greater than the width of the fifth circuit 250 , and the cross-section of the fifth pad 450 may be nearly circular. of.
第三通路330可與第五接墊450接觸。具體而言,第三通路330的下表面可與第五接墊450的上表面接觸。此外,第四通路340可與第五接墊450接觸。具體而言,第四通路340的上表面可與第五接墊450的下表面接觸。 The third via 330 may be in contact with the fifth pad 450 . Specifically, the lower surface of the third via 330 may be in contact with the upper surface of the fifth pad 450 . In addition, the fourth via 340 may be in contact with the fifth pad 450 . Specifically, the upper surface of the fourth via 340 may be in contact with the lower surface of the fifth pad 450 .
第六電路260可包括第六接墊460,第六接墊460可形成於第四絕緣層140的下表面上以向外突出,這與第六電路260類似。第六接墊460可形成於組成第六電路260的導線的端部部分處。第六接墊460的厚度可與第六電路260的厚度實質上相同,且第六接墊460的寬度可大於第六電路260的寬度,且第六接墊460的橫截面可近乎是圓形的。 The sixth circuit 260 may include sixth pads 460 , and the sixth pads 460 may be formed on the lower surface of the fourth insulation layer 140 to protrude outward, similar to the sixth circuit 260 . The sixth pad 460 may be formed at an end portion of the wire constituting the sixth circuit 260 . The thickness of the sixth pad 460 may be substantially the same as the thickness of the sixth circuit 260 , and the width of the sixth pad 460 may be greater than the width of the sixth circuit 260 , and the cross-section of the sixth pad 460 may be nearly circular. of.
第四通路340可與第六接墊460接觸。具體而言,第四通 路340的下表面可與第六接墊460的上表面接觸。 The fourth via 340 may be in contact with the sixth pad 460 . Specifically, the fourth pass The lower surface of the path 340 may be in contact with the upper surface of the sixth pad 460 .
在實例中,可透過以下路線傳送電訊號:第六電路260-第六接墊460-第四通路340-第五接墊450-第三通路330-第四接墊440-貫穿通路100b-第一接墊410-第一通路310-第二接墊420-第二通路320-第三接墊430-第三電路230。 In an example, the electrical signal may be transmitted through the following route: sixth circuit 260 - sixth pad 460 - fourth via 340 - fifth pad 450 - third via 330 - fourth pad 440 - through via 100b - th A pad 410 - first via 310 - second pad 420 - second via 320 - third pad 430 - third circuit 230.
與此同時,第三接墊430及第六接墊460可各自耦合至連接部件500。連接部件500可以是焊料凸塊或焊球。此類連接部件500被配置成電性連接印刷電路板與電子裝置(或外部板)且實體地接合印刷電路板與電子裝置。換言之,印刷電路板與電子裝置(或外部板)藉由連接部件500彼此接合。 At the same time, the third pad 430 and the sixth pad 460 may each be coupled to the connection component 500 . The connection components 500 may be solder bumps or solder balls. Such connection component 500 is configured to electrically connect the printed circuit board and the electronic device (or external board) and to physically engage the printed circuit board and the electronic device. In other words, the printed circuit board and the electronic device (or external board) are joined to each other through the connection part 500 .
在實例中,放置於印刷電路板的上側上的連接部件500(亦即,耦合至第三接墊430的連接部件500)可耦合至電子裝置,且放置於印刷電路板的下側上的連接部件500(亦即,耦合至第六接墊460的連接部件500)可耦合至外部板。在此種情形中,可透過以下路線傳送電訊號:外部板-連接部件500-第六接墊460-第四通路340-第五接墊450-第三通路330-第四接墊440-貫穿通路100b-第一接墊410-第一通路310-第二接墊420-第二通路320-第三接墊430-連接部件500-電子裝置。 In an example, the connecting component 500 placed on the upper side of the printed circuit board (ie, the connecting component 500 coupled to the third pad 430 ) may be coupled to the electronic device, and the connecting component 500 placed on the lower side of the printed circuit board Component 500 (ie, connection component 500 coupled to sixth pad 460) may be coupled to the external board. In this case, the electrical signal can be transmitted through the following route: external board - connecting component 500 - sixth pad 460 - fourth via 340 - fifth pad 450 - third via 330 - fourth pad 440 - through Via 100b - first pad 410 - first via 310 - second pad 420 - second via 320 - third pad 430 - connecting component 500 - electronic device.
第四絕緣層140的下表面上可層疊有阻焊層600,且第二絕緣層120的上表面上亦可層疊有阻焊層600。阻焊層600可被配置成保護第六電路260及第三電路230。與此同時,阻焊層600中可形成有開口(或通孔)以部分地暴露出第六接墊460及第三 接墊430,且所述開口中可耦合有連接部件500。 The solder resist layer 600 may be laminated on the lower surface of the fourth insulating layer 140 , and the solder resist layer 600 may also be laminated on the upper surface of the second insulating layer 120 . The solder resist layer 600 may be configured to protect the sixth circuit 260 and the third circuit 230 . At the same time, an opening (or through hole) may be formed in the solder resist layer 600 to partially expose the sixth pad 460 and the third pad 430, and a connection component 500 may be coupled in the opening.
圖3示出根據本發明的實施例的印刷電路板。 Figure 3 shows a printed circuit board according to an embodiment of the invention.
參考圖3,根據本發明的實施例的印刷電路板包括絕緣材料100、第一絕緣層110、第二絕緣層120、第三絕緣層130、第四絕緣層140、第一電路210、第二電路220、第三電路230、第四電路240、第五電路250及第六電路260,且可更包括貫穿通路100b及整合式通路350、整合式通路360。 Referring to Figure 3, a printed circuit board according to an embodiment of the present invention includes an insulating material 100, a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a first circuit 210, a second The circuit 220 , the third circuit 230 , the fourth circuit 240 , the fifth circuit 250 and the sixth circuit 260 may further include through vias 100 b and integrated vias 350 and 360 .
絕緣材料100、第一絕緣層110、第二絕緣層120、第三絕緣層130、第四絕緣層140、第一電路210、第二電路220、第三電路230、第四電路240、第五電路250、第六電路260及貫穿通路100b上文已加以闡述且因此本文中將不再贅述。 Insulating material 100, first insulating layer 110, second insulating layer 120, third insulating layer 130, fourth insulating layer 140, first circuit 210, second circuit 220, third circuit 230, fourth circuit 240, fifth The circuit 250, the sixth circuit 260 and the through-via 100b have been described above and therefore will not be described again herein.
整合式通路350與第一電路210電性連接且整體地穿透第一絕緣層110及第二絕緣層120。此外,整合式通路360與第四電路240電性連接且整體地穿透第三絕緣層130及第四絕緣層140。 The integrated via 350 is electrically connected to the first circuit 210 and integrally penetrates the first insulation layer 110 and the second insulation layer 120 . In addition, the integrated via 360 is electrically connected to the fourth circuit 240 and integrally penetrates the third insulating layer 130 and the fourth insulating layer 140 .
整合式通路350、整合式通路360的熔點可低於第一電路210(或第四電路240)的熔點。整合式通路350、整合式通路360可由導電膏製成。在此,導電膏可以是含有金屬的膏,或是由導電聚合物製成但不含任何金屬的膏。膏中所含有的金屬可以是銀(Ag)、錫(Sn)、鎳(Ni)及銅(Cu)中的一者或多者。在實例中,第一電路210可主要由銅製成,且整合式通路350、整合式通路360可主要由錫製成。導電膏的此實例被填充於通孔中且然後透過迴焊製程或加熱/冷卻製程而被金屬化以成為整合式通路 350、整合式通路360。 The melting point of the integrated via 350 and the integrated via 360 may be lower than the melting point of the first circuit 210 (or the fourth circuit 240). The integrated vias 350 and 360 can be made of conductive paste. Here, the conductive paste may be a paste containing metal, or a paste made of conductive polymer but not containing any metal. The metal contained in the paste may be one or more of silver (Ag), tin (Sn), nickel (Ni) and copper (Cu). In an example, the first circuit 210 may be mainly made of copper, and the integrated vias 350 and 360 may be mainly made of tin. This example of conductive paste is filled in the via and then metallized through a reflow process or a heating/cooling process to become an integrated via 350. Integrated pathway 360.
整合式通路350是被整合在一起的參考圖1及圖2所述的第一通路310與第二通路320,但不具有接墊。此外,整合式通路360是整合在一起的第三通路330及第四通路340,但不具有接墊。 The integrated via 350 is the first via 310 and the second via 320 described with reference to FIGS. 1 and 2 that are integrated together, but do not have pads. In addition, the integrated via 360 is the third via 330 and the fourth via 340 integrated together, but does not have a pad.
整合式通路350、整合式通路360可延伸至阻焊層600的開口。此外,整合式通路350、整合式通路360可在整合式通路350、整合式通路360與連接部件500之間不存在接墊的情況下與連接部件500接合。 The integrated vias 350 and 360 can extend to the opening of the solder resist layer 600 . In addition, the integrated vias 350 and 360 can be coupled to the connecting component 500 without the presence of pads between the integrated vias 350 and 360 and the connecting component 500 .
圖4及圖5示出製造根據本發明的實施例的印刷電路板的方法。 4 and 5 illustrate a method of manufacturing a printed circuit board according to an embodiment of the present invention.
圖4說明在第二絕緣層120上或在第二絕緣層120中形成第二電路220、第三電路230及第二通路320的步驟,且圖5說明使用圖4中已製備的各個組件(在後文中稱為「單元基板」)來製造印刷電路板的步驟。 FIG. 4 illustrates the steps of forming the second circuit 220 , the third circuit 230 and the second via 320 on or in the second insulating layer 120 , and FIG. 5 illustrates the use of various components prepared in FIG. 4 ( (hereinafter referred to as "unit substrate") to manufacture a printed circuit board.
參考圖4中的步驟(a),在其中金屬層M1層疊於第二絕緣層120的兩個表面上的基板中形成通孔VH1。 Referring to step (a) in FIG. 4 , a through hole VH1 is formed in the substrate in which the metal layer M1 is laminated on both surfaces of the second insulating layer 120 .
如上文所述,第二絕緣層120可由諸如聚醯亞胺等撓性材料製成。第二絕緣層120已在上文加以詳細地闡述且因此本文中將不再贅述。金屬層M1可由與第二電路220及第三電路230相同的金屬製成。金屬層M1可用作晶種層。 As mentioned above, the second insulation layer 120 may be made of a flexible material such as polyimide. The second insulating layer 120 has been described in detail above and therefore will not be described again herein. The metal layer M1 may be made of the same metal as the second circuit 220 and the third circuit 230 . Metal layer M1 can be used as a seed layer.
通孔VH1穿透金屬層M1及第二絕緣層120兩者。可使用例如雷射鑽機來形成通孔VH1,或者若有必要,可在使用例如蝕 刻來部分地移除金屬層M1之後對第二絕緣層120進行雷射鑽孔來打孔。CO2雷射可用作雷射鑽機。 The through hole VH1 penetrates both the metal layer M1 and the second insulation layer 120 . The through hole VH1 may be formed using, for example, a laser drill, or if necessary, the second insulating layer 120 may be laser drilled after partially removing the metal layer M1 using, for example, etching. CO2 lasers can be used as laser drills.
通孔VH1的橫截面積可自第二絕緣層120的一個表面至另一表面首先減小且然後增大。具體而言,在使用雷射鑽機形成通孔的情形中,孔的橫截面積可在雷射入射的表面處是最大的。因此,可通過將雷射輻射於第二絕緣層120的一個表面及另一表面兩者上來形成圖4的步驟(a)中所示的通孔VH1的形狀。然而,本發明不一定僅限於此形狀。與圖4的步驟(a)中所示的形狀不同,通孔的橫截面積自第二絕緣層120的一個表面至另一表面可以是恆定的、一直減小或一直增大。 The cross-sectional area of the through hole VH1 may first decrease and then increase from one surface of the second insulation layer 120 to the other surface. Specifically, in the case of using a laser drill to form a through hole, the cross-sectional area of the hole may be largest at the surface where the laser is incident. Therefore, the shape of the through hole VH1 shown in step (a) of FIG. 4 can be formed by irradiating laser on both one surface and the other surface of the second insulation layer 120 . However, the present invention is not necessarily limited to this shape. Different from the shape shown in step (a) of FIG. 4 , the cross-sectional area of the through hole may be constant, continuously decreasing, or always increasing from one surface of the second insulating layer 120 to another surface.
參考圖4中的步驟(b),可在通孔VH1內形成鍍覆層。鍍覆層可僅形成於通孔VH1內,或可不僅形成於通孔VH1內而且形成於金屬層M1的表面上。鍍覆層可由與金屬層M1相同的金屬製成。雖然鍍覆層與金屬層M1之間可形成界面,但圖4中未示出所述界面。 Referring to step (b) in FIG. 4, a plating layer may be formed within the through hole VH1. The plating layer may be formed only within the through hole VH1, or may be formed not only within the through hole VH1 but also on the surface of the metal layer M1. The plating layer may be made of the same metal as the metal layer M1. Although an interface may be formed between the plating layer and the metal layer M1, the interface is not shown in FIG. 4 .
參考圖4中的步驟(c),在第二絕緣層120的兩個表面上形成電路。在第二絕緣層120的一個表面上(亦即,下表面)形成第二電路220,且在第二絕緣層120的另一表面(亦即,上表面)上形成第三電路230。與此同時,第二接墊420與第二電路220一起形成,且第三接墊430與第三電路230一起形成。 Referring to step (c) in FIG. 4 , circuits are formed on both surfaces of the second insulating layer 120 . The second circuit 220 is formed on one surface (ie, the lower surface) of the second insulating layer 120, and the third circuit 230 is formed on the other surface (ie, the upper surface) of the second insulating layer 120. At the same time, the second pad 420 is formed together with the second circuit 220 , and the third pad 430 is formed together with the third circuit 230 .
可使用卷對卷設備(roll-to-roll equipment)透過減成技術或蓋孔技術(tenting technique)來形成第二電路220及第三電路 230。在鍍覆層僅形成於通孔VH1內的情形中,蝕刻金屬層M1以形成第二電路220及第三電路230。在鍍覆層不僅形成於通孔VH1內而且亦形成於金屬層M1的表面上的情形中,一起蝕刻金屬層M1及鍍覆層以形成第二電路220及第三電路230。 The second circuit 220 and the third circuit can be formed using roll-to-roll equipment through subtractive technology or tenting technology. 230. In the case where the plating layer is only formed in the through hole VH1, the metal layer M1 is etched to form the second circuit 220 and the third circuit 230. In the case where the plating layer is formed not only within the through hole VH1 but also on the surface of the metal layer M1 , the metal layer M1 and the plating layer are etched together to form the second circuit 220 and the third circuit 230 .
在通過減成技術或蓋孔技術形成電路的情形中,電路可各自具有精密的節距,且電路的製造成本可得以降低。與此同時,當使用減成技術或蓋孔技術形成電路時,電路的側面可為傾斜的,且電路中的每一者的橫截面積可向外減小。 In the case where the circuit is formed by the subtractive technology or the capped hole technology, the circuits can each have a precise pitch, and the manufacturing cost of the circuit can be reduced. Meanwhile, when a circuit is formed using a subtractive technology or a capped hole technology, the sides of the circuit may be inclined, and the cross-sectional area of each of the circuits may be reduced outward.
參考圖5中的步驟(a),形成第一電路210。可透過減成技術、蓋孔技術、SAP(半加成製程)技術或MSAP(經過修改的半加成製程)技術來形成第一電路210。 Referring to step (a) in Figure 5, a first circuit 210 is formed. The first circuit 210 may be formed through subtractive technology, capped hole technology, SAP (semi-additive process) technology or MSAP (modified semi-additive process) technology.
具體而言,提供拆卸型芯(detach core)(或載體)D,且在拆卸型芯D的一個表面上形成第一電路210。 Specifically, a detach core (or carrier) D is provided, and the first circuit 210 is formed on one surface of the detach core D.
拆卸型芯D是最終可拆除的基板,其絕緣材料層的兩個表面上可形成有金屬層。此外,金屬層可各自包括載體金屬層及晶種金屬層S,其中載體金屬層層疊於絕緣材料層上且晶種金屬層S層疊於載體金屬層上。載體金屬層的厚度可小於晶種金屬層S的厚度。在步驟(a)中,圖5僅示出晶種金屬層S,未示出載體金屬層。 The detachable core D is a final detachable substrate, on which metal layers can be formed on both surfaces of the insulating material layer. In addition, the metal layers may each include a carrier metal layer and a seed metal layer S, wherein the carrier metal layer is stacked on the insulating material layer and the seed metal layer S is stacked on the carrier metal layer. The thickness of the carrier metal layer may be smaller than the thickness of the seed metal layer S. In step (a), FIG. 5 only shows the seed metal layer S and not the carrier metal layer.
使用拆卸型芯的優勢之一是可同時製造兩個印刷電路板。亦即,如圖5的步驟(a)中所說明,除了拆卸型芯D的一個表面之外,亦可在拆卸型芯D的另一表面上形成與第一電路210 相同或類似的電路。在此種情形中,載體金屬層及晶種金屬層S層疊於拆卸型芯D的兩個表面上。 One of the advantages of using knockdown cores is that two PCBs can be manufactured simultaneously. That is, as illustrated in step (a) of FIG. 5 , in addition to one surface of the disassembly core D, the first circuit 210 may also be formed on another surface of the disassembly core D. The same or similar circuit. In this case, the carrier metal layer and the seed metal layer S are laminated on both surfaces of the disassembly core D.
根據減成技術或蓋孔技術,可藉由在晶種金屬層S上形成鍍覆層且然後與抗蝕劑圖案對應地選擇性地蝕刻所述鍍覆層來形成第一電路210。此外,根據SAP技術或MSAP技術,可藉由與抗鍍覆劑的圖案對應地對晶種金屬層S執行選擇性的鍍覆來形成第一電路210。 The first circuit 210 may be formed by forming a plating layer on the seed metal layer S and then selectively etching the plating layer corresponding to the resist pattern according to the subtractive technology or the capping technology. Furthermore, according to SAP technology or MSAP technology, the first circuit 210 may be formed by selectively plating the seed metal layer S corresponding to the pattern of the plating resist.
亦可使用與第一電路210相同的技術形成第一接墊410。 The first pad 410 can also be formed using the same technology as the first circuit 210 .
參考圖5中的步驟(b),在拆卸型芯D上層疊第一絕緣層110。第一絕緣層110覆蓋第一電路210。可在拆卸型芯D的一個表面上層疊第一絕緣層110,且亦可在拆卸型芯D的另一表面上層疊與第一絕緣層110相同或類似的絕緣層。 Referring to step (b) in FIG. 5 , the first insulating layer 110 is laminated on the disassembly core D. The first insulation layer 110 covers the first circuit 210 . The first insulating layer 110 may be stacked on one surface of the detachable core D, and an insulating layer that is the same as or similar to the first insulating layer 110 may also be stacked on the other surface of the detachable core D.
在第一絕緣層110中形成通孔VH2以部分地暴露出第一接墊410。可使用雷射鑽機來形成通孔VH2。CO2雷射可用作雷射鑽機。通孔VH2的橫截面積可向內減小。 A through hole VH2 is formed in the first insulation layer 110 to partially expose the first pad 410 . A laser drill can be used to form via VH2. CO2 lasers can be used as laser drills. The cross-sectional area of the through hole VH2 may be reduced inward.
參考圖5中的步驟(c),將導電膏P填充於通孔VH2中。可將導電膏擠壓至通孔VH2中。導電膏P的熔點可低於第一電路210的熔點。 Referring to step (c) in Figure 5, conductive paste P is filled into the through hole VH2. Conductive paste can be squeezed into via VH2. The melting point of the conductive paste P may be lower than the melting point of the first circuit 210 .
參考圖5中的步驟(d),將透過圖4中所說明的步驟製造的單元基板層疊於第一絕緣層110上。單元基板的第二接墊420可定位於導電膏P的上表面上。 Referring to step (d) in FIG. 5 , the unit substrate manufactured through the steps illustrated in FIG. 4 is laminated on the first insulating layer 110 . The second pad 420 of the unit substrate may be positioned on the upper surface of the conductive paste P.
可在高溫環境將單元基板加壓層疊於第一絕緣層110上, 且加壓可在高於導電膏P的熔點且低於第一電路210的熔點的溫度下進行。在此種情形中,僅導電膏P被熔融,而第一電路210及第二電路220未被熔融,且在冷卻期間使導電膏P硬化以成為第一通路310。在一系列步驟中,導電膏P用作第一電路210與第二電路220的黏合劑。 The unit substrate can be pressurized and laminated on the first insulating layer 110 in a high temperature environment. And the pressurization may be performed at a temperature higher than the melting point of the conductive paste P and lower than the melting point of the first circuit 210 . In this case, only the conductive paste P is melted, but the first circuit 210 and the second circuit 220 are not melted, and the conductive paste P is hardened to become the first via 310 during cooling. In a series of steps, the conductive paste P is used as an adhesive for the first circuit 210 and the second circuit 220 .
此外,透過圖5的(d)中所示的步驟,將第二電路220及第二接墊420嵌入於第一絕緣層110中。為此,當圖5的(d)中所示的步驟開始時,第一絕緣層110可處於B階段。 In addition, through the steps shown in (d) of FIG. 5 , the second circuit 220 and the second pad 420 are embedded in the first insulating layer 110 . To this end, when the step shown in (d) of FIG. 5 is started, the first insulating layer 110 may be in the B phase.
參考圖5中的步驟(e),移除拆卸型芯D。可通過首先移除除了晶種金屬層S之外的部分且然後蝕刻掉晶種金屬層S來移除拆卸型芯D。具體而言,在首先將載體金屬層與晶種金屬層S彼此分離且然後將晶種金屬層S保留於將成為印刷電路板的一部分處之後,透過單獨的步驟(亦即,蝕刻)移除晶種金屬層S。當蝕刻晶種金屬層S時,可部分地蝕刻第一電路210的下表面(亦即,位於拆卸型芯的一側上的表面)。 Referring to step (e) in Figure 5, remove the disassembly core D. The disassembly core D may be removed by first removing portions other than the seed metal layer S and then etching away the seed metal layer S. Specifically, after first separating the carrier metal layer and the seed metal layer S from each other and then leaving the seed metal layer S where it will become part of the printed circuit board, it is removed by a separate step, that is, etching. Seed metal layer S. When the seed metal layer S is etched, the lower surface of the first circuit 210 (ie, the surface on one side of the disassembly core) may be partially etched.
參考圖5中的步驟(f),將阻焊層600層疊於第一絕緣層110及第二絕緣層120上,並在阻焊層600中形成通孔VH3。可透過微影製程來形成通孔VH3,所述微影製程包括曝光及顯影。通孔VH3可暴露出第一接墊410的部分及第三接墊430的部分。 Referring to step (f) in FIG. 5 , the solder resist layer 600 is laminated on the first insulating layer 110 and the second insulating layer 120 , and a through hole VH3 is formed in the solder resist layer 600 . The through hole VH3 can be formed through a photolithography process, which includes exposure and development. The through hole VH3 may expose part of the first pad 410 and part of the third pad 430 .
參考圖5中的步驟(g),將連接部件500(諸如,焊料凸塊或焊球)耦合於通孔VH3中。連接部件500可與第一接墊410及第三接墊430接合。 Referring to step (g) in FIG. 5 , a connection component 500 (such as a solder bump or a solder ball) is coupled into the via VH3 . The connecting component 500 can be coupled with the first pad 410 and the third pad 430 .
圖6示出製造根據本發明的實施例的印刷電路板的方法。圖6中所示的方法是使用透過圖4中所示的步驟製造的單元基板來製造印刷電路板的另一方法。 Figure 6 illustrates a method of manufacturing a printed circuit board according to an embodiment of the invention. The method shown in FIG. 6 is another method of manufacturing a printed circuit board using the unit substrate manufactured through the steps shown in FIG. 4 .
參考圖6中的步驟(a),提供兩個表面上皆層疊有金屬層M2的絕緣材料100(例如,雙面覆銅層疊板),並在所述絕緣材料中形成通孔VH4。可使用例如雷射鑽機來形成通孔VH4。 Referring to step (a) in FIG. 6 , an insulating material 100 (for example, a double-sided copper-clad laminate) with a metal layer M2 laminated on both surfaces is provided, and a through hole VH4 is formed in the insulating material. The via hole VH4 may be formed using, for example, a laser drill.
參考圖6中的步驟(b),在通孔VH4內形成貫穿通路100b。此外,在絕緣材料100的表面上形成第一電路210及第四電路240。亦與第一電路210及第四電路240同時地形成第一接墊410及第四接墊440。 Referring to step (b) in FIG. 6 , a through passage 100b is formed in the through hole VH4. In addition, the first circuit 210 and the fourth circuit 240 are formed on the surface of the insulating material 100 . The first pad 410 and the fourth pad 440 are also formed simultaneously with the first circuit 210 and the fourth circuit 240 .
參考圖6中的步驟(c),將第一絕緣層110及第三絕緣層130層疊於絕緣材料100上,且分別在第一絕緣層110及第三絕緣層130中形成通孔VH5及通孔VH5’。 Referring to step (c) in FIG. 6 , the first insulating layer 110 and the third insulating layer 130 are laminated on the insulating material 100 , and through holes VH5 and through holes are formed in the first insulating layer 110 and the third insulating layer 130 respectively. Hole VH5'.
參考圖6中的步驟(d),將導電膏P填充於通孔VH5中,且將導電膏P’填充於通孔VH5’中。可將導電膏P、導電膏P’擠壓至通孔VH5、通孔VH5’中。導電膏P、導電膏P’的熔點可低於第一電路210(或第四電路240)的熔點。 Referring to step (d) in FIG. 6 , the conductive paste P is filled into the through hole VH5, and the conductive paste P' is filled into the through hole VH5'. The conductive paste P and conductive paste P’ can be squeezed into the through hole VH5 and the through hole VH5’. The melting point of the conductive paste P and the conductive paste P' may be lower than the melting point of the first circuit 210 (or the fourth circuit 240).
參考圖6中的步驟(e),將單元基板層疊於第一絕緣層110及第三絕緣層130中的每一者上。可透過圖4中所示的步驟製造單元基板。第一絕緣層110可與包括第二絕緣層120的單元基板層疊在一起,且第三絕緣層130可與包括第四絕緣層140的單元基板層疊在一起。當單元基板被層疊時,第二接墊420對應於導 電膏P,且第五接墊450對應於導電膏P’。 Referring to step (e) in FIG. 6 , the unit substrate is stacked on each of the first insulating layer 110 and the third insulating layer 130 . The unit substrate can be manufactured through the steps shown in FIG. 4 . The first insulating layer 110 may be stacked together with the unit substrate including the second insulating layer 120 , and the third insulating layer 130 may be stacked together with the unit substrate including the fourth insulating layer 140 . When the unit substrates are stacked, the second pad 420 corresponds to the conductive Electrical paste P, and the fifth pad 450 corresponds to the conductive paste P'.
可在高溫環境下將單元基板加壓層疊於第一絕緣層110及第三絕緣層130中的每一者上,且加壓可在高於導電膏P、導電膏P’的熔點且低於第一電路210(或第四電路240)的熔點的溫度下進行。在此種情形中,僅導電膏P、導電膏P’被熔融,而第一電路210(或第四電路240)未被熔融,且在冷卻期間使導電膏P硬化以成為第一通路310,且在冷卻期間使導電膏P’硬化以成為第三通路330。 The unit substrate can be stacked on each of the first insulating layer 110 and the third insulating layer 130 under high temperature environment, and the pressure can be higher than the melting point of the conductive paste P and the conductive paste P' and lower than The temperature of the first circuit 210 (or the fourth circuit 240) is the melting point. In this case, only the conductive paste P and the conductive paste P' are melted, but the first circuit 210 (or the fourth circuit 240) is not melted, and the conductive paste P is hardened during cooling to become the first via 310, And during the cooling period, the conductive paste P′ is hardened to form the third via 330 .
此外,第二電路220嵌入於第一絕緣層110中,且第五電路250嵌入於第三絕緣層130中。 In addition, the second circuit 220 is embedded in the first insulation layer 110 , and the fifth circuit 250 is embedded in the third insulation layer 130 .
參考圖6中的步驟(f),將阻焊層600層疊於第二絕緣層120及第四絕緣層140中的每一者上,且在阻焊層600中形成通孔VH6。可透過微影製程來形成通孔VH6,所述微影製程包括曝光及顯影。通孔VH6可暴露出第三接墊430的部分及第六接墊460的部分。 Referring to step (f) in FIG. 6 , the solder resist layer 600 is laminated on each of the second insulating layer 120 and the fourth insulating layer 140 , and a through hole VH6 is formed in the solder resist layer 600 . The through hole VH6 can be formed through a photolithography process, which includes exposure and development. The through hole VH6 may expose part of the third pad 430 and part of the sixth pad 460 .
參考圖6中的步驟(g),可將連接部件500(諸如,焊料凸塊或焊球)耦合於通孔VH6內。連接部件500可與第三接墊430及第六接墊460接合。可藉由將焊接材料插入於通孔VH6中且然後執行迴焊製程來形成連接部件500。 Referring to step (g) in FIG. 6 , a connection component 500 (such as a solder bump or a solder ball) may be coupled within the via VH6 . The connecting component 500 can be coupled with the third pad 430 and the sixth pad 460 . The connection component 500 may be formed by inserting solder material into the through hole VH6 and then performing a reflow process.
圖7及圖8示出製造根據本發明的實施例的印刷電路板的方法。 7 and 8 illustrate a method of manufacturing a printed circuit board according to an embodiment of the present invention.
圖7示出形成與圖4中所示的單元基板不同的單元基板的 步驟,且圖8示出使用透過圖7中所示的步驟所製備的單元基板來製造印刷電路板的步驟。 FIG. 7 illustrates formation of a unit substrate different from that shown in FIG. 4 . steps, and FIG. 8 shows a step of manufacturing a printed circuit board using the unit substrate prepared through the steps shown in FIG. 7 .
參考圖7,在第二絕緣層120上形成第二電路220及第三電路230,且在第二絕緣層120中形成通孔VH7。未使用通路來填充通孔VH7。 Referring to FIG. 7 , the second circuit 220 and the third circuit 230 are formed on the second insulation layer 120 , and the through hole VH7 is formed in the second insulation layer 120 . No via is used to fill via VH7.
圖8中的步驟(a)與圖6中的步驟(a)相同,且圖8中的步驟(b)與圖6中的步驟(b)相同。 Step (a) in FIG. 8 is the same as step (a) in FIG. 6 , and step (b) in FIG. 8 is the same as step (b) in FIG. 6 .
參考圖8中的步驟(c)及步驟(d),將第一絕緣層110及第三絕緣層130層疊於絕緣材料100的兩個表面上,且分別在第一絕緣層110及第三絕緣層130中形成通孔VH5及通孔VH5’。可首先將每一者皆包括金屬層M3的第一絕緣層110及第三絕緣層130層疊於絕緣材料100上,且然後可在形成通孔VH5、通孔VH5’之後,藉由例如蝕刻來移除金屬層M3。 Referring to steps (c) and (d) in FIG. 8 , the first insulating layer 110 and the third insulating layer 130 are laminated on both surfaces of the insulating material 100 , and the first insulating layer 110 and the third insulating layer are respectively The through hole VH5 and the through hole VH5' are formed in the layer 130. The first insulating layer 110 and the third insulating layer 130 , each including the metal layer M3 , may first be laminated on the insulating material 100 , and then may be formed by, for example, etching after the via holes VH5 and VH5 ′ are formed. Remove metal layer M3.
參考圖8中的步驟(e),將單元基板層疊於第一絕緣層110及第三絕緣層130中的每一者上。在此,形成於第二絕緣層120中的通孔VH7對應於形成於第一絕緣層110中的通孔VH5,且形成於第四絕緣層140中的通孔VH7’對應於形成於第三絕緣層130中的通孔VH5’。 Referring to step (e) in FIG. 8 , the unit substrate is stacked on each of the first insulating layer 110 and the third insulating layer 130 . Here, the through hole VH7 formed in the second insulating layer 120 corresponds to the through hole VH5 formed in the first insulating layer 110 , and the through hole VH7 ′ formed in the fourth insulating layer 140 corresponds to the through hole VH7 ′ formed in the third insulating layer 110 . Via hole VH5' in insulating layer 130.
參考圖8中的步驟(f),在第二絕緣層120及第四絕緣層140的每一者上形成阻焊層600,且然後在使阻焊層600形成有暴露出第三接墊430及第六接墊460的開口之後,將導電膏P整體地填充於通孔VH5、通孔VH7及阻焊層600的開口中。此外,將 導電膏整體地填充於通孔VH5’、通孔VH7’及阻焊層600的開口中。將整體填充的導電膏熔融,且然後冷卻以成為整合式通路350、整合式通路360。 Referring to step (f) in FIG. 8 , a solder resist layer 600 is formed on each of the second insulating layer 120 and the fourth insulating layer 140 , and then the solder resist layer 600 is formed to expose the third pad 430 and the opening of the sixth pad 460 , conductive paste P is integrally filled in the through hole VH5 , the through hole VH7 and the opening of the solder resist layer 600 . In addition, it will The conductive paste is integrally filled in the through hole VH5', the through hole VH7' and the openings of the solder resist layer 600. The integrally filled conductive paste is melted and then cooled to form integrated vias 350 and 360 .
參考圖8中的步驟(g),將連接部件500(諸如,焊料凸塊或焊球)耦合至整合式通路350、整合式通路360。 Referring to step (g) in FIG. 8 , connecting components 500 (such as solder bumps or balls) are coupled to integrated vias 350 , 360 .
雖然本發明包括具體的實例,但熟習此項技術者應明瞭可在不背離申請專利範圍及其等效形式的精神及範疇的情況下對該些實例做出各種形式及細節上的改變。本文中所述的實例僅應被視為具說明意義,並不應出於限制目的。對每一實例中的特徵或態樣的說明應被視為適用於其他實例中的類似特徵或態樣。若以不同的次序執行所述技術,及/或若以不同的方式組合及/或藉由其他組件或其等效形式替代或補充所述系統、架構、裝置或電路中的組件,則可達成合適的結果。因此,本發明的範疇並不是由所述詳細說明界定,而是由申請專利範圍及其等效形式界定,且在申請專利範圍及其等效形式的範疇內的所有的變化應被理解為包含於本發明中。 Although the present invention includes specific examples, it will be understood by those skilled in the art that various changes in form and details can be made in these examples without departing from the spirit and scope of the claimed scope and equivalents thereof. The examples set forth herein should be considered illustrative only and not for purposes of limitation. Descriptions of features or aspects in each instance should be deemed to apply to similar features or aspects in other instances. This may be achieved if the techniques are performed in a different order, and/or if components in the systems, architectures, devices or circuits are combined in a different manner and/or are replaced or supplemented by other components or their equivalents. suitable results. Therefore, the scope of the present invention is defined not by the detailed description, but by the patented scope and its equivalents, and all changes within the scope of the patented scope and its equivalents should be understood to include in the present invention.
110‧‧‧第一絕緣層 110‧‧‧First insulation layer
120‧‧‧第二絕緣層 120‧‧‧Second insulation layer
210‧‧‧第一電路 210‧‧‧First Circuit
220‧‧‧第二電路 220‧‧‧Second circuit
230‧‧‧第三電路 230‧‧‧Third circuit
310‧‧‧第一通路 310‧‧‧First Avenue
320‧‧‧第二通路 320‧‧‧Second Access
410‧‧‧第一接墊 410‧‧‧First pad
420‧‧‧第二接墊 420‧‧‧Second pad
430‧‧‧第三接墊 430‧‧‧Third pad
500‧‧‧連接部件 500‧‧‧Connecting parts
600‧‧‧阻焊層 600‧‧‧Solder mask
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JP2002009440A (en) * | 2000-06-16 | 2002-01-11 | Sumitomo Metal Mining Co Ltd | Composite wiring board |
JP2005072187A (en) * | 2003-08-22 | 2005-03-17 | Denso Corp | Multilayer circuit board, and its manufacturing method |
TW200904279A (en) * | 2007-07-04 | 2009-01-16 | Samsung Electro Mech | Carrier and method for manufacturing printed circuit board |
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US8127979B1 (en) | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
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