JP2007088009A - Method of embedding electronic part and printed wiring board with built-in electronic part - Google Patents
Method of embedding electronic part and printed wiring board with built-in electronic part Download PDFInfo
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- JP2007088009A JP2007088009A JP2005271567A JP2005271567A JP2007088009A JP 2007088009 A JP2007088009 A JP 2007088009A JP 2005271567 A JP2005271567 A JP 2005271567A JP 2005271567 A JP2005271567 A JP 2005271567A JP 2007088009 A JP2007088009 A JP 2007088009A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
本発明は、電子部品（能動部品、受動部品）を絶縁層中に埋め込む方法及び電子部品内蔵プリント配線板に関する。 The present invention relates to a method for embedding an electronic component (active component, passive component) in an insulating layer and a printed wiring board with a built-in electronic component.
近年、電子部品の小型化、薄型化に対する要求は益々大きくなり、電子機器の高機能化、高周波化も進んでいる。このような電子機器に対応すべく、小型高密度化、高周波対応を実現する様々な実装構造、あるいは基板での構造が提案されている。その中でも、基板内に電子部品を内蔵する構造は、電子機器そのもののトータル厚みを薄くすることが可能になり、部品と配線との距離を短くすることができることから注目されている構造である。 In recent years, demands for downsizing and thinning of electronic parts are increasing, and electronic devices have higher functions and higher frequencies. In order to cope with such an electronic device, various mounting structures that realize miniaturization and high density and high frequency response, or structures on a substrate have been proposed. Among these, the structure in which the electronic component is built in the substrate is a structure that has been attracting attention because the total thickness of the electronic device itself can be reduced and the distance between the component and the wiring can be shortened.
従来は、表裏両面に配線回路を備えた二層以上のプリント配線基板に、電子部品を実装し、当該電子部品を実装したプリント配線板の電子部品を搭載した一方の面に絶縁層を介して銅箔を重ねて積層してから貫通スルーホール、ＩＶＨ、ＢＶＨなどで表裏の接続を行なうことにより、電子部品を内蔵したプリント配線板を製造していた（例えば特許文献１参照）。
上記のように、従来の部品内蔵プリント配線では、必ず、少なくとも一方の面に回路を形成した絶縁基板をコア基板として使用している。すなわち、前記コア基板の回路形成面に電子部品を実装して絶縁層で埋め込み、更に上下にビルドアップ層を積層することにより、多層プリント配線板を製造しているが、当該コアの絶縁基材の存在の故に、その厚さ相当分はどうしてもプリント配線板のトータル厚みを薄くすることはできない、と云う問題があった。 As described above, in the conventional component built-in printed wiring, an insulating substrate having a circuit formed on at least one surface is always used as a core substrate. That is, a multilayer printed wiring board is manufactured by mounting an electronic component on the circuit forming surface of the core substrate and embedding it with an insulating layer, and further laminating buildup layers on the upper and lower sides. For this reason, there is a problem that the total thickness of the printed wiring board cannot be reduced by an amount corresponding to the thickness.
本発明者は上記問題点に鑑み、プリント配線板のトータル厚みを薄くすることができる電子部品の埋め込み方法及びトータル厚みの薄い部品内蔵プリント配線板を提供することも課題とする。 In view of the above problems, the present inventor also has an object to provide an electronic component embedding method capable of reducing the total thickness of a printed wiring board and a component built-in printed wiring board having a small total thickness.
本発明は、少なくとも２層構造から成る支持体の第一層部の不要部分を除去する工程と、次いで、当該第一層部に残された凸状部分の少なくとも一つに電子部品を搭載する工程と、次いで、当該電子部品搭載面に絶縁層を積層する工程と、次いで、支持体の第二層部を除去する工程とを有することを特徴とする絶縁層中への電子部品の埋め込み方法により上記課題を解決したものである。 In the present invention, an unnecessary part of the first layer portion of the support having at least a two-layer structure is removed, and then an electronic component is mounted on at least one of the convex portions remaining in the first layer portion. And a step of laminating an insulating layer on the electronic component mounting surface, and then a step of removing the second layer portion of the support, and a method of embedding the electronic component in the insulating layer This solves the above problem.
上記のとおり本発明においては、支持体の第二層部を除去しているので、プリント配線板のトータルの厚みが薄くなる。また、本発明においては、第１層部に残された凸状部、すなわち接続パッドに搭載された電子部品ごと絶縁層に埋め込まれるため、絶縁層の表面が平坦化され、次工程のビルドアップ層を積層するためにも有利である。 As described above, in the present invention, since the second layer portion of the support is removed, the total thickness of the printed wiring board is reduced. Further, in the present invention, since the convex portions remaining in the first layer portion, that is, the electronic components mounted on the connection pads are embedded in the insulating layer, the surface of the insulating layer is flattened, and the next process build-up is performed. It is also advantageous for laminating the layers.
本発明において、前記絶縁層としては、シート状の絶縁層を用いるのが、トータルの厚みのバラツキが少なくなる点で好ましい。
また、前記絶縁層としては、予め電子部品の大きさに合わせた開口部を形成したものが、実装された電子部品に絶縁層の樹脂が溶融し、ボイドをかむことなく樹脂を充填することができる点で好ましい。
In the present invention, it is preferable to use a sheet-like insulating layer as the insulating layer from the viewpoint of reducing variation in total thickness.
In addition, as the insulating layer, an opening that has been previously adjusted to the size of the electronic component may be formed, and the resin of the insulating layer melts into the mounted electronic component, and the resin is filled without biting the void. It is preferable in that it can be performed.
また、前記絶縁層としては、補強材が含まれているものが、電子部品が埋め込まれた絶縁層にコシができ、次工程でのビルドアップ層が容易に形成できる点で好ましい。 The insulating layer containing a reinforcing material is preferable in that the insulating layer in which the electronic component is embedded can be stiff and a build-up layer in the next process can be easily formed.
また、前記電子部品の接続は、異方性導電膜、異方性導電ペースト又は導電性接着剤を使用して行なうのが、はんだ実装した場合のフラックス洗浄がいらなくなる点で好ましい。特に、電子部品の隙間に入ったフラックスを除去することは通常の洗浄では困難であるため、異方性導電膜などを使用することは、大変有効である。 Further, the connection of the electronic components is preferably performed using an anisotropic conductive film, an anisotropic conductive paste, or a conductive adhesive in terms of eliminating the need for flux cleaning when soldered. In particular, since it is difficult to remove the flux that has entered the gap between the electronic components by ordinary cleaning, it is very effective to use an anisotropic conductive film.
また、前記少なくとも二層構造の支持体としては、選択エッチング可能な２種の金属からなるものが、各層選択的にエッチングできる結果、凸状部を形成して電子部品を実装し、更に絶縁層に埋め込み後、支持体をエッチングにて容易に除去することが可能になる点で好ましいと共に、部品搭載時及び搭載後の熱による収縮が小さいため、部品搭載後の位置精度が高い点でも有利である。 The at least two-layered support is made of two kinds of metals that can be selectively etched, and each layer can be selectively etched. As a result, a convex portion is formed and an electronic component is mounted. In addition, it is preferable in that the support can be easily removed by etching after being embedded in the substrate, and since the shrinkage due to heat after mounting and after mounting the component is small, it is advantageous in that the positional accuracy after mounting the component is high. is there.
また、本発明は、上記の方法によって埋め込まれた電子部品を備えた電子部品内蔵プリント配線板によって前記課題を解決したものである。すなわち、本発明によれば、トータルの厚みが薄い電子部品内蔵プリント配線板を提供することができる。
本発明において、前記電子部品内蔵プリント配線板としては、ビルドアップ多層プリント配線板とするのが、上下に導体層と絶縁層を交互に積層することで高密度化された電子部品内蔵基板が形成できる点で好ましい。
Moreover, this invention solves the said subject by the electronic component built-in printed wiring board provided with the electronic component embedded by said method. That is, according to the present invention, it is possible to provide an electronic component built-in printed wiring board having a thin total thickness.
In the present invention, as the electronic component built-in printed wiring board, a build-up multilayer printed wiring board is formed, and a high-density electronic component built-in substrate is formed by alternately laminating conductor layers and insulating layers on the upper and lower sides. It is preferable in that it can be performed.
本発明によれば、従来コアの絶縁基材相当分の厚みを薄くし得るので、トータルの基板の厚みが薄くなった電子部品内蔵プリント配線板を提供することができる。 According to the present invention, since the thickness corresponding to the insulating base of the conventional core can be reduced, it is possible to provide an electronic component built-in printed wiring board in which the total thickness of the substrate is reduced.
本発明の第１の実施の形態を図１〜２を用いて説明する。 A first embodiment of the present invention will be described with reference to FIGS.
まず、図１（ａ）に示されるように、銅１ａとニッケル１ｂから成る二層構造の支持体１を用意する。
ここで、二層構造の支持体の例としては、金属を用いる場合にはこの実施の形態の如く、第一層部／第二層部を、銅１ａ／ニッケル１ｂで構成したものが挙げられるが、第一層部と第二層部の金属は、選択エッチングできる金属であれば特に限定されない。また、第一層部／第二層部を、銅／感光性樹脂あるいは剥離性樹脂で構成しても構わない。
First, as shown in FIG. 1A, a two-layer structure support 1 made of copper 1a and nickel 1b is prepared.
Here, as an example of the support having a two-layer structure, when a metal is used, as in this embodiment, the first layer portion / second layer portion may be composed of copper 1a / nickel 1b. However, the metal of the first layer part and the second layer part is not particularly limited as long as it can be selectively etched. Moreover, you may comprise a 1st layer part / 2nd layer part with copper / photosensitive resin or peelable resin.
本発明においては、前記した通り少なくとも二層構造の支持体であることが必須である。換言すれば、第一層部と第二層部の材質によっては三層構造以上の支持体を使用しても構わない。
例えば、部品実装パッドを含む第一層部と第二層部の材質の厚みが薄い場合、部品実装時の負荷に耐えうるために三層構造の支持体を使用することができる。
ここで、三層構造の支持体としては、例えば後述する第２の実施の形態のように、第一層部／第二層部／第三層部を、銅／ニッケル／銅で構成したものが挙げられるが、当該第一層部と第二層部の金属は、選択エッチングできる金属であれば特に限定されない。また、第一層部／第二層部／第三層部を、銅／感光性樹脂あるいは剥離する樹脂／銅で構成しても構わない。
In the present invention, it is essential that the support has at least a two-layer structure as described above. In other words, depending on the material of the first layer portion and the second layer portion, a support having a three-layer structure or more may be used.
For example, when the thickness of the material of the first layer part and the second layer part including the component mounting pad is thin, a support having a three-layer structure can be used to withstand the load during component mounting.
Here, as a support body having a three-layer structure, for example, a first layer portion / second layer portion / third layer portion made of copper / nickel / copper as in a second embodiment described later. However, the metal of the said 1st layer part and the 2nd layer part will not be specifically limited if it is a metal which can be selectively etched. Further, the first layer portion / second layer portion / third layer portion may be composed of copper / photosensitive resin or a resin / copper to be peeled off.
次いで、図１（ｂ）に示されるように、前記二層構造の支持体１の表裏にエッチングレジスト２を形成した後、一方の面のみ露光・現像しエッチングマスク２ａを形成する。エッチングレジストとしては、例えば感光性ドライフィルムレジスト、感光性液状樹脂などが用いられる。 Next, as shown in FIG. 1B, after forming an etching resist 2 on the front and back of the support 1 having the two-layer structure, only one surface is exposed and developed to form an etching mask 2a. As the etching resist, for example, a photosensitive dry film resist or a photosensitive liquid resin is used.
次いで、図１（ｃ）に示されるように、露出している銅１ａの部分のみエッチングにて除去する。この時のエッチングは例えばアルカリエッチング液を用いて行なわれる。次いで、図１（ｄ）に示されるように、エッチングレジスト２とエッチングマスク２ａを剥離し、銅１ａの部分が凸状となった二層構造の支持体１とする。 Next, as shown in FIG. 1C, only the exposed portion of the copper 1a is removed by etching. The etching at this time is performed using, for example, an alkaline etching solution. Next, as shown in FIG. 1D, the etching resist 2 and the etching mask 2a are peeled to form a support 1 having a two-layer structure in which the copper 1a portion is convex.
次いで、図１（ｅ）に示されるように、この凸状の銅１ａの部分に電子部品、例えばＬＳＩ３ａやチップ抵抗３ｂを実装する。この時の電子部品の実装は、はんだ接続（図示せず）でも構わないが、実装後のフラックスの洗浄等を考慮すると異方性導電膜や異方性導電ペーストあるいは導電性接着剤、接着剤などを使用するのが洗浄工程を省略できるので好ましい。 Next, as shown in FIG. 1E, an electronic component such as an LSI 3a or a chip resistor 3b is mounted on the convex copper 1a. At this time, the electronic component may be mounted by solder connection (not shown). However, in consideration of flux cleaning after mounting, an anisotropic conductive film, anisotropic conductive paste, conductive adhesive, adhesive, etc. It is preferable to use such as because the washing step can be omitted.
次いで、図１（ｆ）に示されるように、電子部品搭載面に、絶縁層４を積層する。ここで、絶縁層４に予め電子部品の大きさに合わせて開口部を設けておくと、実装された電子部品に絶縁層４の樹脂が積層の際に溶融し、うまく樹脂が充填されるため、ボイドをかむ恐れがなく好ましい。
また、絶縁層は、厚みが均一なシート状のものが好ましく、補強材が含まれているとより好ましい。補強材としては、例えばガラスクロス、ガラス繊維、アラミド繊維や無機フィラーが挙げられ、これらに樹脂を含浸せしめた絶縁シートが好適に使用される。
当該樹脂としては、有機成分もしくは高分子成分のものが好適に使用でき、就中熱硬化性樹脂と熱可塑性樹脂が特に好適に用いられる。
熱硬化性樹脂としては、主にフェノール樹脂とエポキシ樹脂が使用されるが、特にポリイミド、ビスマレイミドトリアジン樹脂、メラミン樹脂、シアネート樹脂、ベンゾシクロブテン樹脂、不飽和ポリエステル、ポリベンゾオキサゾール、ポリフェニレンエーテル、ポリフェニレンオキサイド、ジアリルフタレート樹脂などが好適に使用される。
また、熱可塑性樹脂としては、ポリイミド、ポリエステル、液晶ポリマー、フッ素樹脂、ポリエーテルエーテルケトン、ポリノルボルネン、ポリエチレンテレフタレート、シクロオレフィン樹脂、ポリフェニレンサルファイド、ポリエーテルスルフォン、アクリル樹脂などが好適に使用される。
Next, as shown in FIG. 1F, the insulating layer 4 is laminated on the electronic component mounting surface. Here, if an opening is provided in advance in the insulating layer 4 in accordance with the size of the electronic component, the resin of the insulating layer 4 melts in the laminated electronic component and is well filled with the resin. It is preferable because there is no risk of biting the void.
The insulating layer is preferably a sheet having a uniform thickness, and more preferably includes a reinforcing material. Examples of the reinforcing material include glass cloth, glass fiber, aramid fiber, and inorganic filler, and an insulating sheet impregnated with a resin is preferably used.
As the resin, those having an organic component or a polymer component can be preferably used, and thermosetting resins and thermoplastic resins are particularly preferably used.
As thermosetting resin, phenol resin and epoxy resin are mainly used, but especially polyimide, bismaleimide triazine resin, melamine resin, cyanate resin, benzocyclobutene resin, unsaturated polyester, polybenzoxazole, polyphenylene ether, Polyphenylene oxide, diallyl phthalate resin and the like are preferably used.
As the thermoplastic resin, polyimide, polyester, liquid crystal polymer, fluororesin, polyether ether ketone, polynorbornene, polyethylene terephthalate, cycloolefin resin, polyphenylene sulfide, polyether sulfone, acrylic resin, and the like are preferably used.
次いで、図１（ｇ）に示されるように、絶縁層４側にエッチングレジスト２を形成した後、ニッケル１ｂを硝酸系のエッチング液などで除去する。次いで、エッチングレジスト２を剥離し、図１（ｈ）に示されるように、支持体の金属、すなわちニッケル１ｂがなく、かつ電子部品が絶縁層４中に埋め込まれた構造体を得る。
斯様に支持体の金属（ニッケル）を除去することで、当該金属（ニッケル）の厚さ相当分、基板の厚みが薄くなる結果、プリント配線板のトータル厚みを薄くすることが可能となる。
Next, as shown in FIG. 1G, after forming the etching resist 2 on the insulating layer 4 side, the nickel 1b is removed with a nitric acid-based etching solution or the like. Next, the etching resist 2 is peeled off, and as shown in FIG. 1 (h), a structure in which the metal of the support, that is, nickel 1b is absent and the electronic component is embedded in the insulating layer 4 is obtained.
Thus, by removing the metal (nickel) of the support, the thickness of the substrate is reduced by an amount corresponding to the thickness of the metal (nickel), and as a result, the total thickness of the printed wiring board can be reduced.
次いで、図２（ｉ）に示されるように、前記電子部品を埋め込んだ絶縁層５の上下にビルドアップ材６と銅箔７を重ねて積層する。 Next, as shown in FIG. 2I, the build-up material 6 and the copper foil 7 are stacked on top and bottom of the insulating layer 5 in which the electronic component is embedded.
次いで、図２（ｊ）に示されるように、層間接続部にレーザ加工にて、非貫通穴８を設けた後、貫通穴９をドリル加工あるいはレーザ加工で形成し、更に全面にパネルメッキを施す。 Next, as shown in FIG. 2 (j), after the non-through hole 8 is provided in the interlayer connection portion by laser processing, the through hole 9 is formed by drilling or laser processing, and further panel plating is performed on the entire surface. Apply.
次いで、図２（ｋ）に示されるように、ドライフィルムレジストを上下に形成し、露光・現像後、エッチングにて回路１０と層間接続ビア１１、貫通めっきスルーホール１２を形成する。 Next, as shown in FIG. 2 (k), a dry film resist is formed up and down, and after exposure and development, a circuit 10, an interlayer connection via 11, and a through-plating through hole 12 are formed by etching.
次いで、上記図２（ｉ）〜（ｋ）工程を繰り返し、図２（ｌ）に示される２段目のビルドアップ層を備えたビルドアップ基板を得る。次いで、図２（ｍ）に示されるように、最外層にソルダーレジスト１３を形成する。
斯様に、電子部品を埋め込んだ絶縁層４をコアとしてその上下に、ビルドアップ材を積層してビルドアップ多層プリント配線板を製造すれば、電子部品を埋め込んだ絶縁層を中心に上下対象構造となり、プリント配線板が反ることがなくなる。
Next, the steps shown in FIGS. 2 (i) to 2 (k) are repeated to obtain a build-up substrate having the second-stage build-up layer shown in FIG. 2 (l). Next, as shown in FIG. 2 (m), a solder resist 13 is formed on the outermost layer.
In this way, if a build-up multilayer printed wiring board is manufactured by stacking build-up materials on the upper and lower sides of the insulating layer 4 in which the electronic component is embedded, the upper and lower target structures centering on the insulating layer in which the electronic component is embedded. Thus, the printed wiring board is not warped.
以上第１の実施の形態では、支持体１に実装した電子部品を、絶縁層にその片側から埋め込む例を説明した。 In the first embodiment, the example in which the electronic component mounted on the support 1 is embedded in the insulating layer from one side has been described.
次に、本発明の第２の実施の形態を図３を用いて説明する。 Next, a second embodiment of the present invention will be described with reference to FIG.
まず、図３（ａ）、（ｂ）に示されるように、図１（ａ）〜（ｄ）に示す工程と同様にして得られた第１層部が凸状の三層構造、すなわち銅２１ａ，ニッケル２１ｂ，銅２１ｃから成る三層構造の支持体２１を２枚用意し、それぞれに、ＩＣやＬＳＩ２３ａ、チップ抵抗２３ｂやチップコンデンサなどを実装する。 First, as shown in FIGS. 3A and 3B, the first layer portion obtained in the same manner as the steps shown in FIGS. 1A to 1D has a convex three-layer structure, that is, copper. Two supports 21 having a three-layer structure 21a, nickel 21b, and copper 21c are prepared, and an IC, LSI 23a, chip resistor 23b, chip capacitor, and the like are mounted on each.
次いで、図３（ｃ）に示されるように、絶縁層２４の上下両面から、ＩＣやＬＳＩ２３ａ、チップ抵抗２３ｂやチップコンデンサなどの電子部品を実装した前記三層構造の支持体２１を積層する。ここで、絶縁層２４に予め部品の大きさに合わせて開口部を設けておくと、実装された電子部品に絶縁層２４の樹脂が積層の際に溶融し、うまく樹脂が充填されるため、ボイドをかむ恐れがなく好ましい。尚、絶縁層としては、前記したものが好適に使用される。 Next, as shown in FIG. 3C, the support 21 having the three-layer structure on which electronic components such as an IC, an LSI 23a, a chip resistor 23b, and a chip capacitor are mounted is laminated from the upper and lower surfaces of the insulating layer 24. Here, if an opening is provided in the insulating layer 24 according to the size of the component in advance, the resin of the insulating layer 24 melts at the time of lamination in the mounted electronic component, and the resin is well filled. There is no risk of biting voids. As the insulating layer, those described above are preferably used.
次いで、図３（ｄ）に示されるように、支持体２１の銅２１ｃをアルカリ液でエッチング除去した後、硝酸系のエッチング液などでニッケル２１ｂを除去し、図３（ｅ）に示されるように、支持体の金属、すなわちニッケル２１ｂがなく、かつ電子部品が絶縁層２４中に埋め込まれた構造体を得る。
斯様に支持体の金属（ニッケル）を除去することで、当該金属（ニッケル）の厚さ相当分が薄くなる結果、プリント配線板のトータル厚みを薄くすることが可能となる。しかも、三層構造の支持体２１を使用することで電子部品実装時の合成にも耐え得ることができる。
Next, as shown in FIG. 3 (d), the copper 21c of the support 21 is removed by etching with an alkaline solution, and then the nickel 21b is removed with a nitric acid-based etching solution or the like, as shown in FIG. 3 (e). In addition, a structure in which the metal of the support, that is, nickel 21b is absent and the electronic component is embedded in the insulating layer 24 is obtained.
By removing the metal (nickel) from the support in this manner, the thickness corresponding to the thickness of the metal (nickel) is reduced. As a result, the total thickness of the printed wiring board can be reduced. In addition, by using the support 21 having a three-layer structure, it is possible to withstand synthesis when mounting electronic components.
次いで、前記図２（ｉ）〜（ｋ）の工程を表裏上下に施し、図３（ｆ）に示されるように、一層のビルドアップ層を備えると共に、回路３０、層間接続ビア３１、貫通めっきスルーホール３２を備えたビルドアップ多層基板を得る。
次いで、前記図２（ｉ）〜（ｋ）の工程を繰り返し、図３（ｇ）に示されるように、二層のビルドアップ層を備えたビルドアップ多層基板を得、最後に、図３（ｈ）に示されるように、最外層にソルダーレジスト３３を形成する。
Next, the steps of FIGS. 2 (i) to 2 (k) are performed on the top and bottom, and as shown in FIG. 3 (f), a single build-up layer is provided, and the circuit 30, interlayer connection via 31, and through plating are provided. A build-up multilayer board provided with through holes 32 is obtained.
Next, the steps of FIGS. 2 (i) to (k) are repeated to obtain a build-up multilayer substrate having two build-up layers as shown in FIG. 3 (g). Finally, FIG. As shown in h), a solder resist 33 is formed on the outermost layer.
以上第２の実施の形態では、２枚の三層構造の支持体２１を用意し、当該支持体に実装した電子部品を、絶縁層にその上下から埋め込む例を説明した。 As described above, in the second embodiment, two examples of the support 21 having a three-layer structure are prepared, and the electronic component mounted on the support is embedded in the insulating layer from above and below.
１：二層構造の支持体
２１：三層構造の支持体
１ａ，２１ａ：銅
１ｂ，２１ｂ：ニッケル
２１ｃ：銅
２：エッチングレジスト
２ａ：エッチングマスク
３ａ，２３ａ：ＬＳＩ
３ｂ，２３ｂ：チップ抵抗
４，２４：絶縁層
５，２５：電子部品を埋め込んだ絶縁層
６，２６：ビルドアップ基材
７，２７：銅箔
８：非貫通穴
９：貫通穴
１０，３０：回路
１１，３１：層間接続ビア
１２，３２：貫通めっきスルーホール
１３，３３：ソルダーレジスト
1: Two-layer structure support 21: Three-layer structure support 1a, 21a: Copper 1b, 21b: Nickel 21c: Copper 2: Etching resist 2a: Etching mask 3a, 23a: LSI
3b, 23b: chip resistance 4, 24: insulating layer 5, 25: insulating layer embedded with electronic components 6, 26: build-up substrate 7, 27: copper foil 8: non-through hole 9: through hole 10, 30: Circuits 11 and 31: Interlayer connection vias 12 and 32: Through-plating through holes 13 and 33: Solder resist
Claims (10)
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| JP2005271567A JP2007088009A (en) | 2005-09-20 | 2005-09-20 | Method of embedding electronic part and printed wiring board with built-in electronic part |
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| JP2005271567A JP2007088009A (en) | 2005-09-20 | 2005-09-20 | Method of embedding electronic part and printed wiring board with built-in electronic part |
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| JP2007088009A true JP2007088009A (en) | 2007-04-05 |
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| JP2005271567A Pending JP2007088009A (en) | 2005-09-20 | 2005-09-20 | Method of embedding electronic part and printed wiring board with built-in electronic part |
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