KR100997880B1 - Method of interconnection between bonding pad and substrate conducting layer and multi-functional printed circuit board manufactured thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of printed circuit boards, and more particularly to a technology for manufacturing printed circuit boards incorporating semiconductor chips. Instead of performing a separate via processing process for electrical connection with the embedded semiconductor die on the substrate, the bumps formed on the semiconductor die in the laminate lamination process are directly bonded to the wiring conductive layer of the substrate outer layer through the laminated insulation layer in the molten state. The low melting point dissimilar metal, such as tin, is formed on the surface of the conductive layer to allow the low melting point dissimilar metal to be melted under the hot press lamination process conditions, thereby doubling the electrical coupling force between the bump and the conductive layer of the substrate. As a result, unlike the prior art, since the photolithography process and the laser drill process for forming the via hole may be omitted, the manufacturing cost of the chip embedded substrate may be reduced, and the process may be simplified to reduce the defective rate.

Embedded chip printed circuit boards, PCBs, semiconductor dies, low melting point metals, active devices.

Description

METHOD OF INTERCONNECTION BETWEEN BONDING PAD AND SUBSTRATE CONDUCTING LAYER AND MULTI-FUNCTIONAL PRINTED CIRCUIT BOARD MANUFACTURED THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of chip-embedded printed circuit boards (PCBs), and in particular, a bare die chip or a wafer level package (WLP) is mounted on a substrate and then mounted. An interconnect method for electrically connecting one element and an outer layer copper foil circuit of a substrate.

Hereinafter, in the specification and claims, the above bare die chip or wafer level package will be collectively referred to as a "semiconductor die", but need not be limited thereto. Since it is possible to apply to an electric device, an electronic device, a system component, it should be interpreted to apply to all embedded components in the spirit and claims of the present invention.

Recently, in order to improve the portability and maximize the function of electronic devices, a technology of directly embedding an active component such as a bare die chip or a wafer level package into a substrate has been introduced. As such, when the component is embedded in the substrate, the substrate can be miniaturized, the mounting density of the component is increased, and the high frequency characteristics of the electronic circuit are improved.

1A to 1F illustrate a die chip embedded substrate manufacturing method according to the prior art.

The prior art begins by adhesively fixing the semiconductor die 20 onto the substrate 10 using a die attach film or adhesive indicated by numeral 30 (FIG. 1A). Then, the lamination is performed by aligning the first insulating layer 40, the second insulating layer 50, and the conductive layer 60, which have been cavity-processed, on the substrate 10 on which the semiconductor die 20 is mounted. (Fig. 1b).

Here, the prepreg PREPREG may be used as the second insulating layer 50, and copper foil may be used as an example of the conductive layer 60. In another embodiment, the second insulating layer 50 and the conductive layer 60 may use a resin coated copper (RCC).

FIG. 1C shows a substrate in which the semiconductor die 20 is mounted and laminated. Bonding pads 25 are shown on the top surface of the mounted semiconductor die 20, and the conductive pads 25 must be electrically interconnected with the substrate.

In order to electrically connect the bonding pads 25 of the mounted semiconductor die 20 with the copper foil circuits of the substrate, the prior art photographs / exposures / developers / etches images of the conductive layer 60 formed of copper foil on the outer layer of the substrate. A method of selectively connecting the conductive pads and the copper foil of the substrate is used as a method of selectively opening the electrodes, etching the insulating layer to form interlayer vias, and performing plating.

That is, referring to FIG. 1D, a dry film (not shown) is applied to the outer conductive layer 60 of the substrate 10 on which the semiconductor die 20 is mounted, and exposed using an exposure mask according to a selected circuit pattern. By etching, the conductive layer 60 is selectively etched to form openings. Subsequently, referring to FIG. 1E, the CO _{2 in} the opening formed once. The interlayer via hole is formed by irradiating the laser beam to etch the insulating layer until the surface of the bonding pad 25 of the semiconductor die 20 is exposed. Subsequently, referring to FIG. 1F, when copper plating is performed, the pad 25 of the semiconductor die 20 and the conductive layer 60 of the substrate are electrically connected and connected to each other by copper plating.

However, in the related art, in order to interconnect the mounted semiconductor die and the substrate circuit with each other, an image operation is performed on the outer copper foil of the substrate, and the via hole is processed by irradiating a laser beam.

Moreover, there is a disadvantage in that an expensive laser imaging process, such as dry film adhesion, photography, stray light, development, and etching, has to be performed in order to form an opening in the copper foil.

Accordingly, an object of the present invention is to provide a technology that allows the semiconductor die to be electrically connected and interconnected with a substrate circuit while eliminating a high cost and low yield process such as imaging, plating, and via hole laser processing, unlike the prior art.

A method of manufacturing a printed circuit board having a semiconductor die embedded therein, the method comprising: (a) forming a bump on a surface of a bonding pad of a semiconductor die; (b) mounting the semiconductor die having the bumps formed on the bonding pad surface to a substrate using an adhesive film or an adhesive; (c) stacking and arranging a first insulating layer on which a cavity of a size that the semiconductor die is to be placed is placed on the substrate on which the semiconductor die is mounted, and aligned so as to be placed inside the cavity; Stacking and arranging a second insulating layer, a dissimilar metal layer, and a conductive layer on the layer in order; And (d) performing a lamination process on the laminated aligned structure, heating the first and second insulating layers and the dissimilar metal layer to a molten state, and pressing the bumps on the bonding pads in a molten state. And a step of connecting the conductive layer with the molten dissimilar metal when the second insulating layer is pierced and connected to the interface of the conductive layer.

As described above, the present invention can reduce the cost of the substrate manufacturing process by making it possible to conduct electricity to the wiring of the substrate using stud bumps formed on the semiconductor die without a separate via processing process for electrical connection with the semiconductor die embedded in the substrate. There is an advantage to simplify.

Hereinafter, a die chip interconnection method and a printed circuit board manufacturing technology using the same according to the present invention will be described in detail with reference to FIGS. 2A to 2C.

FIG. 2A shows a bare semiconductor die or wafer level package (collectively referred to as a 'semiconductor die') mounted on a substrate 10 using a die attach film or adhesive indicated by numeral 30. It is showing. Unlike the prior art, a bump 26 is formed on the surface of the bonding pad 25 of the semiconductor die 20 mounted on the substrate shown in FIG. 2A.

As a preferred embodiment of the present invention, the bumps 26 formed on the surface of the bonding pad 25 may be manufactured in the form of stud bumps using a wire bonding machine, and the stud bumps may be formed on the surface of the pad 25. The purpose is to allow stud bumps with a sharp protrusion to penetrate the resin layer and make direct contact with the outer layer copper foil without the need to machine via holes in subsequent lamination processes.

As a preferred embodiment of the present invention, the bonding pads 25 are formed of aluminum, and the bumps 26 on the surface may be formed of gold (Au). In addition, the board | substrate 10 shown to FIG. 2A-2C contains the laminated circuit board which the multilayer circuit already processed, The laminated copper foil circuit is not shown in figure in order to simplify drawing.

Subsequently, referring to FIG. 2B, a first insulating layer 40, a second insulating layer 50, and a conductive metal formed with a dissimilar metal 110, having a cavity formed on the substrate 10 on which the semiconductor die 20 is mounted. (60) are arranged in order and laminated, and a lamination process is performed to form a crimp.

At this time, as a preferred embodiment of the present invention, the lamination process proceeds around 200 ° C, the cavity-processed first insulating layer 40 or the second insulating layer 50 can proceed using a prepreg (PREPREG). have. In the laminate heating pressurization process at around 200 ° C., the prepreg undergoes a melting state from the B stage to a C stage.

As a preferred embodiment of the present invention, the conductive layer 60 may use copper foil, and sputtering dissimilar metal 110 on the surface of the conductive layer 60 in contact with the second insulating layer as a characteristic element of the present invention. Or it forms by the plating process, It is characterized by the above-mentioned. As a preferred embodiment of the dissimilar metal 110 formed on the surface of the conductive layer 60, tin (Sn) or an alloy metal including tin may be used, and may be around 200 ° C., which may be transferred to a molten state in other lamination processes. The low melting point metal of can be used.

Here, by forming a low melting point dissimilar metal 110 such as tin to a thickness of about 0.5 to 10 ㎛ by sputtering or plating (plating) method, a low melting point dissimilar metal is melted during the lamination process bump ( Increasing the surface contact force of 26 facilitates interconnection connection between bump 26 and conductive layer 60.

In a preferred embodiment of the present invention, the second insulating layer 50, the dissimilar metal 110, and the conductive layer 60 may use a resin coated with copper foil (RCC), in which tin or It is formed by plating or sputtering low melting dissimilar metals such as alloys including tin.

Referring again to FIG. 2B, the present invention penetrates through the insulating layer PREPREG by a pressure applied to bumps having a pointed shape or a quadrangular shape rising to a similar height during the lamination heat pressurization lamination process, and the conductive layer 60. In this case, the dissimilar metal 110 formed in advance is melted to serve to facilitate bonding between the metals.

Figure 2c is a view showing a cross-section of the laminated substrate after the lamination process in accordance with the present invention. Referring to FIG. 2C, it can be seen that the bonding pads of the semiconductor die and the substrate may be directly interconnected with each other, without additionally performing a via hole processing process. In the hot press lamination process, the pointed bumps 26 are advanced through the resin or the second insulating layer to reach the copper foil layer, that is, the conductive layer 60, and at this time, the dissimilar metal layer 110 having a low melting point such as tin is Melting has the effect of doubling the metal bonding force. Finally, although not shown in the drawings, the copper foil of the outer layer is selectively corroded according to a conventional method to form a copper foil circuit, thereby forming a circuit in which the copper foil of the substrate and the semiconductor die are energized with each other.

The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

 Instead of performing a separate via processing process for electrical connection with the embedded semiconductor die on the substrate, the bumps formed on the semiconductor die in the laminate lamination process are directly bonded to the wiring conductive layer of the substrate outer layer through the laminated insulation layer in the molten state. The low melting point dissimilar metal, such as tin, is formed on the surface of the conductive layer to allow the low melting point dissimilar metal to be melted under the hot press lamination process conditions, thereby doubling the electrical coupling force between the bump and the conductive layer of the substrate. As a result, unlike the prior art, since the photolithography process and the laser drill process for forming the via hole may be omitted, the manufacturing cost of the chip embedded substrate may be reduced, and the process may be simplified to reduce the defective rate.

1A to 1F show a method of embedding a semiconductor die in a substrate according to the prior art;

2A to 2C are views showing a method of electrically connecting a semiconductor die and a substrate by embedding the semiconductor die in a substrate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

    10: Substrate

    20: semiconductor die

    25: bonding pad

    26: bump

    30: die attach film or adhesive

40, 50: insulation layer

    60: conductive layer

   110: dissimilar metal layer

Claims (5)

In the method for manufacturing a printed circuit board containing a semiconductor die, (a) forming a bump on the bonding pad surface of the semiconductor die; (b) mounting the semiconductor die having the bumps formed on the bonding pad surface to a substrate using an adhesive film or an adhesive; (c) stacking and arranging a first insulating layer on which a cavity having a size to which the semiconductor die is placed is placed on the substrate on which the semiconductor die is mounted, and aligned so as to be placed inside the cavity; Stacking and arranging a second insulating layer, a dissimilar metal layer, and a conductive layer on the layer in order; And (d) Lamination process is performed on the laminated alignment structure, but the heating and the first and second insulating layers and the dissimilar metal layer are transferred to the molten state, and the bumps on the bonding pads are pressed in the molten state. Connecting to the conductive layer together with the molten dissimilar metal when the second insulating layer is pierced and bonded to the interface of the conductive layer. Printed circuit board manufacturing method comprising a. The method of claim 1, wherein the dissimilar metal is formed on the conductive layer by sputtering or plating. The method of claim 1, wherein the dissimilar metal is tin (Sn) or an alloy metal including tin. The method of claim 1, wherein the semiconductor die comprises a bare die chip or a wafer level package (WLP). A printed circuit board manufactured by the manufacturing method according to any one of claims 1 to 4.

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