KR101102789B1 - Method of electroplating the hole for the semi-additive process with a heterogeneous metal seed layer - Google Patents

Abstract

PURPOSE: A method of electroplating the hole for a semi-additive process with a heterogeneous metal seed layer is provided to prevent the width of a copper circuit from being decreased in an etching step. CONSTITUTION: A method of electroplating the hole for a semi-additive process with a heterogeneous metal seed layer is comprised of steps: forming a hetero metal layer(30) in the opposite surface of an insulating layer; forming an electroless copper plating layer in the hetero metal layer; forming a via hole(50); coating carbon through electroless-plating; removing the carbon by performing soft etching; forming a mask in the hetero metal layer; and filing copper n the via hole.

Description

Hole plating method of SFA method based on dissimilar metal seed layer {METHOD OF ELECTROPLATING THE HOLE FOR THE SEMI-ADDITIVE PROCESS WITH A HETEROGENEOUS METAL SEED LAYER}

The present invention relates to a semi-additive process (SAP) for fabricating a printed circuit of a fine pattern, and in particular, when a seed layer for forming chemical copper is used as a dissimilar metal, The present invention relates to a new SFA method that solves the problem that copper plating is not performed in a subsequent electroplating process because no seed layer is formed on the sidewall of the insulating layer.

A method for forming a copper foil pattern on a printed circuit board, by coating a dry film (D / F) on the copper foil and selectively removing the dry film to transfer the circuit pattern, by etching the copper foil using the dry film as an etching mask The circuit pattern can be transferred to the copper foil. The above-mentioned method is called a subtractive method, and when the copper foil is etched with a chemical solution, the cross section of the etched copper foil is inclined due to the tendency of the isotopic etching characteristic of the etching solution, so that adjacent copper foil patterns This can lead to access and eventually short circuit.

Due to this problem, in the printed circuit board manufacturing industry, for printed circuit boards having a line width of 25 micrometers or less, instead of the above subtractive method, a dry film plating mask is formed on the surface of the substrate, and only the copper foil is required. An additive process or an SAP process for producing a copper foil circuit by allowing copper plating to proceed is commonly used.

However, in order to apply the SPA method, a copper foil circuit must be formed by flowing electricity to a portion to be copper-plated. In the case of a fine pitch copper foil pattern, it is impossible to supply electricity locally, so that electricity is supplied to the entire substrate. Is being used. To do this, a conductive layer (called the 'seed layer') must be covered to allow electricity to flow through the entire substrate, often with a chemical layer of about 0.4 to 0.6 micrometers thick to the seed layer. On top of that, a dry film plating mask is formed and electroplating is performed. After copper plating is performed to form a copper foil pattern, the dry film is peeled off and a soft etching is performed with a chemical solution to remove the chemical copper which used as a seed layer.

However, in the process of soft etching with chemical solution, the chemical solution attacks not only the chemical copper used as the seed layer, but also the electroplated copper layer forming the copper foil circuit, so that the pitch of the copper foil circuit formed of the electroplated copper is damaged. A problem arises. Thus, in order to prevent the electroplating layer from being etched together when removing the seed layer, a technique of using a dissimilar metal instead of copper as a seed layer has been proposed. After supplying power using dissimilar metals as seed layers for electroplating, the copper foil may be removed by using a selective etch in which the etch rate for the dissimilar metal is relatively higher than that for copper in the seed layer removal step. It is possible to prevent damage during the soft etching process. The SPA method using dissimilar metals is disclosed in Korean Patent Publication No. 10-2010-0019000, which is a prior art of the applicant of the present patent application.

As such dissimilar metals, silver (Ag), tin (Sn), nickel (Ni), and the like are used. When using dissimilar metals as seed layers, a seed layer may be formed on the surface of the substrate, but the inner wall of the hole having steps In particular, there is no method of applying a seed layer on the sidewall surface of the insulating layer, so there is a problem in that copper plating cannot be filled on the inner wall of the hole even when electroplating is performed.

Accordingly, it is a first object of the present invention to provide a printed circuit board manufacturing method which can define a pitch of a copper foil circuit into a fine pattern on the order of several micrometers.

A second object of the present invention is to provide a method for allowing electroplating to be carried out on the inner wall of a hole even in the case of using a dissimilar metal as a seed layer of the SAP method in addition to the first object.

In order to achieve the above object, the present invention forms the seed layer by applying carbon (C) to the epoxy surface by an electroless plating method to enable electroplating not only on the substrate surface but also on the inner wall of the hole. The present invention is characterized in that the seed layer on the surface of the substrate is formed of a dissimilar metal, and the seed layer on the inner wall of the hole is formed of a carbon electroless plating layer.

In the present invention, a dissimilar metal such as silver (Ag), nickel (Ni), tin (Sn), or an alloy thereof is coated, and electroless plating is performed thereon to apply a chemical copper / dissimilar metal to the substrate. Subsequently, when a via hole is required, a hole is made by laser or mechanical drill to expose the lower copper foil surface. Then, carbon (C) is applied to the entire surface of the substrate by electroless plating. At this time, carbon is not only applied to the surface of the chemical copper, but also to the epoxy side of the hole sidewall exposed by hole processing. By the way, the carbon coated on the chemical copper is roughly formed, so that the surface adhesion is small, and when the soft etching is performed, the chemical copper is removed together with the carbon even though the carbon is covered on the chemical copper.

Meanwhile, in the soft etching process, the carbon applied to the inner wall of the hole remains on the surface of the insulating layer. As a result, the surface of the substrate is covered with a dissimilar metal and carbon is covered on the epoxy surface such as the inner wall of the hole so that the seed layer is applied to all surfaces of the substrate. Is formed. Subsequently, after the dry film plating mask is manufactured, the copper foil may be formed only on a desired portion by performing electroplating.

The present invention provides a conductive layer for electroplating on the entire surface of the substrate by forming a seed layer of a dissimilar metal on the surface of the substrate and a seed layer of carbon on an epoxy surface such as a hole inner wall. As a result, the width of the copper foil circuit can be prevented from being reduced in the flash etching step for removing the seed layer, and the via hole filling can be performed, thereby enabling the manufacture of a fine pitch printed circuit board.

1A to 1I illustrate a method of manufacturing a printed circuit board according to the present invention.

SPA method according to the present invention comprises the steps of (a) forming a dissimilar metal on the insulating layer surface; (b) forming copper (Cu) on the dissimilar metal surface; (c) forming a via hole to electrically connect the copper foil formed in the lower layer of the insulating layer with the upper layer; (d) applying carbon to the entire surface of the substrate; (e) applying a dry film and transferring the selected circuit pattern to the dry film to form a mask; (f) performing soft etching using the mask as an etching mask to remove copper (Cu) on the dissimilar metal surface; And (g) electroplating to fill the via holes and form a copper foil circuit on the upper layer. (h) exfoliating and removing the dry film mask and removing the moving metal with a selective etching solution.

The present invention provides a method of manufacturing a printed circuit board, comprising: (a) forming a first conductive layer on an upper surface of an insulating layer on which copper foil is formed; (b) forming a second conductive layer on the surface of the first conductive layer; (c) forming a via hole to electrically connect the copper foil formed under the insulating layer; (d) applying a third conductive layer to the entire surface of the substrate including the inner wall of the insulating layer exposed by the via hole and the surface of the lower copper foil; (e) selectively etching away the second conductive layer and allowing the third conductive layer to remain on the inner wall of the via hole not coated with the second conductive layer, wherein the third conductive layer is coated on the second conductive layer during the selective etching of the second conductive layer. Etching the conductive layers together; (f) applying a dry film and transferring the selected circuit pattern to the dry film to form a mask; (g) electroplating to fill the via holes and form a copper foil circuit on the upper layer; And (h) exfoliating and removing the dry film mask and removing the exposed first conductive layer.

Hereinafter, a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to FIGS. 1A to 1I.

In order to clearly explain the idea of the present invention, the copper foil circuit is formed by applying the SAP method according to the present invention to the upper layer of the substrate on which the copper foil is formed under the insulating layer, and at the same time, the lower copper foil and the upper layer The manufacturing process of the via holes connecting the copper foil circuits of each other is described with reference to the accompanying drawings, but the present invention is not necessarily limited thereto.

First, the dissimilar metal 30 is formed on the surface of the insulating layer 20 of the substrate on which the copper foil is to be formed by the SPA method according to the present invention. In the specification of the present invention, the dissimilar metal 30 refers to a metal other than copper (Cu), and silver (Ag), nickel (Ni), tin (Sn), or an alloy thereof may be used. Here, the insulating layer 20 may be a prepreg (prereg) or a resin (resin), and as a different metal 30, not copper (Ag), nickel (Ni), tin (Sn) or These alloys can be formed by various methods, such as plating or substitution plating, sputtering. FIG. 1A shows a state where dissimilar metals are applied to a substrate on which copper foil is formed on a lower layer.

Subsequently, as shown in FIG. 1B, an electroless plating process is performed to form copper foil on the dissimilar metal 30. Commonly, copper formed by an electroless plating process is called chemical copper 40. Then, the via hole 50 is processed by performing a laser via process or a drill process with respect to the site | part which wants an electrical connection between the copper foil 10 of a lower layer, and an upper copper foil. As a result, as shown in Fig. 1C, the surface of the lower copper foil 10 is exposed, and the insulating layer sidewall surface of the hole inner wall is exposed.

The present invention is characterized in that the seed layer is also formed on the sidewall surface of the insulating layer of the hole inner wall by applying carbon (C). According to a preferred embodiment of the present invention, as shown in FIG. 1D, carbon can be applied to the substrate surface and the entire inner wall of the hole by performing an electroless plating process. As a result, the dissimilar metal 30, the chemical copper 40, and the carbon 60 are covered on the substrate surface, and the carbon 60 is covered on the inner wall of the via hole 50 insulating layer and the surface of the copper foil 10 in the lower layer. do.

Subsequently, when the soft etching used to remove copper in the art is performed, the chemical copper 40 on the surface is removed, and since the carbon 60 is densely formed on the chemical copper 40, the carbon ( 60 is removed together with the chemical copper 40.

Referring to FIG. 1E, the carbon 60 on the surface of the substrate is removed together with the chemical copper 40 in the soft etching process, but the carbon 60 applied to the inner wall of the hole remains as it is. As a result, referring to FIG. 1E, since the dissimilar metal 30 is covered on the substrate surface, the carbon is covered on the inner wall of the hole, and the surface of the copper foil 10 of the lower layer is exposed, eventually they are transferred to the seed layer in a subsequent electroplating process. It will work. Then, in order to selectively perform electroplating to form copper foil by an additional method, a dry film is coated and a photo pattern of exposure, transfer, and etching is performed according to a circuit pattern prepared in advance, and then the circuit pattern transfer process is performed.

FIG. 1F illustrates a state in which the via hole 50 is exposed and the remaining portion is covered with the dry film 70 as one embodiment of the present invention. Subsequently, when copper plating is performed, copper 80 is formed on the copper foil 10 serving as the seed layer, the carbon 60 on the inner wall of the hole, and the dissimilar metal 30 on the substrate surface. Subsequently, when the mask of the dry film 70 is peeled off, the copper foil circuit is formed on the upper layer of the substrate as shown in FIG. 1H, and the copper foil circuit of the upper layer and the copper foil circuit of the lower layer are electrically connected through the via hole filled with electroplating at a desired portion. .

Referring to FIG. 1I, finally, the seed layer 30 is etched away using a selective etchant to complete the copper foil circuit. In this case, the selective etching solution refers to a solution in which metals such as nickel and tin are etched but copper is not etched. In practice, it is meant a solution in which the etch rate for metals such as silver, nickel, tin, etc. is relatively low compared to the etch rate for copper. For example, to selectively etch away silver, a cyanide (CN ⁻ ) chemical solution such as potassium cyanide (KCN), ferricyanide or ferrocyanide may be used. Selective etching solutions for silver, nickel, tin, or copper of these alloys are readily available from common chemical companies and are well known in the art.

The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

The present invention is characterized in that carbon is used as a seed layer on the sidewall of a stepped insulating layer structure such as an inner wall of a hole, thereby solving the problem of filling via holes with electroplating, which is not solved by the prior art. As a result, the present invention makes it possible to fabricate a micropattern printed circuit of several micrometers pitch by an addition method.

The present invention prevents the pitch of the copper foil circuit from being changed in the flash etching step for removing the seed layer by using silver, nickel, tin, or an alloy thereof, which can selectively etch the seed layer of the SAP process (SAP). As a result, it is possible to produce a fine pitch printed circuit board.

10: copper foil
20: insulation layer
30: dissimilar metal
40: chemical copper
50: Via Hole
60: carbon
70: dry film
80: copper

Claims (4)

In the method of manufacturing a printed circuit board,
(a) forming a dissimilar metal layer comprising any one of silver, nickel, tin, or an alloy thereof on an opposite surface of the insulating layer having copper foil formed on one surface thereof;
(b) forming an electroless copper plating layer on the dissimilar metal layer surface;
(c) exposing one surface of the copper foil by selectively etching the electroless copper plating layer, the dissimilar metal layer, and the insulating layer to form via holes;
(d) electroless plating and coating carbon (C) on the inner wall of the insulating layer and the surface of the copper foil exposed by the via hole and the surface of the electroless copper plating layer;
(e) performing soft etching to remove both the electroless copper plating layer and the carbon applied on the electroless copper plating layer;
(f) applying a dry film and transferring the selected circuit pattern to the dry film to form a mask on the dissimilar metal layer;
(g) Filling the via hole with copper by electroplating such that copper (Cu) is formed on the exposed copper foil surface, via hole inner wall, and exposed dissimilar metal layer surface while the mask is covered. Making; And
(h) exfoliating the mask and etching away the exposed dissimilar metal layer;
Printed circuit board manufacturing method comprising a. delete delete delete

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