KR100934106B1 - Complete Addition Method for Fabrication of Fine Pitch Printed Circuit Boards - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complete addition process (FAP) for making the pitch of copper foil circuits to a few tens of micrometers on a printed circuit board. The present invention relates to a printed circuit board manufacturing technology that solves the undercut problem.

According to the present invention, an electrophoretic plating process is performed, unlike conventional semi-addition method, by chemically plating the dry film after processing a hole for interlayer connection to the insulating layer substrate and performing an image process according to a circuit pattern. It is not necessary and the flash etching process can be omitted. As a result, unlike the prior art, the problem of narrowing the width of the wiring copper foil or the undercut problem of chemical copper is solved.

Printed Circuit Board, PCB, Semi Additive Process, SAP, FAP, Chemical Copper, Fine Pattern.

Description

FULL-ADDITIVE PROCESS FOR A FINE-PITCH PRINTED CIRCUIT BOARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full-additive process (FAP) for making a pitch of copper foil circuits on a printed circuit board to a level of tens of micrometers. The present invention relates to a conventional semi-additive process (SAP). The present invention relates to a printed circuit board manufacturing technology which has solved the problem of undercut of copper copper generated during flash etching, narrowing of wiring width, and uneven etching of wiring roughness. In other words, the present invention is a method that solves the problem of the conventional semi-addition method for manufacturing a printed circuit board, in particular a printed circuit board manufacturing technology that enables the formation of a pattern of fine pitch length of several tens of micrometers level. It is about.

In recent years, as the size of a notebook computer becomes thinner, such as a few millimeters, as electronic devices become smaller and slimmer, a technology for miniaturizing a copper foil circuit pattern of a printed circuit board has been introduced.

In general, a process of forming a copper foil circuit on a printed circuit board is as follows. That is, the dry film (D / F) is tightly coated on the copper foil coated on the insulating layer, and the dry film is selectively defined as a dry film by selectively removing the dry film according to the circuit diagram and the copper foil part to be removed and the copper foil part to be left. Subsequently, a circuit is formed by treating the substrate on which the dry film is selectively coated with a corrosion solution such as copper chloride to etch away the exposed copper foil. However, in order to form a fine circuit pattern, the pitch length between a circuit line masked with a dry film and an adjacent circuit line should be able to be refined to, for example, several micrometers to several tens of micrometers. However, when the copper foil is wet etched using an etchant such as copper chloride, a phenomenon in which the cross section of the copper foil etched by the isotropic etching characteristic of the wet etching does not have a vertical shape but has an inclined cross section often occurs.

Such an inclined cross section does not cause a problem when the line width pitch is relatively large, but when the circuit pitch approaches the thickness of the copper foil (for example, several tens of micrometers pitch), there is a risk of short circuit between the circuits.

1 is a view showing a cross-sectional profile of an etched copper foil when the etching process is performed after forming a pattern with a dry film on the copper foil coated on the insulating resin according to the prior art. Referring to FIG. 1, when wet etching is performed using a copper chloride solution having a patterned dry film 50 on the copper foil 15, it may be observed that the cross-section of the etched copper foil is inclined due to the isotropic etching property. . That is, as shown in FIG. 1, the pitch length cut by the dry film 50 is L, but the pitch length of the etched copper foil circuit is reduced to L ', compared with the given copper foil thickness to form a fine circuit pattern. If the pitch length is reduced, the circuit may be shorted due to the isotropic etching characteristic.

A semi addition method (SAP) has been proposed and used to solve the problem of inclination of the copper foil cross section due to the isotropic etching characteristic problem of the etching solution and to refine the copper foil circuit pitch. In the SAP process of the art, instead of etching copper foil, it is possible to form a copper foil circuit having a relatively vertical step by first forming a dry film pattern having a substantially vertical shape, and then performing electrocopper plating on the substrate on which the dry film pattern is formed. When the semi-addition method is applied, it is possible to overcome some of the limitations of circuit tightness and miniaturization experienced in the conventional etching process, and the circuit shaping characteristics can be improved.

2a to 2h is a view showing a semi addition method according to the prior art. As mentioned above, the conventional copper foil circuit forming method forms an image on a plated plate by etching and then cuts copper (Cu) to form a circuit, whereas the SAP method performs a dry film developing process on a plate. Proceeding to form an image and pattern plating to form a circuit.

The point of the conventional semi-addition method is that dry film pattern formation with a vertical step is relatively easy to realize in the process of forming a pattern with a dry film. Therefore, dry film is formed by first copper plating after forming a dry film pattern with a vertical step. It is to obtain copper of vertical step according to shape.

Hereinafter, the semi-addition method according to the prior art will be described in detail with reference to FIGS. 2A to 2H, and a problem thereof will be pointed out. Referring to FIG. 2A, first, a hole is formed by drilling to form an interlayer connection hole for interlayer connection between an upper layer and a lower layer in an insulating layer 10 such as a prepreg (FIG. 2B). ).

As shown in FIG. 2B, the hole 30 is formed to electrically connect the upper copper foil circuit and the lower copper foil circuit to each other. After the hole processing, the desmear process is performed to smoothly perform the subsequent plating process.

Here, the desmear process removes residues generated during the drilling process when drilling is performed to form holes, and roughness, that is, roughness (surface roughness) on the surface of the inner wall of the hole so that the plating proceeds smoothly during the subsequent plating process. A process for providing a hole processing and a desmear process is described in Korean Patent Publication No. 10-2004-0062723, which is the prior art document of the applicant.

Referring again to FIG. 2C, electroless copper plating is performed to coat the chemical copper 40 on the surface of the substrate and the inner wall surface of the exposed hole 30. Subsequently, the dry film (D / F) 50 is closely coated on the surface of the substrate, and the dry film 50 is selectively etched in order to selectively mask portions to be copper plated and portions not to be formed in a subsequent electroplating process. To form (FIG. 2D).

Then, when the copper copper plating is performed as shown in FIG. 2E, the electrolytic copper is not formed where the dry film 50 remains, and the electrolytic copper 60 is formed only on the portion where the remaining electricity flows, that is, the chemical copper 40. do. Here, it is noted that both the chemical copper 40 and the copper copper 60 are copper (Cu), but are shown separately because the etching characteristics are different in the subsequent flash etching process.

Subsequently, after peeling off the dry film 50 as shown in FIG. 2F, a copper foil circuit having a relatively vertical step is formed in the upper layer and the lower layer. Referring to FIG. 2F, the chemical copper 40 remains on the peeled dry film 50 spot (indicated by the dashed circle), and the portion that has been shorted only after the chemical copper 40 is removed is removed to the left copper foil and the right copper foil. This is separated and a copper foil circuit is finally formed.

To this end, in the conventional semi-addition process (SAP), as shown in Figure 2g by performing a flash etching (flash etching), that is, using a method of etching the entire surface of the chemical copper 40 by slightly immersing the substrate in the etchant. FIG. 2G shows the state in which the chemical copper 40 exposed to the surface of the substrate is etched away as a result of flash etching, and the step of the cross section of the etched copper foil has a relatively vertical cross section.

However, a phenomenon in which the wiring width becomes narrow during the flash etching process of the conventional semi addition method occurs. That is, as shown in Figs. 2G and 2H, a problem may occur in which the width of the wiring decreases from L to L-? L. In addition, due to the difference in the etching rate in the wet etching solution between the electroless copper plating and the electrolytic copper plating (generally, the electroless copper plating, that is, the etching rate of the chemical copper is larger than the etching rate of the copper copper), as shown in FIG. 2H That is, an undercut (80) occurs in the chemical copper, which may cause a problem that the length of the chemical copper is narrowed by ΔL '. As a result, the wiring width becomes narrow due to flash etching, and technical problems such as uneven progress of the etching in the wiring rough portion occur.

Accordingly, a first object of the present invention is to provide a printed circuit board manufacturing method which can define a pitch length of a copper foil circuit into a fine pattern on the order of tens of micrometers.

It is a second object of the present invention to provide a novel printed circuit board manufacturing method which solves the above-mentioned problems by omitting the flash etching process performed in the existing semi addition method (SAP) in addition to the first object.

In order to achieve the above object, the present invention is characterized in that instead of performing a chemical copper to plate the surface of the inner wall of the hole after the hole processing, to form a circuit pattern with a dry film in advance, forming a pattern image Subsequently, chemical copper is performed subsequently, the copper foil circuit connected between layers is formed, and a dry film is peeled off. It is characterized by the above-mentioned.

Since the present invention can omit the flash etching process that the semi-addition method (SAP) must proceed, it is advantageous for miniaturizing the circuit pattern to about 40 μm, and there is no problem of narrowing the wiring width. In addition, data circuit reinforcement due to flash etching can be reduced, thereby increasing work efficiency and reducing costs. In addition, according to the present invention, since the product shape is made through electroless copper plating, it is possible to expect an advantage of not requiring expensive electrophoretic equipment investment, and to improve yield by reducing plating variation.

According to an aspect of the present invention, there is provided a method of manufacturing a printed circuit board, the method comprising: (a) forming a hole for interlayer connection by drilling a predetermined position on an insulating layer substrate; (b) forming a catalyst for electroless copper plating on the inner wall surface of the hole in front of the holed substrate; (c) tightly coating a dry film on a substrate having the catalyst formed thereon and selectively removing the dry film according to a given circuit pattern to selectively expose the catalyst-coated substrate according to the circuit pattern; (d) performing electroless copper plating to form chemical copper only on the exposed substrate surface not masked by the dry film; And (e) removing the dry film to form a copper foil circuit having an upper layer and a lower layer energized by an interlayer connection hole.

Hereinafter, a preferred embodiment of a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to FIGS. 3 and 4.

Referring to FIG. 3A, the present invention begins with an insulating layer 10, such as a prepreg. As shown in FIG. 3B, a drill process is performed at a desired position for interlayer connection to the insulating layer 10 to form a hole 30 for interlayer electrical connection (FIG. 3B).

Subsequently, the residue remaining on the inner wall surface of the hole for the interlayer connection is removed according to the conventional method, and the desmear process is performed for the surface roughness treatment. That is, the cleaning process for degreasing the residues and the like remaining after the hole processing and the soft etching process may be performed to give the surface a roughness, that is, roughness. Subsequently, a pre-dip process for water removal and atmosphere composition is carried out, and a catalyst for chemical copper is formed on the entire surface of the substrate through surface treatment with a tin-palladium (Sn-Pd) colloid solution or a complexing liquid. And surface treatment steps such as acid activation treatment for removing tin (Sn) are performed. Details of the degreasing process to the acid activity treatment will be described later with reference to FIG. 4.

FIG. 3C is a view showing a catalyst 45 for chemical copper formed on a hole processed substrate through the above-described degreasing process or acid activation treatment process. Referring to FIG. 3C, a catalyst is applied to the surface of the insulating layer substrate on which the hole 30 is drilled and the surface of the inner wall of the hole. Next, in the present invention, the dry film 50 is brought into close contact with and developed as shown in FIG. 3D to selectively remove the dry film according to the circuit diagram to form a pattern. According to the present invention, unlike the conventional semi-addition method, the circuit pattern image work is performed before the chemical copper process, and the chemical copper is not used as an auxiliary step for subsequent electrophoresis, but only by copper copper. There are technical features to form.

Then, electroless copper plating is performed as shown in FIG. 3E to form chemical copper 40 on the entire surface of the substrate not covered with the dry film 50. Here, since the dry film 50 masks the catalyst in the part where the dry film 50 is covered, no chemical copper is formed on the dry film 50 even when electroless copper plating is performed. Here, unlike the semi-addition method (SAP) according to the prior art, the electrolytic copper plating time is long so that the chemical copper serves as an interlayer connection copper foil so that the thickness of the chemical copper coating layer is sufficiently thick. Finally, referring to FIG. 3F, a copper foil circuit having a complete interlayer connection is formed simply by peeling off the dry film 50, and no additional flash etching process is required to separate wiring of adjacent circuits. .

4 is a flowchart illustrating a method of manufacturing a printed circuit board according to the present invention in detail. Referring to FIG. 4, first, hole processing is performed on the insulating layer substrate (step S400), and a cleaning and degreasing process is performed to remove residues remaining on the inner wall of the hole (step S410). Then, a soft etching process is performed to provide roughness on the surface (step S420). On the other hand, foreign matter or moisture adhering to the substrate surface may contaminate the catalytic treatment bench in the subsequent step, so that the pre-dip treatment is performed in step S430.

Subsequently, a catalyst for chemical copper is formed on the entire surface of the substrate through surface treatment with a tin-palladium (Sn-Pd) colloidal solution or a complexing liquid (step S440). Subsequently, the accelerated process accelerator removes the tin Sn by about 1/2 to 1/3 so as to further improve the adhesion during the electroless plating (step S450).

Then, the image operation (step S460) for the dry film is performed according to the given circuit pattern, and the chemical copper is performed (step S470) to form the interlayer connection copper (Cu). Finally, the dry film which completed the mission is peeled off (step S480).

The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

The present invention is characterized in that instead of performing chemical copper to plate the surface of the inner wall of the hole after the hole processing, the circuit pattern is imaged with a dry film in advance. It forms a copper foil circuit connected between layers, and peels and removes a dry film, It is characterized by the above-mentioned. As a result, the flash etching step required in the conventional semi addition method can be omitted, and as a result, the above-mentioned problems occurring in the flash etching process are solved.

1 is a view of forming a copper foil circuit according to the prior art.

2a to 2h show a semi addition process (SAP) according to the prior art;

3a to 3f are detailed views of a method for manufacturing a printed circuit board according to the present invention.

4 is a flowchart showing a detailed process for explaining a method of manufacturing a printed circuit board according to the present invention;

<Explanation of symbols for the main parts of the drawings>

10: insulation layer

30: hall

40: chemical copper

45: catalyst

50: dry film

80: undercut

Claims (1)

In the method of manufacturing a printed circuit board, (a) drilling a predetermined position on the insulating layer substrate to form holes for interlayer connection; (b) forming a catalyst for electroless copper plating on the inner wall surface of the hole in front of the holed substrate; (c) tightly coating a dry film on a substrate having the catalyst formed thereon and selectively removing the dry film according to a given circuit pattern to selectively expose the catalyst-coated substrate according to the circuit pattern; (d) performing electroless copper plating to form chemical copper only on the surface of the substrate selectively exposed by the dry film; And (e) removing the dry film to form a copper foil circuit in which an upper layer and a lower layer are energized by an interlayer connection hole; Printed circuit board manufacturing method comprising a.

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