JP2850579B2 - Film carrier for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier for a semiconductor device, and more particularly to a TAB (Tape Automa).
The present invention relates to a film carrier for ted bonding.

[0002]

2. Description of the Related Art In mounting semiconductor elements, TAB is used for automation in order to mass-produce semiconductor devices having a certain level of performance or higher at high speed. In this TAB, continuous mounting is enabled by bonding a copper foil patterned on a continuous belt-shaped film carrier to a semiconductor element by wireless bonding.

FIGS. 4 and 5 show an example of mounting using this TAB. FIG. 4 shows a film carrier 1 in which an inner lead 6 and an outer lead 7 are pattern-formed on a long flexible insulating film 2. The film carrier 1 has thinner leads 6 and electrodes on a semiconductor element 12. By aligning the Au bumps 13 and pressing the bonding tool 14 in a heated state, the inner leads 6 and the Au bumps 13 of the semiconductor element 12 are bonded. After the inner lead bonding, the semiconductor element 12 and the inner lead 6 are sealed with a mold resin 15 as shown in FIG. 5 as necessary, separated from the film carrier 1, and then provided for outer lead bonding as shown in FIG. Is done. In FIG. 5, reference numeral 16 denotes an external wiring board, and a conductor pattern 1 for wiring is provided on the upper surface.
7 are formed. After the conductor pattern 17 of the external wiring board 16 and the outer lead 7 of the film carrier are aligned, they are pressed by the bonding tool 14 in a heated state to join them.

FIG. 3 is a sectional view of a part of a conventional film carrier, and corresponds to a sectional view taken along lines AA and BB in FIG. 2 described later. This film carrier is provided with device holes 4a in a flexible insulating film 2 such as a polyimide resin.
After the outer hole 4b, the sprocket hole 3 and the like are formed by punching, a copper foil 8 is adhered, and the copper foil 8 is etched by a photo-etching method to form an inner lead 6 and an outer lead 7 having a predetermined pattern. Have been obtained. The plating layer 11 is applied to the inner lead 6 and the outer lead 7 in order to make good connection between the electrode of the semiconductor element and the conductor pattern of the external wiring board. The plating layer 11 has a low melting point and good bonding properties such as Sn or Sn alloy (for example, Sn-
Pb alloy) is formed on the entire surface of the inner lead 6 and the outer lead 7. In this case, the plating layer 11 at the bonding portion is provided for bonding with the electrode of the semiconductor element and the conductor pattern of the external wiring board, and is also provided for preventing oxidation and corrosion of the copper foil 8.

[0005]

However, in the conventional film carrier, needle-like metal single crystals called whiskers are generated from Sn or Sn alloy of the plating layer 11 applied to the entire inner lead 6 and outer lead 7. However, there is a risk of short-circuiting between adjacent leads, between electrodes of a semiconductor element, or between conductor patterns on an external substrate. Further S
Since the n or Sn alloy plating layer is soft and has low mechanical strength, the n or Sn alloy plating layer is easily scratched by rubbing or contact with an external member, and the scratch may expose the internal copper foil to oxidize and corrode. In order to prevent the generation of the whiskers described above, it is generally necessary to perform a heat treatment at about 100 ° C. after the plating step. However, such a treatment is not only troublesome, but also causes an oxide film to be formed by heating, which causes problems such as a decrease in solder wettability and bonding property and further discoloration.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned disadvantages of the prior art and to greatly increase the number of pins without generating whiskers, having high mechanical strength, and without causing oxidative corrosion. It is to provide a novel film carrier for a semiconductor device.

[0007]

The gist of the present invention is that Pd is used as a film carrier plating layer for a semiconductor device.
Or Ni or N as a base with using Pd alloy
i-alloy plating layer and the Pd or Pd alloy concerned
The plating layer and Ni or Ni alloy plating layer are suitable for the above purpose.
The thickness of Sn and S
Heat resistance and corrosion resistance are significantly improved as compared with the n-alloy plating layer. Furthermore, the plating layer of Pd or Pd alloy is Sn
Also, there is no problem of whisker generation and migration from the Sn alloy plating layer, and the solder wettability is good, which leads to improvement of reliability.

An object of the present invention is to provide a flexible insulating film.
Etching the copper foil adhered to the inner lead and the inner lead joined to the electrode of the semiconductor element and the outer lead joined to the external wiring board connected to the inner lead
In the film carrier for a semiconductor device having a pattern formed on the flexible insulating film, at least the inner lead and the outer lead have a thickness of 0.3 to 1.0 μm on a bonding surface of the semiconductor element electrode and the wiring substrate . Ni
Or, with a Ni alloy plating layer as a base, a thickness of 0.01 to
1.0 μm Pd or Pd alloy plating layer is applied
That it is achieved by a semiconductor device for a film carrier, characterized in that.

As the film carrier used in the present invention, a flexible insulating film made of a polyimide resin, a polyester resin, a glass epoxy resin or the like is used.

In the present invention, a copper foil is used as a material of the inner lead and the outer lead, and the type of the copper foil may be any of a rolled copper foil and an electrolytic copper foil.

In the present invention, the plating film of Ni and the Ni alloy as the base of the Pd or Pd alloy plating layer is preferably thicker, but is harder. Therefore, when a step such as bending is included, a phenomenon such as cracking is observed. , 0.3 to 1.0 μm .

The plating film of Pd and Pd alloy in the present invention requires a coating in the range of 0.01 to 1.0 μm in order to satisfy the characteristics, but it is desirable to use a plating layer as thin as possible because the cost is high.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a plan view of an embodiment of the film carrier for a semiconductor device according to the present invention. FIG. 1 is a sectional view taken along line AA of FIG. 2 and a sectional view taken along line BB of FIG. And the same elements as those in the prior art are assigned the same reference numerals. The film carrier 1 includes a flexible insulating film 2 made of a polyimide resin, a polyester resin, a glass epoxy resin or the like, and leads 5 of a metal conductor film such as a copper foil patterned on the insulating film 2. The insulating film 2 has a long continuous band shape, and sprocket holes 3 are formed by punching at predetermined intervals on both sides in the width direction.
A device hole 4a for positioning a semiconductor element (not shown) is formed at the center in the width direction, and an outer hole 4b facing the conductor pattern of an external wiring board (not shown) is formed outside the device hole 4a. Is formed. The lead 5 has an inner lead 6 inside and an outer lead 7
Are formed continuously on the outside, and the inner leads 6 are formed.
Extend into the device hole 4a of the insulating film 2 as shown in FIG. The outer lead 7 connected to the inner lead 6 has an outer hole 4b.
It extends outwardly past the top. In such a structure,
The tip of the inner lead 6 extending into the device hole 4a is joined to the electrode of the semiconductor element, and the outer lead 7
Is separated from the film carrier and the outer hole 4b
Through the wiring 17 of the external wiring board 16.

As shown in FIG. 1, the inner lead 6 and the outer lead 7 are each provided with a 0.3 to 1.0 μm thick Ni or Ni alloy plating layer 9 on the entire surface, and at least the inner lead 6 and the outer lead 7 are provided thereon. Seventh semiconductor element 12
The thickness of the bonding surface between the electrode and the wiring board 16 is 0.01 to 0.01 mm.
1.0 μm Pd or Pd alloy plating layer 10 is applied,
The entire surface of the inner lead 6 and the outer lead 7 is covered with a plating layer 9 or 10. As shown in FIGS. 4 and 5, the lower surface of the inner lead 6 is joined to the electrode of the semiconductor element, and the lower surface of the outer lead 7 is joined to the conductor pattern of the external wiring board. The lower surface of 7 is a joining surface. Since the Pd or Pd alloy plating layer applied to such a bonding surface is chemically stable and does not easily form an oxide film, the bonding with the semiconductor element or the external wiring board can be performed well. Furthermore, the Pd or Pd alloy plating layer has high corrosion resistance and is hard, and contributes to protection of these leads 6 and 7 by being formed on the upper surface and side surfaces of the inner lead 6 and the outer lead 7 other than the above-mentioned joint surface. I do. That is, the semiconductor element, for bonding with an external wiring substrate, the bonding tool is lowered into the inner leads 6 or the outer lead 7 to the upper surface of the lead 6, 7 Ni or or Pd or Ni alloy plating layer 9 A Pd alloy plating layer 10 is provided. Since the plating layers 9 and 10 are hard, they are hardly damaged, and prevent oxidation and corrosion of the inner inner lead 6 and the outer lead 7.

On the other hand, the plating layer of Ni or Ni alloy is stable with respect to the ammonia-based plating solution, and is composed of Pd or Pd.
By being applied as a base of the plating layer of the alloy, it is possible to prevent contamination due to dissolution of copper, which is a base material, into the plating solution of Pd or a Pd alloy, which is an ammonia-based plating solution. Further, the plating layer of Ni or Ni alloy is corrosion resistant, and prevents the formation of an internal battery at the plating interface in order to prevent the elution and diffusion of copper in the base material, and to prevent the inner lead 6 and the outer lead 7 from forming.
The corrosion resistance is increased.

[0017]

As described above, the film carrier for a semiconductor device of the present invention has a thickness of at least 0.01 to 1.0 μm on the joint surface of the inner lead and the outer lead with the electrode of the semiconductor element and the wiring board. of Pd or Pd alloy plating layer is also thick as its underlying 0.3-1.0
μm Ni or Ni alloy plating layer is applied,
The contamination of the plating solution of Pd or Pd alloy can be prevented, and the corrosion resistance of the lead can be further improved. Further, Pd or Pd alloy is chemically stable, hardly forms an oxide coating, enhances bonding property, is hard and is hardly damaged, can protect the surface of the lead, and can improve reliability. .

Also, there is no concern about the generation of whiskers.

Pd or a Pd alloy is less expensive than Au plating.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view taken along line AA of FIG. 2 of the present invention (A).
And a sectional view taken along line BB (B).

FIG. 2 is a plan view showing one embodiment of a film carrier for a semiconductor device of the present invention.

FIGS. 3A and 3B are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB of an example of a conventional film carrier for a semiconductor device, corresponding to FIGS. 1A and 1B.

FIG. 4 is a cross-sectional view showing an example of mounting a semiconductor element by TAB.

FIG. 5 is a sectional view showing an example of mounting to an external wiring board by TAB following FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Film carrier 2 Insulating film 3 Sprocket hole 4a Device hole 4b Outer hole 5 Lead 6 Inner lead 7 Outer lead 8 Copper foil 9 Ni or Ni alloy plating layer 10 Pd or Pd alloy plating layer 11 Sn or Sn alloy plating layer 12 Semiconductor element 13 Au bump 14 Bonding tool 15 Mold resin 16 External wiring board 17 Wiring

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-54-121670 (JP, A) JP-A-63-2358 (JP, A) JP-A-3-274741 (JP, A) JP-A 50-121 139671 (JP, A) JP-A-2-224257 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/60 311

Claims (1)

(57) [Claims] 1. A copper foil adhered to a flexible insulating film is etched.
And etching, the inner leads are bonded to the electrode of the semiconductor element, a semiconductor device for film carriers patterned outer leads are bonded to the external wiring substrate provided continuously to the inner leads on the flexible insulating film In at least, at the bonding surface between the electrode of the semiconductor element and the wiring board of the inner lead and the outer lead,
0.3-1.0 μm thick Ni or Ni alloy plating layer
Pd or Pd having a thickness of 0.01 to 1.0 μm as a base
A film carrier for a semiconductor device, which is provided with an alloy plating layer.