JP2974840B2 - Semiconductor element mounting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial shaped FIELD The present invention relates to a mounting method of a semiconductor device using a suitable mounting materials in connecting the electrodes on the lead frame or TAB leads and the semiconductor element by plating.

[0002]

2. Description of the Related Art In mounting a semiconductor element, electrodes on the semiconductor element are connected to a lead frame or TAB (Tape Auto
As a method of connecting the leads of a mated tape, wire bonding is used to bridge the electrode and the lead using a thin metal wire such as Au or Al, or a TAB tape that connects the lead directly to the electrode bump provided on the element. Bonding and face-down bonding. In the former method, a physical load due to thermocompression bonding or ultrasonic vibration at the tip of the capillary is applied when joining fine metal wires,
Occasionally, these may affect the work or the characteristics of the semiconductor device, or if the distance between adjacent bridging thin wires is reduced, contact may occur between the fine wires, thereby restricting the installation interval. There is a problem that it becomes more difficult to respond to the demand for increasing the number of pins as the case may be. In the latter case, connection (pressure bonding) is performed at once with a large number of bumps provided on the electrode (or) lead. However, the bonding temperature is high, and the same problems as above remain. As the number of bumps increases, the connection becomes more stable. It will be difficult to do. On the other hand, bumps are usually made by plating high-purity Au on electrodes, and are heat-treated at approximately 250 to 300 ° C. in order to reduce hardness and improve pressure bonding with leads. The diffusion of Au and the electrode (Al) into Au-
In some cases, the Al interface is deteriorated, and in order to prevent the deterioration, a complicated means of interposing a diffusion preventing metal thin film such as TiW between both metals must be taken.

In order to solve the problems caused by using such a thin wire or applying heat, recently, a method of joining an electrode and a lead of a semiconductor element with a plating metal has been proposed. For example, in Japanese Patent Publication No. 57-50056,
It discloses that an electrode formed on a semiconductor element and an end of a lead wiring are arranged close to each other, and an electrode-lead gap is connected by plating. Also, JP-A-2-66953
In the publication, a circuit board having a base electrode on the surface and a semiconductor element having a protruding electrode on the surface face downward, a predetermined space is set between them, and a resin layer is adhered thereto, and the base electrode and the protruding electrode are bonded. 1 shows a mounting structure of a semiconductor element for connecting the semiconductor elements by a plating method.

[0004]

As described above, a technique for joining an electrode and a lead of a semiconductor element with a plating metal as described above is already known. However, in this type of conventional method, the electrode and the lead (or It is difficult to set all the intervals between the electrodes and the electrodes uniformly, so that the plating metal to be joined does not always adhere evenly, and the plating time must be lengthened to compensate for the lacking portion. That is, the amount of plating that adheres relatively increases, which limits the allowable spacing between adjacent leads, and is not suitable for mounting a semiconductor having a multi-pin structure. Even if the gap is set to be uniform, the plating metal initially adheres to the surface of the electrode and the lead surface, respectively, and gradually develops from both sides and joins (crosslinks). Therefore, it takes considerable time to fill the gap. In addition, the amount of adhesion from each surface is not always constant, and the same problem as described above is included.

SUMMARY OF THE INVENTION The present invention solves such a conventional problem. In plating and joining, a lead coated with an insulating material and having only a tip end surface exposed to a conductor is used. A uniform and stable mounting method of a multi-pin oriented semiconductor device capable of efficiently connecting with a minimum plating area and preventing a short circuit between leads and a semiconductor edge by directly contacting the semiconductor device with an electrode. The purpose is to do.

[0006]

Means for Solving the Problems In order to achieve the above object, the present invention has the following features. That is, after coating the lead portion of the lead frame or a TAB tape with an insulating material, by cutting the tip allowed exposing the lead conductors in the disconnected end face, close to or in contact with the electrodes of the lead exposed portion and the semiconductor element A method for mounting a semiconductor element, comprising fixing the semiconductor device in a state in which the lead is exposed and connecting the exposed electrode and the electrode by plating. As a result, the plating connection between the TAB tape or the lead of the lead frame and the electrode of the semiconductor element is performed on the end face and the electrode face, and an efficient connection can be achieved in a short time without excessive adhesion of the plating metal.

Hereinafter, the present invention will be described in detail. The lead of the present invention is a lead such as a TAB tape or a lead frame which is brought into direct contact with a semiconductor electrode. The lead surface is covered with a coating on the peripheral surface, but the lead conductor is exposed on the tip surface.
FIG. 1 is a schematic view showing an example of manufacturing a lead for the TAB tape of the present invention. As shown in FIG. 1 (a), a lead portion 1 is entirely coated with an insulating paint, a film or an insulating inorganic material as shown in FIG. (Hereinafter referred to as insulation coating), the tip 3 of the insulation coating lead 1 is cut as shown in FIG. 3 (b), and the lead conductor 1 is exposed on the cut end surface 4. Further, as shown in FIG. 3 (c), the coating 2 of the cut end portion 3 of the lead shown in FIG. 2 (b) may be removed with a solvent or the like, or the lead portion may be exposed without coating the tip portion 3. good.

The lead of the TAB tape formed in this manner is arranged at the position of the electrode 6 provided on the semiconductor element 5, and comes close to or in contact with the surface of the electrode 6 as shown in FIG. in and fixed allowed, either immersed in this state in the plating bath, by placing in the injection plating solution, the exposed conductors and the electrode surface of the lead end surface 4 as shown in the Figure 2 to connect with the plating metal.

FIG. 3 is a schematic view showing another example of manufacturing the lead of the present invention for a TAB tape. FIG. 3 (a) shows the lead 1 placed on an organic resist film 8 such as polyimide. The via hole 9 is formed by removing the film 8 at the tip portion 3, and the lead 1 surface is exposed 10 in the hole. Next, as shown in FIG. 2B, the lead 1 is cut over the end face portion of the hole 9 at the tip portion 3 to expose the lead end face 4 and the lead face 10 in the via hole. Thereafter, the exposed lead tip 3 is arranged at a position on the semiconductor element electrode 6, and is brought into close proximity to or in contact with the surface of the electrode 6 and fixed using the jig 11 shown in FIG. By immersing it in a plating bath or placing it in a spray plating solution in this state, a plating metal 7 is attached to the exposed conductor of the lead end face 4 and attached to the electrode surface as shown in FIG. At this time, the lead 1 and the semiconductor element 5 are close to each other, but since the insulating film 8 to which the lead 1 is attached is interposed between the two, no short circuit will occur even if they contact each other. An exposed surface other than the tip portions (4, 10) of the leads is coated with an oxide film or a plating resist coating.

The formation of the lead end face of the present invention is preferably performed by cutting. However, the present invention is not limited to this. For example, the insulator may be removed with a solvent. Further, even if bumps are provided on the electrodes, no particular trouble occurs.

As the metal to be plated, the same material as the lead or another conductive material, for example, Cu, Ni, Au, Sn, an alloy thereof, or solder can be used. And

[0012]

Embodiment 1 FIG. 2 shows a state in which the tip of an inner lead of a TAB tape and an electrode of a semiconductor chip are connected by plating. The TAB tape has a copper wire provided on a resin sheet such as polyimide. A plating joint is formed between the lead tip and the electrode, and both are electrically connected.

A method of connecting the inner leads of the TAB tape and the electrodes of the semiconductor chip by copper plating in the above semiconductor device will be described.

As the TAB tape, a two-layer TAB having a lead width of 70 μm, a lead thickness of 35 μm, a pitch of 140 μm, and 200 leads was used. Semiconductor chips are
200 electrodes of 80 μm × 80 μm are arranged on a chip of 8.0 mm × 8.0 mm, and the structure of the electrodes is A
1 was 1 μm, the intermediate TiW alloy layer was 2,000 Å, and the upper layer was 3,000 Å of gold by sputtering.

First, a copper lead portion of a TAB tape is coated with an insulating paint to a thickness of several μm (FIG. 1A). The material to be coated is, for example, an oil-based paint, but any material may be used as long as the material maintains insulation in the plating solution. After cutting the tip of the inner lead after coating with the insulating paint (FIG. 1B), or removing the coating of the tip from the tip by about 100 to 200 μm with an organic solvent or the like,
Or about 100-200μ
By covering the insulating lead [FIG. 1 (c)], the copper metal portion is exposed only at the tip of the inner lead.
And the tip of the lead of the TAB tape and the electrode of the semiconductor chip are arranged so as to approach or contact each other,
Fix as shown in FIG.

Next, connection plating between the tip of the lead and the electrode of the semiconductor chip is performed. The plating was performed using CuSO ₄ (0.
8 mol / l) and an aqueous solution of H ₂ SO ₄ (0.5 mol / l), the plating current density was 100 A / m ² , and the plating time was 30 to 50 minutes. After plating bonding, the plate was washed with water to remove the adhering plating solution, and the insulating coating at the time of plating was removed with an organic solvent or the like.

As for the bonding strength, the lead was pulled up at a position 200 μm away from the bonding portion, and the load at break was measured (pull test). The average pull strength is 40 g (minimum 35
g, up to 46 g) and that all were electrically connected.

[0018]

As described above, according to the present invention, the lead conductor is exposed only at the tip of the lead, the tip is brought into contact with the electrode, and the plating area is minimized. In addition, it is possible to provide a highly reliable semiconductor device suitable for multi-pins, which can prevent contact between leads and edge short-circuit of a semiconductor element.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are schematic views showing an example of molding a lead of the present invention.

FIG. 2 is a schematic view showing an example of a semiconductor element mounting method of the present invention using the leads of FIG. 1;

FIGS. 3A and 3B are schematic views showing another example of molding the lead of the present invention.

FIG. 4 is a schematic view showing an example of a semiconductor element mounting method of the present invention using the leads of FIG. 3;

FIG. 5 is a schematic view showing a jig used for plating bonding according to the present invention.

[Explanation of symbols]

 1: Lead 2: Insulating coating 3: Lead tip 4: Lead end face 5: Semiconductor element 6: Electrode 7: Plating metal 8: Insulating film 9: Via hole 10: Lead exposed surface 11: Jig

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yasuhide Ohno 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Nippon Steel Corporation Advanced Technology Research Laboratories (72) Inventor Takao Fujitsu, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 In the Tamagawa Plant, Toshiba Corporation (72) Yoshimasa Kudo Inventor Yoshimasa Kudo No. 1 in Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture (72) Inventor Shinya Shinya Shinya Shimizu Toshiba Komukai, Saiwai-ku, Kawasaki City, Kanagawa Prefecture No. 1, Toshiba Corporation Tamagawa Plant (56) References JP-A-5-102253 (JP, A) JP-B-58-45181 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB) Name) H01L 23/50 H01L 21/60 H05K 1/18 H05K 3/32

Claims (1)

(57) [Claims] 1. A after coating the lead portion of the lead frame or a TAB tape with an insulating material, by cutting the tip allowed exposing the lead conductors in the disconnected end face, the electrode of the lead exposed portion and the semiconductor element A method for mounting a semiconductor element, comprising: fixing a lead exposed portion and the electrode by plating in proximity or in contact with each other.