JP2777345B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrical connection between an electrode on a semiconductor chip and an inner lead, and an electrical connection between an outer lead and a wiring pattern on a printed wiring board. In particular, the present invention relates to a semiconductor device in which wiring intervals for electrical connection are minute.

[0002]

2. Description of the Related Art When a semiconductor device is manufactured, electrical connection is established between electrode pads on a semiconductor chip and inner leads, between outer leads and a wiring pattern on a printed wiring board, and the like. There are many places. Conventionally, for example, electrical connection between an electrode pad on a semiconductor chip and an inner lead is usually performed by A
Metal bonding using u wire or Al wire, TAB
This is performed by metal bonding using a tape (Tape Automate Bonding), ohmic contact by metal-metal bonding between a bump electrode such as a flip chip, and a lead, or the like.

[0003]

In the connection by wire bonding, the shortest distance between adjacent wires is restricted by the outer shape of a bonding capillary (needle) to be used.
It is difficult to reduce the size to about 0 μm or less. In addition, it is necessary to apply a physical load such as heating, pressurization, ultrasonic vibration, and the like to the metal connection between the Au ball or the Al wire and the aluminum pad on the semiconductor chip. May damage itself.

On the other hand, when a TAB tape or a flip chip is used, the metal connection between the Au bump and the solder bump and the inner lead is performed, and the temperature may be higher than that of the wire bonding connection. May leave physical damage. In this case, the pad spacing can be reduced to about 80 μm, but there is a limit in reducing the bump size due to metal bonding. In addition, since connection at a large number of locations is performed at once, as the number of connection locations such as bump height and connection conditions increases, it becomes more difficult to obtain connection stability, and it is necessary to stabilize process conditions.

[0005] The above-mentioned problem is caused not only by the electrical connection between the pads or bumps on the semiconductor chip and the inner leads, but also by the electrical connection between the outer leads and the wiring pattern on the printed wiring board. It can also occur in cases such as

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to reduce the distance between portions to be electrically connected to each other as compared with the prior art and to reduce the electrical connection. It is an object of the present invention to provide a semiconductor device having high reliability without causing physical damage such as heating and pressurization.

[0007]

According to the present invention, there is provided a semiconductor device comprising: a plurality of leads made of a conductive material, each having a tip; and a semiconductor chip having electrodes formed on a surface thereof.
The semiconductor device is characterized in that a metal plating connection portion is provided for electrically connecting the end surfaces of the tips of the plurality of leads to the electrodes of the semiconductor chip without using physical pressure or heat.

Further, according to the semiconductor device of the present invention, there is provided a semiconductor chip having electrodes formed on the surface, and a T chip having a plurality of leads formed on an insulating film so as to have respective tips.
AB tape, an adhesive for adhering the TAB tape to the semiconductor chip, and electrically connecting each tip of the plurality of leads and each electrode of the semiconductor chip without using any physical pressure or heat. And a connection portion formed by metal plating for connection.

Further, the semiconductor device of the present invention has a semiconductor chip having an electrode formed on a surface thereof, a first tip and a second tip opposite to the first tip, respectively. A TAB tape in which a plurality of leads are formed on an insulating film, wherein a plurality of leads are disposed so that one end corresponds to each electrode of the semiconductor chip, and an adhesive for attaching the TAB tape to the semiconductor chip. A first connection portion formed by metal plating for electrically connecting each first end portion of the plurality of leads and each electrode of the semiconductor chip without using physical pressure or heat; Metal plating for electrically connecting the wiring board on which the wiring pattern is formed, the second end portions of the plurality of leads, and the wiring patterns of the wiring board without using any physical pressure or heat. Second contact Characterized by comprising a part.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a connection between a lead and an electrode of a semiconductor chip, or a lead and a wiring pattern of a wiring board, which need to be electrically connected to each other, is made of metal plating or a conductive adhesive. And metal plating, it is possible to form a sufficient ohmic contact between each connection and to provide a sufficient mechanical strength. Moreover, a plurality of locations can be connected collectively, and heating and pressurizing are not required at the time of connection.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a partial configuration of a semiconductor device according to a first embodiment of the present invention in which the present invention is applied to connection between an electrode pad on a semiconductor chip and an inner lead, and FIG. FIG. 2 is a cross-sectional view showing a substantially entire configuration.

In FIG. 1, reference numeral 11 denotes a semiconductor chip on which active elements such as transistors and passive elements such as resistors and capacitors are formed. A plurality of electrodes each having a lower layer formed of a metal layer 12 made of, for example, aluminum (Al) and an upper layer formed of a metal layer 13 including at least one nickel layer all around the main surface of the semiconductor chip 11. Pads 14 are arranged in a line at regular intervals. Then, except for the positions where the electrode pads 14 are formed, the semiconductor chip 11
Is covered with an insulating surface protective film 15 such as a silicon oxide film. Further, the semiconductor chip 11 is adhered to a predetermined portion of a TAB tape 17 with an epoxy adhesive 16.

As shown in FIG. 1, the TAB tape 17 is made of a resin such as an epoxy resin or a polyimide resin and has a thickness of, for example, about 75 μm on an organic film substrate 18 having a thickness of, for example, about 35 μm. Then, a wiring pattern including a plurality of inner leads 19 to be connected to the plurality of electrode pads 14 and an outer lead (not shown) connected to each of the inner leads 19 is selectively formed by a selective etching technique. It is constituted by forming. The surface on which the wiring pattern is formed is adhered to the semiconductor chip 11 by the adhesive 16.

Also, the TAB tape 17 is provided with a semiconductor chip.
When attaching 11, the positioning is performed in such a state that the electrode pads 14 are located near the end surfaces of the tip portions of the plurality of inner leads 19 exposed. And
Each electrode pad 14 and inner lead 19 on the semiconductor chip 11
And each distal end surface of the, for example, are electrically connected via a metal plating layer 20 made of nickel (Ni).

FIG. 3 is a sectional view showing the detailed structure of each of the electrode pads 14. As shown in FIG. The metal layer 13 formed on the metal layer 12 made of aluminum (Al) is composed of at least two metal layers. That is, the lower layer in contact with the metal layer 12 made of aluminum is made of, for example, a titanium (Ti) layer 31 having a thickness of 1000 angstroms, and the upper layer is made of, for example, a nickel (Ni) layer 32 having a thickness of 3000 angstroms. Here, the upper nickel layer 32 is provided to enable formation of the metal plating layer 20 made of nickel on the electrode pad 14, and the lower titanium layer 31 has a role of a barrier metal. .

FIG. 4 shows the plurality of electrode pads 14 and TAB
FIG. 4 is a plan view showing a connection state with a plurality of inner leads 19 formed on a tape 17, in which a hatched area indicates a metal plating layer 20.

According to the above embodiment, the semiconductor chip 11
Since the upper electrode pads 14 and the inner leads 17 are connected using the metal plating layer 20, there is no need to use a bonding capillary and a TAB tool jig used for wire bonding, TAB connection, and the like. Become. Therefore, the interval between the electrode pads 14 can be reduced to 100 μm or less, for example, to about 50 μm. Further, when the electrode pads 14 and the inner leads 17 are electrically connected, no physical pressure is applied to the semiconductor chip 11, so that the reliability is not reduced due to the damage of the pressure. And since many connection parts can be performed collectively and on the same conditions, the reliability of connection improves. Further, since it is not necessary to heat the semiconductor chip 11 at the time of connection, it is possible to prevent a decrease in reliability due to a thermal stress caused by a mismatch between the thermal expansion coefficients of the layers constituting the semiconductor chip 11.

Since the TAB tape 17 and the semiconductor chip 11 are fixed by the adhesive 16, the metal plating layer
Even if the strength of the connection part cannot be ensured sufficiently by 20, the metal plating layer 20 will not be broken.

The formation of a metal plating layer for electrically connecting the above-mentioned electrode pads and inner leads is performed as follows. That is, as shown by the TAB tape in FIG. 5, after laminating a conductive layer such as copper on the organic film base material 18, the inner lead and the outer lead connected to the inner lead are formed by a selective etching technique. A plurality of lead electrodes 41 are formed for each semiconductor device. At this time, at the same time, a common electrode 42 for connecting the whole of the plurality of lead electrodes 41 is formed around each semiconductor device, and all the common electrodes 42 are also connected in common. In FIG. 5, reference numeral 43 denotes the organic film substrate 18
It is an opening formed in the hole.

FIG. 6 shows one example of the TAB tape shown in FIG.
FIG. 4 is an enlarged plan view showing a portion of one semiconductor device. In FIG. 6, the semiconductor chip 11 is adhered to a TAB tape in a state where the semiconductor chip 11 is positioned so as to be located in a region indicated by a chain line. At this time, as described above, each electrode pad on the semiconductor chip is located near the end face of each of the tips of the plurality of inner leads.

Thereafter, the TAB tape is immersed in a nickel plating bath together with the plating electrodes. The nickel plating bath is generally called a Watt bath, and includes a bath composed of nickel sulfate, nickel chloride, an additive and the like. After immersing both in the watt bath, a predetermined DC voltage is applied between the two so that the common electrode 42 has a positive polarity and the plating electrode has a negative polarity, and electroplating is performed for a predetermined time. For example, the applied DC voltage is 2 V, and the current flowing between them is 60 V.
When the plating time was set at 10 mA, the nickel plating layer having a thickness of 10 μm was obtained as the metal plating layer 20. The nickel plating layer initially grows from each end face of the tip of the inner lead. When this comes into contact with the electrode pad on the chip, a plating layer grows on the electrode pad thereafter, and finally both are electrically connected by the plating layer. After the plating, the substrate is washed with pure water to remove contaminants attached to the surface during plating.

In addition, most of the surface of each of the lead electrodes 41 including the inner lead and the outer lead except for the tip of the inner lead is coated with, for example, an epoxy insulating film called a green coat. Thereby, a plating layer can be formed only on a necessary portion, and the plating time can be reduced.

Next, another embodiment will be described. In the first embodiment, the case where the electrode pads are arranged in a line at a constant interval on the main surface of the semiconductor chip has been described. However, the semiconductor device according to the second embodiment shown in FIG. The present invention is an embodiment in which the electrode pads 14 on a semiconductor chip are arranged in a staggered manner. Note that the same reference numerals are given to the portions corresponding to FIG. 4 and the description is omitted. In the semiconductor device according to the third embodiment shown in FIG. 8, the present invention is based on a so-called free access pad layout system in which electrode pads on a semiconductor chip are randomly arranged on the entire surface of the chip. It was implemented in. Thus, the present invention can be implemented in any system regardless of the arrangement of the electrode pads on the chip.

FIG. 9 is a sectional view of a semiconductor device according to the fourth embodiment. In this semiconductor device, connection between outer leads of a lead frame and a wiring pattern on a printed wiring board is made by plating. In the figure, reference numeral 11 denotes a semiconductor chip, and 17 denotes a TAB tape. In this semiconductor device, the tip of the inner lead of the TAB tape and the electrode pad on the semiconductor chip 11 are electrically connected by the metal plating layer 20 as in the above-described embodiments. Further, in this semiconductor device, a wiring pattern 52 formed on a printed wiring board 51 is provided.
And the outer leads of the TAB tape are also electrically connected by the metal plating layer 20.

As described above, the present invention can be applied not only to the connection between the inner lead of the lead frame and the electrode pad on the semiconductor chip, but also to the connection between the outer lead and the wiring pattern on the printed wiring board. The same effect can be obtained respectively. Further, the present invention can be applied to an electrical connection between the liquid crystal display device and the TAB tape.

The present invention is not limited to the above embodiments, and it goes without saying that various other modifications are possible. For example, in each of the above embodiments, the case where the metal plating layer is a nickel plating layer has been described, but a gold (Au) plating layer, a copper plating layer, or the like can also be used.

Further, in the above-described embodiment, a case has been described in which an insulating coating is applied to most of the surface of the inner lead excluding the tip portion. However, when performing the electroplating, the plating layer grows only to a thickness of about 1/10 or less of the tip of the inner lead at a portion other than the tip of the inner lead, so that the application of the insulating coating as described above is omitted. You can also. Further, in the above embodiment, the case where the plating layer is formed by the electroplating method has been described, but this may be formed by the electroless plating method.

[0028]

As described above, according to the present invention,
Provided is a semiconductor device which can reduce the interval between portions to be electrically connected to each other as compared with the conventional case and has high reliability without causing physical damage such as heating and pressurization when making an electrical connection. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a partial configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a substantially entire configuration of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view showing a detailed configuration of each electrode pad in FIG. 1;

4 is a plan view showing a connection state between a plurality of electrode pads in FIG. 1 and a plurality of inner leads formed on a TAB tape.

FIG. 5 is a plan view showing a TAB tape used in FIG. 1;

FIG. 6 is an enlarged plan view showing a portion of one semiconductor device of the TAB tape of FIG. 5;

FIG. 7 is a plan view of a semiconductor device according to a second embodiment.

FIG. 8 is a plan view of a semiconductor device according to a third embodiment.

FIG. 9 is a sectional view of a semiconductor device according to a fourth embodiment.

[Explanation of symbols]

 11: Semiconductor chip, 12, 13, Metal layer, 14: Electrode pad, 15: Insulating surface protective film, 16: Epoxy adhesive, 17: TAB tape, 18: Organic film substrate, 19: Inner lead , 20 ... metal plating layer.

Claims (8)

(57) [Claims] A plurality of leads made of a conductive material and each having a tip, a semiconductor chip having an electrode formed on a surface thereof, and a tip end face of each of the plurality of leads and each electrode of the semiconductor chip. A semiconductor device comprising: a metal plating connection portion that is electrically connected without using any of physical pressure and heat. 2. The semiconductor device according to claim 1, wherein a plurality of leads are attached to said semiconductor chip with an adhesive. 3. The semiconductor device according to claim 1, wherein said leads are of a TAB type formed on an insulating film. 4. A semiconductor chip having electrodes formed on a surface thereof, a TAB tape having a plurality of leads formed on an insulating film so as to have respective tips, and an adhesive for attaching the TAB tape to the semiconductor chip. And a connection portion formed by metal plating for electrically connecting each end of the plurality of leads and each electrode of the semiconductor chip without using any physical pressure or heat. Semiconductor device. 5. A semiconductor chip having an electrode formed on a surface thereof, a first tip end and a second tip end opposite to the first tip end. A plurality of leads arranged on each of the semiconductor chips in proximity to each electrode, a plurality of leads formed on an insulating film, a TAB tape, an adhesive for attaching the TAB tape to the semiconductor chip, and each of the plurality of leads A first connection portion formed by metal plating for electrically connecting the first tip portion and each electrode of the semiconductor chip without using physical pressure and heat, and a plurality of wiring patterns are formed on the surface thereof. A wiring board, and a second connection portion formed by metal plating for electrically connecting each second end portion of the plurality of leads and each wiring pattern of the wiring board without using physical pressure or heat. Characterized by having Semiconductor device. 6. An electrode formed on a surface of the semiconductor chip, comprising: an aluminum layer; a titanium layer formed on the aluminum layer; and a gold layer, a nickel layer, or a copper layer formed on the titanium layer. The semiconductor device according to claim 1, wherein the semiconductor device includes one of the layers. 7. The semiconductor device according to claim 4, wherein the adhesive adheres the lead to the semiconductor chip. 8. The semiconductor device according to claim 4, wherein the adhesive bonds the insulating film to the semiconductor chip.