JPH0745664A - Mounting method for semiconductor device - Google Patents

Mounting method for semiconductor device

Info

Publication number
JPH0745664A
JPH0745664A JP18594493A JP18594493A JPH0745664A JP H0745664 A JPH0745664 A JP H0745664A JP 18594493 A JP18594493 A JP 18594493A JP 18594493 A JP18594493 A JP 18594493A JP H0745664 A JPH0745664 A JP H0745664A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
solder
electrodes
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18594493A
Other languages
Japanese (ja)
Inventor
Yoshihisa Totsuta
義久 土津田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18594493A priority Critical patent/JPH0745664A/en
Publication of JPH0745664A publication Critical patent/JPH0745664A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PURPOSE:To eliminate the need of forming projecting electrodes in a semiconductor device and, at the same time, to reduce the number of manufacturing processes of the device by removing oxide films from the surfaces of electrodes by performing reverse sputtering and depositing metallic films on the surfaces of the electrodes. CONSTITUTION:Individually and separately fed multiple semiconductor devices 1 are simultaneously put in the chamber of a sputtering device and oxide films formed on Al electrodes are selectively removed by reverse sputtering. After removing the oxide films, metallic films 3 and second metallic films 4 are separately sputtered. Then solder paste 6 is supplied to the surfaces of circuit boards coated with a solder resist 8 and balls 10 coated with an easily solderable metal 9 are arranged on the printed solder paste 6. Thereafter, the solder is melted by counterposing the device 1 to the board 5 and heating the balls 10 while the electrodes 2 of the device 1 are pressed against the balls 10 arranged on the connection pads of the board 5. Then the circuit board 5 is dipped in an etchant so as to selectively remove the second metallic films 4 composed of CuNi.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の接続技
術、特に半導体装置を回路基板にフェイスダウン接続す
る技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device connection technique, and more particularly to a technique for face-down connection of a semiconductor device to a circuit board.

【0002】[0002]

【従来の技術】従来のフェイスダウン接続法について説
明する。
2. Description of the Related Art A conventional face-down connection method will be described.

【0003】従来、半導体装置を回路基板上にフェイス
ダウン接続する際には、予め、半導体装置の電極上に突
起電極を形成する必要があった。半導体装置を自社で製
造しているメーカやウェハ状態で入手することが可能な
半導体装置であれば、ウェハ状態でメッキにより突起電
極を形成する方法が知られている。図4(a)に示すよ
うに、まず、逆スパッタにより半導体装置11の電極1
4上の酸化膜からなる絶縁保護膜21を除去し、続いて
半導体装置11上に金属薄膜12をスパッタにより積層
する。次に前記金属薄膜12上にレジスト13を塗布
し、電極14上部の突起電極を形成する部分のみフォト
リソグラフィ法により開口する。次いで、金属薄膜12
を陰極とし、電解メッキ法によりメッキ金属15を形成
する。続いてレジスト13を除去し、不要な金属薄膜1
2をメッキ金属15をマスクとしてエッチング除去する
ことにより、金属薄膜12、メッキ金属15からなる突
起電極を形成することができる(図4(b))。
Conventionally, when face-down connecting a semiconductor device to a circuit board, it was necessary to previously form protruding electrodes on the electrodes of the semiconductor device. A method of forming a protruding electrode by plating in a wafer state is known as long as it is a semiconductor device manufactured by the manufacturer or a semiconductor device that can be obtained in a wafer state. As shown in FIG. 4A, first, the electrode 1 of the semiconductor device 11 is formed by reverse sputtering.
The insulating protective film 21 made of an oxide film on 4 is removed, and then the metal thin film 12 is laminated on the semiconductor device 11 by sputtering. Next, a resist 13 is applied on the metal thin film 12, and only the portion of the electrode 14 above which the protruding electrode is to be formed is opened by photolithography. Then, the metal thin film 12
Is used as a cathode, and the plated metal 15 is formed by electrolytic plating. Then, the resist 13 is removed to remove the unnecessary metal thin film 1.
By removing 2 by etching using the plated metal 15 as a mask, a protruding electrode composed of the metal thin film 12 and the plated metal 15 can be formed (FIG. 4B).

【0004】この時、金属15が半田の場合は、半田を
溶融することにより、半田の表面張力で図4(c)の如
く、半球状の突起電極を得ることができる。
At this time, when the metal 15 is solder, by melting the solder, it is possible to obtain a hemispherical protruding electrode by the surface tension of the solder as shown in FIG. 4 (c).

【0005】また、図5に示すように、逆スパッタによ
り、半導体装置11の電極14上の酸化膜21を除去
し、次にメタルマスク16を用いて電極14上に金属薄
膜12を蒸着し、続いて半田を構成する金属17a,b
を順次蒸着する。最後に金属17a,bを溶融し、図4
(c)のような半球状の突起電極を得る。
Further, as shown in FIG. 5, the oxide film 21 on the electrode 14 of the semiconductor device 11 is removed by reverse sputtering, and then the metal thin film 12 is vapor-deposited on the electrode 14 by using the metal mask 16. Subsequently, the metals 17a and 17b forming the solder
Are sequentially deposited. Finally, the metals 17a and 17b are melted,
A hemispherical protruding electrode as shown in (c) is obtained.

【0006】上述のような方法により突起電極を形成し
た後、ダイシングにより半導体装置を個別に分割する。
After the protruding electrodes are formed by the method as described above, the semiconductor devices are individually divided by dicing.

【0007】一方、他社から納入される、予め個別に分
割された半導体装置11の電極14上には図6に示すよ
うに、金属細線を用いてワイヤボンディング技術を応用
したボールボンディング法により突起電極を形成する方
法が知られている。キャピラリ19で供給、支持される
金属細線18を溶融して金属ボール20を形成し、半導
体装置11の電極14に加圧すると共に、加熱あるいは
超音波を印加、または両者を併用するなどし、半導体装
置11の電極14上の酸化膜を破壊して金属ボール20
を接続し、この後、金属細線を切断して突起電極を形成
する。
On the other hand, as shown in FIG. 6, on the electrode 14 of the semiconductor device 11 which is delivered from another company and which has been previously divided into individual parts, a protruding electrode is formed by a ball bonding method applying a wire bonding technique using a fine metal wire. There is known a method of forming the. The thin metal wire 18 supplied and supported by the capillary 19 is melted to form a metal ball 20, which is pressed against the electrode 14 of the semiconductor device 11 and is heated or applied with ultrasonic waves, or both are used together. 11 destroys the oxide film on the electrode 14 of the metal ball 20.
After that, the thin metal wire is cut to form a protruding electrode.

【0008】このように突起電極を形成した後、半導体
装置を個別に分割し、予め分割された半導体装置に突起
電極を形成して、ひき続きフェイスダウン接続方法を用
いて回路基板に接続する。
After forming the bump electrodes in this way, the semiconductor device is individually divided, the bump electrodes are formed on the previously divided semiconductor devices, and subsequently, they are connected to the circuit board by using the face-down connection method.

【0009】前記突起電極がAuの場合、突起電極にA
g−Pdを含む導電性ペーストを転写し、回路基板の接
続パッド上に位置合せし押し当て、その後前記導電性ペ
ースト加熱硬化することにより接続を行う方法が知られ
ている。
When the protruding electrode is Au, the protruding electrode is
A method is known in which a conductive paste containing g-Pd is transferred, aligned and pressed onto a connection pad of a circuit board, and then the conductive paste is heat-cured to make a connection.

【0010】また、突起電極が半田の場合、回路基板上
に予めフラックスを塗布して、回路基板の接続パッドと
前記突起電極とを位置合せし、押し当てる。次にこの状
態でリフロー炉を通すなどの方法により半田を溶融して
接続を行う方法が知られている。
When the protruding electrodes are solder, flux is applied on the circuit board in advance, the connection pads of the circuit board and the protruding electrodes are aligned and pressed. Next, a method is known in which the solder is melted and connected in this state by passing it through a reflow furnace.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、従来の
技術には次のような問題点があった。半導体装置をウェ
ハ状態で入手することは、半導体装置の製造メーカが自
社の半導体装置を用いる場合には可能であるが、他社の
半導体装置を購入する場合、通常個別に分割された状態
で納入され、ウェハ状態で入手することは不可能であ
る。個別に分割された半導体装置に電解メッキや蒸着法
により突起電極を形成するのは、コストが大幅に増加
し、効率が悪く現実的ではない。また、たとえ、ウェハ
状態で入手できたとしても、電解メッキ法により突起電
極を形成するプロセスは工程が多く複雑であり、半導体
装置のコストを大幅に増加させてしまう。
However, the conventional technique has the following problems. Obtaining semiconductor devices in the wafer state is possible when semiconductor device manufacturers use their own semiconductor devices, but when purchasing semiconductor devices of other companies, they are usually delivered separately. However, it is impossible to obtain it in a wafer state. It is not practical to form the protruding electrodes on the individually divided semiconductor devices by electrolytic plating or vapor deposition because the cost is significantly increased and the efficiency is poor. Further, even if it is available in a wafer state, the process of forming the protruding electrode by the electrolytic plating method has many steps and is complicated, and the cost of the semiconductor device is significantly increased.

【0012】一方、個別に分割された半導体装置にボー
ルボンディング法により突起電極を形成する場合、電極
数が増加するに従い、突起電極の形成時間が大幅に伸
び、歩留りも低下する。また、突起電極の高さのばらつ
きも大きいため、フェイスダウン接続の際に接続不良を
生じ易く、信頼性が劣るなど問題も多い。更に、半導体
装置の電極として多く用いられるAl上には、広く一般
的に用いられるSn/Pb半田をボールボンディング法
で形成することができない。上述のような理由から、個
別に分割されて入手した半導体装置に安価に且つ容易に
突起電極を形成することは困難である。
On the other hand, when the protruding electrodes are formed on the individually divided semiconductor devices by the ball bonding method, as the number of electrodes increases, the forming time of the protruding electrodes significantly increases and the yield also decreases. Further, since there is a large variation in the height of the protruding electrodes, there are many problems such as poor connection during face-down connection and poor reliability. Furthermore, Sn / Pb solder, which is widely and commonly used, cannot be formed on Al, which is often used as an electrode of a semiconductor device, by a ball bonding method. For the reasons described above, it is difficult to easily and inexpensively form the protruding electrodes on the semiconductor devices obtained by dividing the semiconductor devices individually.

【0013】以上のようなことから、半導体装置に突起
電極を形成することは、半導体装置をフェイスダウン接
続して構成される回路モジュールのコストアップを招
き、問題となっている。
As described above, forming the protruding electrodes on the semiconductor device causes a problem in that the cost of the circuit module formed by connecting the semiconductor devices face down is increased.

【0014】[0014]

【課題を解決するための手段】本発明は上述する課題を
解決するためになされたもので、回路基板上に半導体装
置を実装させる方法において、半導体装置の電極を露出
させる工程と、前記半導体装置の電極露出面側に金属膜
を形成する工程と、回路基板の接続パッド上に半田ペー
ストを供給する工程と、前記回路基板の半田ペースト上
に親半田性の金属に覆われた球を配置する工程と、前記
金属膜を形成した半導体装置と、前記球を配置した回路
基板とを位置合せした後、前記回路基板上の半田ペース
トを溶融加熱させて回路基板の接続パッドと半導体装置
の電極とを電気的に接続させる工程と、前記半導体装置
の金属膜の、半田ペースト非接着領域をエッチング除去
する工程と、からなる半導体装置の実装方法を提供する
ものである。
The present invention has been made to solve the above-mentioned problems, and in a method of mounting a semiconductor device on a circuit board, a step of exposing electrodes of the semiconductor device, and the semiconductor device. A step of forming a metal film on the electrode exposed surface side, a step of supplying a solder paste onto the connection pads of the circuit board, and a sphere covered with a solder-philic metal on the solder paste of the circuit board. After aligning the step, the semiconductor device on which the metal film is formed, and the circuit board on which the sphere is arranged, the solder paste on the circuit board is melted and heated to form the connection pads of the circuit board and the electrodes of the semiconductor device. And a step of electrically removing the solder paste non-adhesive region of the metal film of the semiconductor device, and a method of mounting the semiconductor device.

【0015】[0015]

【作用】このように、個別に分割された半導体装置であ
れば、一度に大量の半導体装置上に、また、ウェハ状態
の半導体装置であれば、ウェハ状態のままで、逆スパッ
タを行って電極上の酸化膜を除去し、引き続き、金属膜
を堆積することにより、半導体装置に突起電極を形成す
ることが不要となる。また、工程数を減ずることが可能
となる。
As described above, in the case of individually divided semiconductor devices, a large number of semiconductor devices are processed at one time, and in the case of a semiconductor device in a wafer state, reverse sputtering is performed while the wafer state is maintained. By removing the upper oxide film and subsequently depositing the metal film, it becomes unnecessary to form the protruding electrode on the semiconductor device. In addition, the number of steps can be reduced.

【0016】[0016]

【実施例】図1〜図3を用いて本発明の第1の実施例、
及び第2の実施例を説明する。
EXAMPLE A first example of the present invention will be described with reference to FIGS.
A second embodiment will be described.

【0017】(第1の実施例)個別に分割して納入され
た半導体装置1を多数個同時にスパッタ装置のチャンバ
内に入れて、まず逆スパッタを行い、半導体装置1に形
成された絶縁酸化膜21のうち、Al電極2表面に形成
された酸化膜を選択的に除去する。引き続き、Tiから
なる金属膜3、CuNiからなる第2の金属膜4を各々
0.1〜0.3μm程度スパッタする。この時、個別に
分割された半導体装置でなく、ウェハ状態の半導体装置
に同様の方法により、酸化膜の除去、金属膜の形成を行
い、その後、ダイシングにより個別に分割してもよい。
通常、半導体装置1のAl電極2表面には強固な酸化膜
21が形成されており、逆スパッタによる酸化膜の選択
的除去を行わずに金属膜を堆積すると、良好な導通を得
ることができない。また、第1の金属膜3としてTiを
用いたが、これは電極2と第2の金属膜(CuNi)4
との密着力を得るためのもので、この目的を達するもの
ならば、Tiに限られるものではなく、TiWを用いて
もよい。
(First Embodiment) A large number of semiconductor devices 1 delivered separately are placed in a chamber of a sputtering apparatus at the same time, and reverse sputtering is performed first to form an insulating oxide film formed on the semiconductor device 1. Of 21, the oxide film formed on the surface of the Al electrode 2 is selectively removed. Subsequently, the metal film 3 made of Ti and the second metal film 4 made of CuNi are sputtered by about 0.1 to 0.3 μm. At this time, the oxide film may be removed and the metal film may be formed on the semiconductor device in a wafer state by the same method, instead of the semiconductor device which is individually divided, and then the semiconductor device may be individually divided by dicing.
Normally, a strong oxide film 21 is formed on the surface of the Al electrode 2 of the semiconductor device 1, and good conductivity cannot be obtained if a metal film is deposited without selectively removing the oxide film by reverse sputtering. . Further, Ti is used as the first metal film 3, but this is used for the electrode 2 and the second metal film (CuNi) 4
In order to obtain an adhesion force with, and if it achieves this purpose, it is not limited to Ti and TiW may be used.

【0018】一方、半導体装置1を接続する回路基板5
の表面にはCuからなる配線材料7が形成され、半導体
装置接続領域である接続パッド部以外は、ほとんどソル
ダーレジスト8で覆われている。ソルダーレジスト8の
形成方法としては、必要な形状にスクリーン印刷する方
法や、更に精度を向上するには感光性のソルダーレジス
トを用いてホトリソグラフイ法により接続パッド部分の
みを開口させる方法もある。また、接続パッドの最表面
に、Auメッキ或いはNiメッキ+Auメッキを施すこ
とにより、後行程で半田を溶融する際に、半田の濡れ性
を向上することもできる。
On the other hand, the circuit board 5 for connecting the semiconductor device 1
A wiring material 7 made of Cu is formed on the surface of, and is almost covered with a solder resist 8 except for the connection pad portion which is a semiconductor device connection region. As a method of forming the solder resist 8, there is a method of screen printing in a required shape, or a method of using a photosensitive solder resist to open only the connection pad portion by a photolithography method to further improve accuracy. Further, by applying Au plating or Ni plating + Au plating to the outermost surface of the connection pad, the wettability of the solder can be improved when the solder is melted in the subsequent process.

【0019】次に、ソルダーレジスト8で覆れた回路基
板5上に、スクリーン印刷によりSn/Pb=60/4
0の共晶半田半田ペースト6を供給する。次いで、印刷
された半田ペースト6上に親半田性の金属9に被覆され
た球10を配置する。球の材質としては、Au,Cu,
Ni,Sn/Pbの高融点半田などの親半田性の金属を
単体で用いたり、金属、セラミック、或いは樹脂などの
表面に親半田金属をコーティングしたものを用いてもよ
い。ここではセラミック球にNiメッキ及びAuメッキ
を施した球を用いた。
Next, Sn / Pb = 60/4 is screen-printed on the circuit board 5 covered with the solder resist 8.
The eutectic solder solder paste 6 of 0 is supplied. Next, the sphere 10 covered with the solder-philic metal 9 is placed on the printed solder paste 6. The material of the sphere is Au, Cu,
A metal having a solder-philic property such as Ni, Sn / Pb high-melting-point solder may be used alone, or a metal, ceramic, or resin whose surface is coated with a solder-friendly metal may be used. Here, a sphere obtained by plating a ceramic sphere with Ni and Au was used.

【0020】図1に示すように、半導体装置1と回路基
板5を対向させ、半導体装置1の電極2と回路基板5の
接続パッド上に配置された球10とを位置合せし、両者
を押し当てる。この状態で半導体装置1及び/または回
路基板5を半田ペースト6の融点以上に加熱することに
より半田が溶融して、球10の表面、回路基板5の接続
パッド、及び半導体装置1の金属膜4に濡れ広がり、図
2の如く、半導体装置1と回路基板5は電気的、機械的
に接続される。このとき、球10により半導体装置1と
回路基板5は一定の距離を保持され、また、半田の表面
張力により、半田の濡れ広がり量が制限される。
As shown in FIG. 1, the semiconductor device 1 and the circuit board 5 are opposed to each other, the electrode 2 of the semiconductor device 1 and the sphere 10 arranged on the connection pad of the circuit board 5 are aligned, and both are pushed. Hit In this state, the semiconductor device 1 and / or the circuit board 5 is heated to a temperature equal to or higher than the melting point of the solder paste 6 to melt the solder, and the surface of the sphere 10, the connection pad of the circuit board 5, and the metal film 4 of the semiconductor device 1 are melted. As shown in FIG. 2, the semiconductor device 1 and the circuit board 5 are electrically and mechanically connected to each other. At this time, the sphere 10 holds the semiconductor device 1 and the circuit board 5 at a constant distance, and the surface tension of the solder limits the amount of spread of the solder.

【0021】続いて、半導体装置1が回路基板5に接続
された回路モジュールをCuNiのエッチング液に浸漬
し、CuNiからなる第2の金属膜4を選択的に除去す
る。エッチング液としては、ヤマト屋商会から販売され
ているアルカエッチ液(商品名)を水で5倍程度に薄め
たものや、硝酸を水で薄めたものなどがある。半導体装
置1の表面に形成されたCuNiからなる金属膜4は非
常に薄く、エッチング時間が短いこと、及び、接続部分
に形成されたCuとSnの合金層はこのエッチング液に
は溶解しにくいことから選択的に不要なCuNiのみ除
去することができる。次にTiからなる第1の金属膜3
を、EDTA、過酸化水素水、及びアンモニア水の混合
液により、選択的にエッチング除去する。こうして図3
の如く半導体装置1が実装された回路モジュールが得ら
れる。
Subsequently, the circuit module in which the semiconductor device 1 is connected to the circuit board 5 is dipped in an etching solution of CuNi to selectively remove the second metal film 4 made of CuNi. As the etching solution, there are a solution of Alka etch solution (trade name) sold by Yamatoya Shokai, diluted with water about 5 times, and a solution of nitric acid diluted with water. The metal film 4 made of CuNi formed on the surface of the semiconductor device 1 is very thin and the etching time is short, and the Cu-Sn alloy layer formed at the connection portion is difficult to dissolve in this etching solution. It is possible to selectively remove only unnecessary CuNi. Next, the first metal film 3 made of Ti
Are selectively removed by etching with a mixed solution of EDTA, hydrogen peroxide solution, and ammonia water. Thus, FIG.
As described above, a circuit module in which the semiconductor device 1 is mounted can be obtained.

【0022】(第2の実施例)個別に分割して納入され
た半導体装置1を多数個同時にスパッタ装置のチャンバ
内に入れて、まず、逆スパッタを行い、半導体装置1に
形成された絶縁酸化膜21のうち、Al電極2表面に形
成された酸化膜を選択的に除去する。引き続き、TiW
からなる第1の金属膜3、Cuからなる第2の金属膜4
を各々0.1〜1μm程度スパッタする。この時第1の
実施例と同様にウェハ状態の半導体装置を用いてもよ
い。
(Second Embodiment) A large number of semiconductor devices 1 separately delivered are placed in a chamber of a sputtering apparatus at the same time, and first, reverse sputtering is performed to perform insulation oxidation on the semiconductor device 1. Of the film 21, the oxide film formed on the surface of the Al electrode 2 is selectively removed. Continue to TiW
A first metal film 3 made of Cu and a second metal film 4 made of Cu
Is sputtered by about 0.1 to 1 μm. At this time, a semiconductor device in a wafer state may be used as in the first embodiment.

【0023】一方、半導体装置1を接続する回路基板5
の表面にはCuからなる配線材料7が形成され、半導体
装置接続領域である接続パッド部以外は、第1の実施例
と同様にソルダーレジスト8で覆われている。また、接
続パッドの最表面に、Auメッキを施すことにより、後
工程で半田を溶融する際に、半田の濡れ性を向上させる
こともできる。
On the other hand, the circuit board 5 for connecting the semiconductor device 1
A wiring material 7 made of Cu is formed on the surface of the substrate, and is covered with a solder resist 8 as in the first embodiment except the connection pad portion which is the semiconductor device connection region. Further, by applying Au plating to the outermost surface of the connection pad, the wettability of the solder can be improved when the solder is melted in a later step.

【0024】次に、ソルダーレジスト8で覆われた回路
基板5上にスクリーン印刷により、Sn/Pb=60/
40の共晶半田からなる半田ペースト6を供給する。次
いで、印刷された半田ペースト6上に親半田性の金属9
に被覆された球10を配置する。ここではNi球の表面
にAuメッキを施したものを用いた。
Next, Sn / Pb = 60 / by screen printing on the circuit board 5 covered with the solder resist 8.
A solder paste 6 of 40 eutectic solder is supplied. Next, the solder-friendly metal 9 is applied onto the printed solder paste 6.
The sphere 10 coated on the base is placed. Here, a Ni ball having a surface plated with Au was used.

【0025】図1に示すように半導体装置1と回路基板
5を対向させ、第1の実施例と同様のプロセスにより図
2の如く、半導体装置1と回路基板5とを電気的機械的
に接続する。
As shown in FIG. 1, the semiconductor device 1 and the circuit board 5 are opposed to each other, and the semiconductor device 1 and the circuit board 5 are electrically and mechanically connected as shown in FIG. 2 by the same process as in the first embodiment. To do.

【0026】続いて、半導体装置1が回路基板5に接続
された回路モジュールをCuのエッチング液に浸漬し、
Cuからなる第2の金属膜4を選択的に除去する。エッ
チング液としては、ヤマト屋商会から販売されているア
ルカエッチ液(商品名)を水で10倍程度に薄めたもの
や、硝酸を水で薄めたものがある。次にTiWからなる
第1の金属膜3を、EDTA、過酸化水素水、及びアン
モニア水の混合液により、選択的にエッチング除去す
る。こうして図3の如く、半導体装置1が実装された回
路モジュールが得られる。
Subsequently, the circuit module in which the semiconductor device 1 is connected to the circuit board 5 is immersed in a Cu etching solution,
The second metal film 4 made of Cu is selectively removed. As the etching solution, there are an alkaline etch solution (trade name) sold by Yamatoya Shokai, diluted with water about 10 times, and nitric acid diluted with water. Next, the first metal film 3 made of TiW is selectively removed by etching with a mixed solution of EDTA, hydrogen peroxide solution, and ammonia water. Thus, as shown in FIG. 3, a circuit module in which the semiconductor device 1 is mounted is obtained.

【0027】[0027]

【発明の効果】以上のように、本発明により、半導体装
置が個別に分割されているかウェハ状態であるかに係わ
りなく、半導体装置に突起電極を形成することが不要と
なり、大幅に工程数を減少させたフェイスダウン接続が
可能となるため、信頼性の高い回路モジュールを安価か
つ容易に得ることが可能となる。
As described above, according to the present invention, it becomes unnecessary to form the protruding electrode on the semiconductor device regardless of whether the semiconductor device is individually divided or in a wafer state, and the number of steps can be drastically reduced. Since reduced face-down connection is possible, a highly reliable circuit module can be obtained inexpensively and easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を説明するための要部断面図で
ある。
FIG. 1 is a sectional view of an essential part for explaining an embodiment of the present invention.

【図2】本発明の実施例を説明するための要部断面図で
ある。
FIG. 2 is a cross-sectional view of an essential part for explaining an embodiment of the present invention.

【図3】本発明の実施例を説明するための要部断面図で
ある。
FIG. 3 is a cross-sectional view of an essential part for explaining an embodiment of the present invention.

【図4】従来例を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional example.

【図5】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.

【図6】従来例を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体装置 2 Al電極 3 第1の金属膜 4 第2の金属膜 5 回路基板 6 半田ペースト 7 配線 8 ソルダーレジスト 9 親半田性金属 10 球 1 Semiconductor Device 2 Al Electrode 3 First Metal Film 4 Second Metal Film 5 Circuit Board 6 Solder Paste 7 Wiring 8 Solder Resist 9 Solder Resistant Metal 10 Ball

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 回路基板上に半導体装置を実装させる方
法において、 半導体装置の電極を露出させる工程と、 前記半導体装置の電極露出面側に金属膜を形成する工程
と、 回路基板の接続パッド上に半田ペーストを供給する工程
と、 前記回路基板の半田ペースト上に親半田性の金属に覆わ
れた球を配置する工程と、 前記金属膜を形成した半導体装置と、前記球を配置した
回路基板とを位置合わせした後、前記回路基板上の半田
ペーストを溶融加熱させて回路基板の接続パッドと半導
体装置の電極とを電気的に接続させる工程と、 前記半導体装置の金属膜の、半田ペースト非接着領域を
エッチング除去する工程と、 からなることを特徴とする半導体装置の実装方法。
1. A method of mounting a semiconductor device on a circuit board, the step of exposing electrodes of the semiconductor device, the step of forming a metal film on the electrode exposed surface side of the semiconductor device, and the step of connecting pads on the circuit board. A step of supplying a solder paste to the circuit board, a step of disposing a sphere covered with a solder-philic metal on the solder paste of the circuit board, a semiconductor device having the metal film formed thereon, and a circuit board having the sphere arranged thereon. After aligning and, the step of melting and heating the solder paste on the circuit board to electrically connect the connection pads of the circuit board and the electrodes of the semiconductor device, and the solder paste non-bonding of the metal film of the semiconductor device. A method for mounting a semiconductor device, comprising: a step of etching away an adhesion region.
JP18594493A 1993-07-28 1993-07-28 Mounting method for semiconductor device Pending JPH0745664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18594493A JPH0745664A (en) 1993-07-28 1993-07-28 Mounting method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18594493A JPH0745664A (en) 1993-07-28 1993-07-28 Mounting method for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0745664A true JPH0745664A (en) 1995-02-14

Family

ID=16179619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18594493A Pending JPH0745664A (en) 1993-07-28 1993-07-28 Mounting method for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0745664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038144B2 (en) 2000-11-08 2006-05-02 Sharp Kabushiki Kaisha Electronic component and method and structure for mounting semiconductor device
JP2007287712A (en) * 2006-04-12 2007-11-01 Oki Electric Ind Co Ltd Semiconductor device, packaging structure thereof, and manufacturing method of semiconductor device and packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038144B2 (en) 2000-11-08 2006-05-02 Sharp Kabushiki Kaisha Electronic component and method and structure for mounting semiconductor device
JP2007287712A (en) * 2006-04-12 2007-11-01 Oki Electric Ind Co Ltd Semiconductor device, packaging structure thereof, and manufacturing method of semiconductor device and packaging structure

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