JP2811741B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2811741B2 JP2811741B2 JP1106209A JP10620989A JP2811741B2 JP 2811741 B2 JP2811741 B2 JP 2811741B2 JP 1106209 A JP1106209 A JP 1106209A JP 10620989 A JP10620989 A JP 10620989A JP 2811741 B2 JP2811741 B2 JP 2811741B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- solder
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にバンプ電
極を有する半導体装置の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a bump electrode.
従来、バンプ電極を有する半導体装置のバンプ部には
金又は銅が用いられていた。最近になり、低温化,低コ
スト化が要求され、バンプ部の金属として半田(錫・鉛
系)が用いられ始めている。Conventionally, gold or copper has been used for a bump portion of a semiconductor device having a bump electrode. Recently, lower temperatures and lower costs have been required, and solder (tin / lead-based) has begun to be used as a metal for the bump portion.
第2図は従来の半導体装置を説明するための半導体チ
ップの断面図である。FIG. 2 is a sectional view of a semiconductor chip for explaining a conventional semiconductor device.
第2図に示すように、素子領域(図示せず)を有する
シリコン基板1の表面に酸化膜2を形成し、酸化膜2の
上に前記素子領域に接続したアルミニウム配線(図示せ
ず)と接続した外部回路接続用のアルミニウム電極3を
形成し、アルミニウム電極3を含む表面に絶縁膜4を堆
積し、アルミニウム電極3の上の絶縁膜4を選択的にエ
ッチングして開孔部を設ける。次に、開口部のアルミニ
ウム電極3の上にチタン,ニッケル,銅などのカップリ
ング用金属膜10を形成し、さらにその上に半田を付着さ
せて半田バンプ8を形成する。アルミニウム電極部3に
カップリング用金属膜10を形成する方法として真空蒸着
法や湿式めっき法があり、半田を付着させる方法として
は直接、溶融半田槽に浸漬させる方法、湿式めっき法が
行なわれている。As shown in FIG. 2, an oxide film 2 is formed on a surface of a silicon substrate 1 having an element region (not shown), and an aluminum wiring (not shown) connected to the element region is formed on the oxide film 2. An aluminum electrode 3 for connection to an external circuit is formed, an insulating film 4 is deposited on the surface including the aluminum electrode 3, and the insulating film 4 on the aluminum electrode 3 is selectively etched to form a hole. Next, a coupling metal film 10 of titanium, nickel, copper or the like is formed on the aluminum electrode 3 in the opening, and a solder is adhered thereon to form a solder bump 8. There are a vacuum deposition method and a wet plating method as a method of forming the coupling metal film 10 on the aluminum electrode portion 3, and a method of directly immersing in a molten solder bath and a wet plating method are used as a method of attaching solder. I have.
上述した従来の半導体装置は、カップリング用金属膜
を設ける方法が品質,価格の面でネックポイントになっ
ている。In the conventional semiconductor device described above, a method of providing a coupling metal film is a bottleneck in terms of quality and price.
例えば湿式めっきではその前処理としてアルミニウム
薄膜表面の酸化膜除去を行なわなければならず、処理条
件の制御が困難である。そのため、酸化膜のエッチング
過度によるカップリング用金属の不完全めっきを引き起
こす。一方酸化膜エッチング不足の場合はカップリング
用金属の密着不良につながる。いずれの場合も、カップ
リング用金属上に設けた半田バンプの強度不良となり、
品質が非常に不安定である。For example, in wet plating, it is necessary to remove an oxide film from the surface of the aluminum thin film as a pretreatment, and it is difficult to control the processing conditions. This causes incomplete plating of the coupling metal due to excessive etching of the oxide film. On the other hand, insufficient etching of the oxide film leads to poor adhesion of the coupling metal. In either case, the strength of the solder bumps provided on the coupling metal becomes poor,
Quality is very unstable.
また、真空蒸着法でカップリング用金属膜を設けるた
めには、数回のリソグラフィー工程と真空処理が必要で
あるため、非常に効果な半田バンプ素子となってしま
う。Further, in order to provide a coupling metal film by a vacuum deposition method, several lithography steps and a vacuum treatment are required, which results in a very effective solder bump element.
本発明の半導体装置の製造方法は、素子領域を有する
半導体基板の上に第1の絶縁膜を設け前記第1の絶縁膜
上に前記素子領域に接続する配線を設ける工程と、前記
配線を含む前記半導体基板全面に第2の絶縁膜を設けた
後該第2の絶縁膜を選択的にエッチングし、前記配線上
の該第2の絶縁膜に開口部を設ける工程と、前記開口部
の前記配線上に印刷法により直接に金,銀等の貴金属を
含有してなる導電性樹脂膜を形成する工程と、前記導電
性樹脂膜の上に半田を溶着して半田バンプを形成する工
程とを含んで構成される。The method of manufacturing a semiconductor device according to the present invention includes the steps of: providing a first insulating film on a semiconductor substrate having an element region, and providing a wiring connected to the element region on the first insulating film; Providing a second insulating film over the entire surface of the semiconductor substrate and then selectively etching the second insulating film to provide an opening in the second insulating film on the wiring; A step of directly forming a conductive resin film containing a noble metal such as gold or silver on the wiring by a printing method; and a step of forming a solder bump by welding solder on the conductive resin film. It is comprised including.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず、第1図(a)に示すように、素子領域(図示せ
ず)を有するシリコン基板1の上に設けた酸化膜2の上
に前記素子領域に接続したアルミニウム配線(図示せ
ず)及び前記アルミニウム配線と接続した外部回路接続
用のアルミニウム電極3を設け、アルミニウム電極3を
含む表面に酸化シリコン膜又はPSG膜等の絶縁膜4を堆
積する。次に、アルミ電極3の上の絶縁膜4を選択的に
エッチングして開口部5を設ける。First, as shown in FIG. 1 (a), on an oxide film 2 provided on a silicon substrate 1 having an element region (not shown), an aluminum wiring (not shown) connected to the element region and An aluminum electrode 3 for connecting an external circuit connected to the aluminum wiring is provided, and an insulating film 4 such as a silicon oxide film or a PSG film is deposited on the surface including the aluminum electrode 3. Next, the opening 5 is provided by selectively etching the insulating film 4 on the aluminum electrode 3.
次に、第1図(b)に示すように、パターニングした
印刷マスク6を開口部5に整合させて載置し、印刷用マ
スク6の上に導電性ペースト7を供給し、ローラー治具
等でスキージして開口部5のアルミニウム電極3の上に
導電性ペースト7を流し込む。Next, as shown in FIG. 1 (b), a patterned printing mask 6 is placed in alignment with the opening 5, and a conductive paste 7 is supplied on the printing mask 6, and a roller jig or the like is provided. And the conductive paste 7 is poured onto the aluminum electrode 3 in the opening 5.
次に、第1図(c)に示すように、印刷用マスク6を
取りはずし、加熱処理して導電性ペースト7を硬化さ
せ、導電性樹脂層7aを形成する。Next, as shown in FIG. 1 (c), the printing mask 6 is removed, and the conductive paste 7 is cured by a heat treatment to form a conductive resin layer 7a.
次に、第1図(d)に示すように、半導体基板1を溶
融半田槽中に浸漬し、導電性樹脂層7aに半田を付着させ
て半田バンプ8を作成する。導電性ペースト7はエポキ
シ樹脂やポリイミド樹脂等に金,銀等の貴金属粉末を分
散させたものを用いる。Next, as shown in FIG. 1 (d), the semiconductor substrate 1 is immersed in a molten solder bath, and solder is adhered to the conductive resin layer 7a to form a solder bump 8. The conductive paste 7 is obtained by dispersing a noble metal powder such as gold and silver in an epoxy resin or a polyimide resin.
ここで、第1図(c)の導電性樹脂層7aの上に半田ペ
ーストを選択的に印刷した後、加熱し、半田ペーストを
溶融して導電性樹脂層7aの上に半田層を形成し、半田バ
ンプ8を形成しても良く、半田ペーストの印刷の厚さを
加減することにより半田バンプ8の高さを制御できる効
果がある。Here, after selectively printing the solder paste on the conductive resin layer 7a of FIG. 1 (c), the solder paste is heated and melted to form a solder layer on the conductive resin layer 7a. Alternatively, the solder bumps 8 may be formed, and the height of the solder bumps 8 can be controlled by adjusting the thickness of the printed solder paste.
以上説明したように本発明は、導電性ペーストを熱硬
化させる事によってカップリング用金属層を形成できる
ので湿式処理でのアルミニウム電極処理のばらつきによ
る品質低下がなく、真空蒸着法のように複雑でかつ多工
程に亘る処理が不用である。従って本発明によって品質
が安定した半田バンプを有する半導体装置の製造方法を
実現できるという効果がある。As described above, the present invention can form a coupling metal layer by heat-curing a conductive paste, so that there is no quality deterioration due to variation in aluminum electrode processing in wet processing, and it is complicated like a vacuum evaporation method. In addition, processing over multiple steps is unnecessary. Therefore, the present invention has an effect that a method of manufacturing a semiconductor device having solder bumps of stable quality can be realized.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図は従
来の半導体装置の製造方法を説明するための半導体チッ
プの断面図である。 1……シリコン基板、2……酸化膜、3……アルミニウ
ム電極、4……絶縁膜、5……開口部、6……印刷用マ
スク、7……導電性ペースト、7a……導電性樹脂層、8
……半田バンプ、10……カップリング用金属膜。1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. FIG. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Oxide film, 3 ... Aluminum electrode, 4 ... Insulating film, 5 ... Opening, 6 ... Printing mask, 7 ... Conductive paste, 7a ... Conductive resin Layer, 8
…… Solder bump, 10 …… Coupling metal film.
Claims (1)
絶縁膜を設け前記第1の絶縁膜上に前記素子領域に接続
する配線を設ける工程と、前記配線を含む前記半導体基
板全面に第2の絶縁膜を設けた後該第2の絶縁膜を選択
的にエッチングし、前記配線上の該第2の絶縁膜に開口
部を設ける工程と、前記開口部の前記配線上に印刷法に
より直接に金,銀等の貴金属を含有してなる導電性樹脂
膜を形成する工程と、前記導電性樹脂膜の上に半田を溶
着して半田バンプを形成する工程とを含むことを特徴と
する半導体装置の製造方法。A step of providing a first insulating film on a semiconductor substrate having an element region and providing a wiring connected to the element region on the first insulating film; and forming a wiring on the entire surface of the semiconductor substrate including the wiring. A step of selectively etching the second insulating film after providing the second insulating film to form an opening in the second insulating film on the wiring, and a method of printing on the wiring in the opening. Forming a conductive resin film directly containing a noble metal such as gold, silver, and the like, and forming a solder bump by welding solder on the conductive resin film. Semiconductor device manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1106209A JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1106209A JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02284426A JPH02284426A (en) | 1990-11-21 |
JP2811741B2 true JP2811741B2 (en) | 1998-10-15 |
Family
ID=14427767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1106209A Expired - Fee Related JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2811741B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2751912B2 (en) | 1996-03-28 | 1998-05-18 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
WO2000010369A1 (en) | 1998-08-10 | 2000-02-24 | Fujitsu Limited | Method of forming solder bump, method of mounting electronic device, and mounting structure of electronic device |
JP4729963B2 (en) * | 2005-04-15 | 2011-07-20 | パナソニック株式会社 | PROJECT ELECTRODE FOR CONNECTING ELECTRONIC COMPONENT, ELECTRONIC COMPONENT MOUNTING BODY USING SAME, AND METHOD FOR PRODUCING THEM |
WO2006112384A1 (en) * | 2005-04-15 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Protruding electrode for connecting electronic component, electronic component mounted body using such electrode and methods for manufacturing such electrode and electronic component mounted body |
WO2008044537A1 (en) * | 2006-10-05 | 2008-04-17 | Nec Corporation | Semiconductor package and method for producing semiconductor package |
JP2008227359A (en) * | 2007-03-15 | 2008-09-25 | Fujitsu Ltd | Semiconductor device and method for manufacturing semiconductor device |
-
1989
- 1989-04-25 JP JP1106209A patent/JP2811741B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH02284426A (en) | 1990-11-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |