JP3847260B2 - Flip chip type IC manufacturing method using IC wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC wafer provided with a plurality of barrier metal layers to which a printing paste is applied, and a method of manufacturing a flip chip type IC using the IC wafer.
[0002]
[Prior art]
Conventionally, an IC is face-down bonded to the upper surface of a circuit board having circuit wiring, that is, the IC is mounted on the circuit board so that the surface on which the integrated circuit of the IC is formed faces the circuit board. Things have been done.
[0003]
An IC used for such face-down bonding is called a flip-chip IC, and generally has a terminal connected to circuit wiring on a circuit board via solder.
[0004]
As such a conventional flip chip type IC, for example, a circuit pattern made of Al or a semiconductor element (not shown) is deposited on the upper surface of a silicon substrate to which an insulating film (not shown) is deposited, and Ni is formed on the circuit pattern. A structure in which a plurality of barrier metal layers composed of a layer and an Au layer are deposited, and a passivation layer composed of silicon nitride or the like is deposited on a non-forming region of the barrier metal layer, and a substantially spherical solder bump is formed on the barrier metal layer When such a flip chip type IC is mounted on a circuit board, the flip chip type IC is arranged so that the solder bump of the flip chip type IC faces the corresponding circuit wiring on the circuit board. The flip-chip barrier metal layer is placed on the substrate, and then the solder bumps are heated and melted at a high temperature. It is soldered to the circuit wiring on the circuit board.
[0005]
And the solder bump provided in the above-mentioned flip chip type IC is usually formed by the following method. That is,
A circuit pattern or a semiconductor element (not shown) is formed on the upper surface of a semiconductor substrate made of single crystal silicon or the like to which an insulating film such as SiO ₂ is applied, and a barrier metal layer is formed on the circuit pattern. An IC wafer in which a passivation layer is formed in a formation region and a printing mask having an opening corresponding to the barrier metal layer are prepared,
Next, the printing mask is disposed on the IC wafer so that the opening is located immediately above the barrier metal layer on the IC wafer,
Next, after supplying the solder paste on the printing mask, the supplied solder paste is printed and applied on the barrier metal layer through the opening,
Finally, the solder paste applied on the barrier metal layer is reflowed to form a substantially spherical solder bump on the barrier metal layer.
[0006]
In order to accurately form the solder bumps on the barrier metal layer by such a method, it is necessary to align the printing mask with respect to the IC wafer with high accuracy. To facilitate such alignment, the IC wafer An alignment mark for alignment of the print mask is provided on the print mask, and a through hole corresponding to the alignment mark is provided on the print mask, and the alignment between the IC wafer and the print mask is performed based on the alignment mark and the through hole. Like to do.
[0007]
The alignment mark is formed of the same material as the circuit pattern, that is, a metal material such as Al, and the surface thereof is generally exposed (see Patent Documents 1 and 2).
[0008]
[Patent Document 1]
JP 2002-29034 A [Patent Document 2]
Japanese Patent Laid-Open No. 9-323401
[Problems to be solved by the invention]
However, when the positioning of the printing mask and the IC wafer is performed with reference to the through hole and the alignment mark, when the solder paste supplied on the printing mask is printed and applied on the IC wafer, the barrier metal layer Solder paste adheres not only on the alignment mark but also on the alignment mark used for alignment via the through hole. When the solder paste printed and applied on the IC wafer is reflowed, it is added to the barrier metal layer and aligned. Unnecessary solder bumps are also formed on the mark. The alignment marks on which such unnecessary solder bumps are formed are made of a metal material such as Al, which has a relatively strong adhesion to the solder. Therefore, in order to remove the unnecessary solder bumps, individually use a solder sucker or the like. The manufacturing process becomes complicated according to the number of unnecessary solder bumps that must be removed, and the productivity of the flip-chip IC may be significantly reduced.
[0010]
The present invention has been devised in view of the above-described drawbacks, and an object of the present invention is to manufacture an IC wafer that can easily remove excess solder bumps formed on the IC wafer, and a flip-chip IC using the IC wafer. It is to provide a method.
[0015]
[Means for Solving the Problems]
A flip chip type IC manufacturing method according to the present invention includes a semiconductor substrate, a plurality of barrier metal layers formed on an upper surface of the semiconductor substrate, and a non-forming region of the barrier metal layer on the upper surface of the semiconductor substrate. Corresponding to the plurality of barrier metal layers on an IC wafer having a passivation layer to be formed and an alignment mark for printing mask alignment provided on the semiconductor substrate and covered with the passivation layer a plurality of openings, a printing mask having a through-hole corresponding to the alignment mark, the step 1 of the through hole directly above the alignment mark is disposed in the position to so that is disposed in the step 1 A paste containing flux is supplied to the upper surface of the printed mask, and the supplied paste is applied to the barrier metal layer through the openings and through holes. Step 2 for applying on the alignment mark, Step 3 for forming a bump on the barrier metal layer and the alignment mark by reflowing the paste applied in Step 2, and the bump obtained in Step 3 And a step 4 of removing bumps on the alignment mark by cleaning the adhered flux.
[0016]
According to the present invention, in an IC wafer formed by forming a plurality of barrier metal layers on the upper surface of a semiconductor substrate and depositing a passivation layer in a region where the barrier metal layers are not formed, the printing mask alignment is performed on the semiconductor substrate. Since the alignment mark is provided, and the alignment mark is covered with the passivation layer, a printing mask having a plurality of openings corresponding to the barrier metal layer and a through hole corresponding to the alignment mark is formed on the alignment mark. When the bumps are formed by printing and applying a paste containing flux on the IC wafer using the printing mask, and unnecessary bumps formed on the alignment marks are formed. It is deposited directly on the passivation layer with poor wettability, and I The adhesion to the wafer can be significantly reduced. Therefore, when cleaning the flux adhering to the bump surface, unnecessary bumps on the alignment mark are easily removed together with the flux, simplifying the manufacturing process of the flip chip IC and improving the productivity of the flip chip IC. Can be improved.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
Figure 1 is a plan view of an IC wafer that will be manufactured by the method according to the present invention, FIG. 2 is a sectional view taken along line X-X of the IC wafer shown in FIG. 1, IC wafer shown in the figure, in generally, the The semiconductor substrate 1 has a structure in which a circuit pattern 2, a barrier metal layer 3, a passivation layer 4, an alignment mark 5, and the like are provided on the upper surface of the semiconductor substrate 1.
[0018]
The semiconductor substrate 1 is formed in a substantially circular shape by a single crystal semiconductor such as single crystal silicon having an insulating film 1a made of an insulating material such as SiO _{2 on} its surface, and the upper surface thereof is formed with no IC formation region A and IC. It is divided into region B.
[0019]
The semiconductor substrate 1 has a semiconductor element, a circuit pattern 2, a barrier metal layer 3, and a passivation layer 4 (not shown) attached to an IC formation region A on the upper surface, and a passivation layer 4 and an alignment mark 5 attached to an IC non-formation region B. And function as a support base material for supporting them. In addition, when such a semiconductor substrate 1 consists of the above-mentioned single crystal silicon, while forming the ingot (lump) which consists of single crystal silicon by employ | adopting a conventionally well-known chocolate ski method (lifting method), for example, This is sliced into a plate shape using a diamond cutter, etc., and a plate body of a predetermined thickness is obtained by surface polishing this, and then a conventionally well-known thermal oxidation method is adopted for such a plate body, It is manufactured by oxidizing the plate body surface to a predetermined depth region (1.5 μm to 4.5 μm) from the surface.
[0020]
The circuit pattern 2 attached to the IC formation region A of the semiconductor substrate 1 is formed in a predetermined pattern from a metal material such as Al or Cu, and the circuit pattern 2 is supplied from an external power source to a semiconductor element (not shown). It functions as a power supply wiring for supplying electric power, electrical signals, and the like.
[0021]
Such a circuit pattern 2 is formed to have a predetermined thickness (0.5 μm to 1.5 μm) by adopting a conventionally well-known thin film forming technique, specifically, sputtering, photolithography technique, etching technique or the like. The
[0022]
Further, the barrier metal layer 3 provided on the circuit pattern 2 has, for example, a three-layer structure in which zinc (Zn), nickel (Ni), and gold (Au) are sequentially stacked from the semiconductor substrate 1 side. The total thickness of the barrier metal layer is set to 0.5 μm to 7.0 μm μm, for example.
[0023]
The barrier metal layer 3 is melted when solder bumps provided on the barrier metal layer 3 are melted when a flip chip IC obtained by processing an IC wafer according to the present invention is mounted on a circuit board. It acts to effectively prevent “erosion” from occurring in the aluminum or the like forming the circuit pattern 2 by the solder.
[0024]
Such a barrier metal layer 3 is formed on the circuit pattern 2 exposed in the opening of the passivation layer 4, that is, in the region where the passivation layer 4 does not exist, after the formation of the passivation layer 4 described later. By adopting plating or the like and sequentially depositing Zn, Ni, and Au, the whole is formed in a substantially cylindrical shape.
[0025]
Of the three layers constituting the barrier metal layer 3, the lowermost Zn layer is a Ni layer formed by a substitution reaction when a Ni layer is formed by a conventionally known electroless plating or the like. The thickness is set to 0.01 μm to 0.05 μm, and the Ni layer as an intermediate layer is for making the solder wettability to the barrier metal layer 3 good. The thickness is set to 0.47 μm to 6.85 μm, and the Au layer as the uppermost layer is for effectively preventing oxidative corrosion of the Ni layer, and the thickness is 0.02 μm to 0.1 μm. Set to
[0026]
On the other hand, the alignment mark 5 attached to the IC non-formation region B of the semiconductor substrate 1 is formed, for example, in a square shape from the same material as the circuit pattern 2, for example, a metal material such as Al or Cu. Is set to two or more (in this embodiment, two).
[0027]
The alignment mark 5 functions as a mark for positioning the print mask on the IC wafer with high accuracy when the print mask is disposed on the IC wafer in order to print / apply the solder paste on the barrier metal layer 3.
[0028]
The alignment mark 5 is formed in the same manner as the circuit pattern 2 described above, that is, by using a thin film forming technique such as sputtering, photolithography technique, etching technique, etc. It is formed to a thickness of 5 μm.
[0029]
A passivation layer 4 is deposited on the non-formation region of the barrier metal layer 3 on the upper surface of the semiconductor substrate 1 described above, and the circuit pattern 2 and the alignment mark 5 are covered in common with the passivation layer 4. .
[0030]
The passivation layer 4 is formed of an electrically insulating material having excellent sealing properties such as silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), and the like. By blocking the mark 5 from the atmosphere well, it effectively prevents these from being corroded by contact with moisture contained in the atmosphere, and the solder paste is directly applied to the alignment mark 5. It works to prevent adhesion.
[0031]
Such a passivation layer 4 employs a conventionally well-known thin film forming technique, for example, a CVD method or a sputtering method. Formed to a thickness of 5 μm to 1.5 μm, and then processed into a predetermined pattern by a conventionally known photolithography and etching technique, that is, by providing an opening at the formation location of the barrier metal layer 3 Is done.
[0032]
Next, a method of manufacturing a flip chip type IC using the above-described IC wafer will be described in detail with reference to FIG. 3 is a cross-sectional view of each process for explaining a method of manufacturing a flip chip type IC using the IC wafer of FIG. 1, wherein 6 is a metal sheet, 7 is an opening, 8 is a through hole, and 9 ′ is a paste. The solder pastes 9a and 9b are solder bumps as bumps.
First, the above-described IC wafer W and printing mask M are prepared (FIG. 3A).
[0033]
The printing mask M includes a metal sheet 6 formed in a plate shape with a metal material such as aluminum alloy or Ni alloy, an opening 7 corresponding to the barrier metal layer 3, and a through hole 8 corresponding to the alignment mark 5. When the printing mask M is made of Ni alloy, for example, it is manufactured by adopting a conventionally known additive method.
Next, an IC wafer W is disposed immediately below the printing mask M (FIG. 3B).
[0034]
In order to dispose the IC wafer W directly below the printing mask M, for example, the IC wafer W is placed and fixed on the stage of the screen printing machine on which the printing mask M is disposed, and the alignment mark 5 is directly above. The IC wafer W is aligned so that the through-hole 8 is positioned at the position, and thereby the print mask M and the IC wafer W are aligned with high accuracy, and the opening 7 of the print mask M is formed on the IC wafer W. It comes to be located right above the barrier metal layer 3.
[0035]
Since the alignment mark 5 is provided in the IC non-formation region B of the semiconductor substrate 1 as described above, the alignment mark 5 is used when the print mask M and the IC wafer W are aligned. It becomes easy to recognize and troubles such as misalignment of the alignment mark 5 with the barrier metal layer 3 can be effectively prevented.
[0036]
Further, since the alignment mark 5 has a shape in plan view different from that of the barrier metal layer 3, the alignment mark 5 is further easily recognized at the time of alignment, and this also makes the alignment mark 5 and the barrier metal layer 3. Troubles such as mistakes can be effectively prevented.
(3) Next, a solder paste 9 ′ is prepared, and the solder paste 9 ′ is supplied onto the printing mask M.
[0037]
As the solder paste 9 ', a paste prepared by adding and mixing a rosin flux to a large number of solder particles to have a predetermined viscosity is suitably used.
(4) Next, the solder paste 9 'on the printing mask M is moved in a predetermined direction while pressing the squeegee toward the IC mask M, so that the solder paste 9' is moved to the openings 7 and the through holes of the printing mask M. 8 is printed / coated on the barrier metal layer 3 and the alignment mark 5 (FIG. 3C).
[0038]
At this time, as described above, since the alignment mark 5 is provided in the IC non-formation region B, the solder paste 9 ′ applied on the alignment mark and the solder paste applied on the barrier metal layer are different from each other. Therefore, there is an advantage that the two can be effectively prevented from being short-circuited due to contact with each other.
(5) Next, by reflowing the applied solder paste 9 ′, the solder particles contained in the solder paste 9 ′ are melted so that the solder particles are coupled to each other and cooled as they are. Solder bumps 9a and 9b are formed on the barrier metal layer 3 and the alignment mark 5 (FIG. 3D).
[0039]
At this time, the solder bumps 9 a on the barrier metal layer 3 are firmly attached to the barrier metal layer 3 by the action of the Ni layer constituting the barrier metal layer 3, but unnecessary solder bumps on the alignment mark 5. Since 9b is formed on the alignment mark 5 through the passivation layer 4 having poor solder wettability, the adhesion force of the solder bump 9b to the passivation layer 4 can be greatly reduced. Therefore, the solder bump 9b on the alignment mark 5 is in a state of being attached to the IC wafer W with extremely weak strength by the action of a flux (not shown) attached to the solder bump itself.
[0040]
The reflow of the solder paste 9 ′ is performed at a temperature of 230 ° C. to 260 ° C., for example.
(6) Next, the flux adhering to the solder bumps 9a and 9b is washed to remove the solder bumps 9b on the alignment mark 5 (FIG. 3E).
[0041]
The cleaning of the flux is performed by swinging up and down while the IC wafer is immersed in a semi-aqueous solvent, whereby the flux residue adhering to the bump is washed away. Therefore, unnecessary solder bumps 9b deposited on the alignment mark 5 by the action of the flux are removed from the alignment mark 5 because the adhesion to the passivation layer 4 is greatly reduced by flux cleaning. Become. Therefore, it is possible to eliminate the trouble of individually removing unnecessary solder bumps 9b with a semiconductor sucking device, simplify the manufacturing process of the flip chip IC, and improve the productivity of the flip chip IC. It becomes.
(7) Finally, the flip-chip type IC is manufactured by processing the IC wafer W into a predetermined shape using a diamond saw or the like.
[0042]
When the obtained flip chip IC is mounted on the circuit board, the flip chip IC is mounted on the circuit board so that the solder bumps of the flip chip IC face the corresponding circuit wiring on the circuit board. After that, the solder bumps are heated and melted at a high temperature, whereby the barrier metal layer of the flip chip is soldered to the circuit wiring on the circuit board.
[0043]
In addition, this invention is not limited to the above-mentioned embodiment, A various change and improvement are possible in the range which does not deviate from the summary of this invention.
[0044]
For example, in the above-described embodiment, if the area of the alignment mark 5 is set to be smaller than the area of the barrier metal layer 3, the alignment can be performed with much higher accuracy than the barrier metal layer 3 is used as a reference for alignment. It becomes possible. Further, at this time, if the opening area of the through hole 8 of the printing mask M is set smaller than the opening 7, the amount of the solder paste 9 'applied from the through hole 8 can be reduced, and the solder paste 9' Waste can be reduced.
[0045]
In the above-described embodiment, a “metal mask” in which a plurality of openings are provided in the metal sheet 6 is used as a printing mask. Instead, various resin materials such as polyimide resin, polyester resin, and polyethylene resin are used. The present invention is applicable even to a mask made of
[0046]
Furthermore, in the above-described embodiment, the solder bump 9a is formed using the solder paste 9 ', but instead of this, a silver bump or other conductive bump is formed using another conductive paste such as a silver paste. You may make it form.
[0047]
Furthermore, in the above-described embodiment, the alignment mark 5 is provided in the IC non-formation region B of the semiconductor substrate 1, but instead of this, it may be provided in the IC formation region A. In this case, the IC formation region If a dummy IC or a TEG (test element group) IC is provided in the area A, troubles such as misalignment of the alignment mark with the barrier metal layer during alignment can be effectively prevented. In addition, there is an advantage that it is possible to effectively prevent the solder paste 9 ′ applied on the alignment mark from causing a short circuit with the solder paste applied on the barrier metal layer.
[0048]
Furthermore, in the above-described embodiment, the barrier metal layer 3 has a three-layer structure of Zn, Ni, and Au. Alternatively, the barrier metal layer may have a two-layer structure. For example, a structure in which Ni and Au are sequentially laminated is considered as an example.
[0049]
Furthermore, in the above-described embodiment, the alignment mark 5 is formed in a quadrangular shape, but instead, the alignment mark may be formed in various shapes such as a triangular shape, a circular shape, and a cross shape.
[0050]
【The invention's effect】
According to the present invention, in an IC wafer in which a plurality of barrier metal layers are formed on an upper surface of a semiconductor substrate and a passivation layer is deposited on a non-formation region of the barrier metal layer, a printing mask is aligned on the semiconductor substrate. Since the alignment mark is provided and the alignment mark is covered with the passivation layer, a printing mask having a plurality of openings corresponding to the barrier metal layer and a through-hole corresponding to the alignment mark is formed on the alignment mark. When a bump is formed by printing and applying a paste containing flux on the IC wafer using the printing mask, and unnecessary bumps are formed on the alignment mark. It is deposited directly on the passivation layer with poor wettability. The adhesion to the wafer can be significantly reduced. Therefore, when cleaning the flux adhering to the bump surface, unnecessary bumps on the alignment mark are easily removed together with the flux, simplifying the manufacturing process of the flip chip IC and improving the productivity of the flip chip IC. Can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view of an IC wafer according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the IC wafer shown in FIG. 1 taken along the line XX.
FIGS. 3A to 3E are cross-sectional views of each step for explaining a method of manufacturing a flip chip type IC using the IC wafer shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Circuit pattern 3 ... Barrier metal layer 4 ... Passivation layer 5 ... Alignment mark 6 ... Metal sheet 7 ... Opening 8 ... Through-hole 9 ' ... Solder paste 9a, 9b ... Solder bump M ... Print mask W ... IC wafer A ... IC formation area B ... IC non-formation area

Claims (1)

A semiconductor substrate; a plurality of barrier metal layers formed on an upper surface of the semiconductor substrate; a passivation layer deposited on a non-formation region of the barrier metal layer on the upper surface of the semiconductor substrate; and provided on the semiconductor substrate. A plurality of openings corresponding to the plurality of barrier metal layers, and a through-hole corresponding to the alignment mark on an IC wafer having an alignment mark for positioning a printing mask covered with the passivation layer. the printing mask having bets, and step 1 of the through hole directly above the alignment mark is disposed in the position to so that,
Step 2 of supplying a paste containing flux to the upper surface of the printing mask disposed in Step 1 and applying the supplied paste on the barrier metal layer and the alignment mark through the opening and the through hole. When,
Step 3 of forming bumps on the barrier metal layer and the alignment mark by reflowing the paste applied in Step 2;
And a step 4 of removing the bumps on the alignment mark by washing the flux adhering to the bumps obtained in the step 3, and a method of manufacturing a flip-chip type IC.

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