JPH02284426A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02284426A JPH02284426A JP1106209A JP10620989A JPH02284426A JP H02284426 A JPH02284426 A JP H02284426A JP 1106209 A JP1106209 A JP 1106209A JP 10620989 A JP10620989 A JP 10620989A JP H02284426 A JPH02284426 A JP H02284426A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bump
- paste
- opening
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000007639 printing Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 238000003466 welding Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 239000010408 film Substances 0.000 description 23
- 238000007747 plating Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000009489 vacuum treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にバンプ電極
を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having bump electrodes.
従来、ハンプ電極を有する半導体装置のバンプ部には金
又は銅が用いられていた。最近になり、低温化、低コス
ト化が要求され、バンプ部の金属として半田(錫・鉛系
)が用いられ始めている。Conventionally, gold or copper has been used for bump portions of semiconductor devices having hump electrodes. Recently, there has been a demand for lower temperatures and lower costs, and solder (tin/lead based) has begun to be used as the metal for the bumps.
第2図は従来の半導体装置を説明するための半導体チッ
プの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional semiconductor device.
第2図に示すように、素子領域く図示せず)を有するシ
リコン基板1の表面に酸化膜2を形成し、酸化膜2の上
に前記素子領域に接続したアルミニウム配線(図示せず
)と接続した外部回路接続用のアルミニウム電極3を形
成し、アルミニウム電極3を含む表面に絶縁膜4を堆積
し、アルミニウム電極3の上の絶縁膜4を選択的にエツ
チングして開孔部を設ける。次に、開口部のアルミニウ
ム電極3の上にチタン、ニッケル、銅などのカップリン
ク用金属膜10を形成し、さらにその上に半田を付着さ
せて半田バンプ8を形成する。アルミニウム電極部3に
カップリンク用金属膜]、 0を形成する方法として真
空蒸着法や湿式めっき法があり、半田を付着させる方法
としては直接、溶融半田槽に浸漬させる方法、湿式めっ
き法か行なわれている。As shown in FIG. 2, an oxide film 2 is formed on the surface of a silicon substrate 1 having an element region (not shown), and aluminum wiring (not shown) connected to the element region is formed on the oxide film 2. An aluminum electrode 3 for external circuit connection is formed, an insulating film 4 is deposited on the surface including the aluminum electrode 3, and the insulating film 4 on the aluminum electrode 3 is selectively etched to provide an opening. Next, a coupling metal film 10 made of titanium, nickel, copper, or the like is formed on the aluminum electrode 3 in the opening, and solder is further applied thereon to form a solder bump 8. There are vacuum evaporation methods and wet plating methods for forming the metal film for cup link on the aluminum electrode portion 3, and methods for attaching solder include direct immersion in a molten solder bath and wet plating methods. It is.
上述した従来の半導体装置は、カップリング用金属膜を
設ける方法が品質9価格の面でネックポイントになって
いる。In the conventional semiconductor device described above, the method of providing a coupling metal film is a bottleneck in terms of quality and price.
例えば湿式めっきではその前処理としてアルミニウム薄
膜表面の酸化膜除去を行なわなりれはならず、処理条件
の制御が困難である。そのため、酸化膜のエツチング過
度によるカップリング用金属の不完全めっきを引き起こ
す。一方酸化膜エツチンク不足の場合はカップリング用
金属の密着不良につながる。いずれの場合も、カップリ
ンク用金属上に設けた半田バンプの強度不良となり、品
質が非常に不安定である。For example, in wet plating, the oxide film on the surface of the aluminum thin film must be removed as a pretreatment, and it is difficult to control the processing conditions. This causes incomplete plating of the coupling metal due to excessive etching of the oxide film. On the other hand, if the oxide film is insufficiently etched, it will lead to poor adhesion of the coupling metal. In either case, the strength of the solder bump provided on the cup link metal is poor, and the quality is extremely unstable.
また、真空蒸着法でカップリング用金属膜を設けるため
には、数回のりソクラフィー工程と真空処理か必要であ
るため、非常に高価な半田ハンプ素子となってしまう。Further, in order to provide a coupling metal film by vacuum evaporation, several lamination steps and vacuum treatment are required, resulting in a very expensive solder hump element.
〔課題を解決するための手段〕
本発明の半導体装置の製造方法は、素子領域を有する半
導体基板の上に第1の絶縁膜を設け前記第1の絶縁膜上
に前記素子領域に接続する配線を設ける工程と、前記配
線を含む表面に第2の絶縁膜を設けて選択的にエツチン
グし前記配線の上に開口部を設ける工程と、前記開口部
の前記配線上に印刷法により導電性樹脂膜を形成する工
程と、前記導電性樹脂膜の上に半田を溶着して半田バン
プを形成する工程とを含んで構成される。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention provides a first insulating film on a semiconductor substrate having an element region, and a wiring connected to the element region on the first insulating film. a step of providing a second insulating film on the surface including the wiring and selectively etching it to form an opening above the wiring; and a step of forming a conductive resin on the wiring in the opening by a printing method. The method includes a step of forming a film, and a step of welding solder onto the conductive resin film to form solder bumps.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
ます、第1図(a>に示すように、素子領域(図示せず
)を有するシリコン基板1の上に設けた酸化膜2の上に
前記素子領域に接続したアルミニウム配線(図示せず)
及び前記アルミニウム配線と接続した外部回路接続用の
アルミニウム電極3を設け、アルミニウム電極3を含む
表面に酸化シリコン膜又はPSG膜等の絶縁膜4を堆積
する。次に、アルミ電極3の上の絶縁HtA 4を選択
的にエツチングして開口部5を設りる。First, as shown in FIG. 1 (a), an aluminum wiring (not shown) connected to the device region is formed on an oxide film 2 provided on a silicon substrate 1 having a device region (not shown).
Then, an aluminum electrode 3 for external circuit connection connected to the aluminum wiring is provided, and an insulating film 4 such as a silicon oxide film or a PSG film is deposited on the surface including the aluminum electrode 3. Next, the insulating HtA 4 on the aluminum electrode 3 is selectively etched to form an opening 5.
次に、第1図(b)に示すように、パターニングした印
刷マスク6を開口部5に整合させて載置し、印刷用マス
ク6の上に導電性ペースト7を供給し、ローラー油臭等
でスキージして開口部5のアルミニウム電極3の上に導
電性ペースト7を流し込む。Next, as shown in FIG. 1(b), the patterned printing mask 6 is aligned and placed on the opening 5, and the conductive paste 7 is supplied onto the printing mask 6 to remove the odor of roller oil. The conductive paste 7 is poured onto the aluminum electrode 3 in the opening 5 using a squeegee.
次に、第1図(c)に示すように、印刷用マスク6を取
りはずし、加熱処理して導電性ベースI・7を硬化させ
、導電性樹脂層7aを形成する。Next, as shown in FIG. 1(c), the printing mask 6 is removed and the conductive base I.7 is cured by heat treatment to form a conductive resin layer 7a.
次に、第1図(d)に示すように、半導体基板1を溶融
半田槽中に浸漬し、導電性樹脂層7aに半田を付着させ
て半田バンプ8を作成する。導電性ペースト7はエポキ
シ樹脂やポリイミド樹脂等に金、銀等の貴金属粉末を分
散させたものを用いる。Next, as shown in FIG. 1(d), the semiconductor substrate 1 is immersed in a molten solder bath, and solder is applied to the conductive resin layer 7a to form solder bumps 8. The conductive paste 7 is made of epoxy resin, polyimide resin, or the like in which noble metal powder such as gold or silver is dispersed.
ここで、第1図(c)の導電性樹脂層7aの上に半田ペ
ーストを選択的に印刷した後、加熱し、半田ペース1〜
を溶融して導電性樹脂層7aの上に半田層を形成し、半
田ハンプ8を形成しても良く、半田ペーストの印刷の厚
さを加減することにより半田バンプ8の高さを制御でき
る効果がある。Here, after selectively printing solder paste on the conductive resin layer 7a of FIG. 1(c), it is heated and solder paste 1 to
A solder layer may be formed on the conductive resin layer 7a by melting the solder bumps 8, and the height of the solder bumps 8 can be controlled by adjusting the thickness of the printed solder paste. There is.
以上説明したように本発明は、導電性ペーストを熱硬化
させる事によってカップリンク用金属層を形成できるの
で湿式処理でのアルミニウム電極処理のばらつきによる
品質低下がなく、真空蒸着法のように複雑でかつ多工程
に亘る処理が不用である。従って本発明によって品質が
安定した半田バンプを有する半導体装置の製造方法を実
現できるという効果がある。As explained above, in the present invention, the metal layer for the cup link can be formed by thermally curing the conductive paste, so there is no quality deterioration due to variations in aluminum electrode processing in wet processing, and it does not require complicated vacuum deposition methods. Moreover, multi-step processing is unnecessary. Therefore, the present invention has the effect of realizing a method of manufacturing a semiconductor device having solder bumps with stable quality.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図は従
来の半導体装置の製造方法を説明するための半導体チッ
プの断面図である。
1・・シリコン基板、2・・・酸化膜、3・・アルミニ
ウム電極、4・・・絶縁膜、5・・開口部、6・・印刷
用マスク、7・・・導電性ペース1へ、7a・・・導電
性樹脂層、8・・・半田バンプ、10・・カップリンク
用金属膜。FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps to explain an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip to explain a conventional method of manufacturing a semiconductor device. FIG. 1... Silicon substrate, 2... Oxide film, 3... Aluminum electrode, 4... Insulating film, 5... Opening, 6... Printing mask, 7... To conductive paste 1, 7a . . . Conductive resin layer, 8. Solder bump, 10. Metal film for cup link.
Claims (1)
前記第1の絶縁膜上に前記素子領域に接続する配線を設
ける工程と、前記配線を含む表面に第2の絶縁膜を設け
て選択的にエッチングし前記配線の上に開口部を設ける
工程と、前記開口部の前記配線上に印刷法により導電性
樹脂膜を形成する工程と、前記導電性樹脂膜の上に半田
を溶着して半田バンプを形成する工程とを含むことを特
徴とする半導体装置の製造方法。a step of providing a first insulating film on a semiconductor substrate having an element region, providing a wiring connected to the element region on the first insulating film, and providing a second insulating film on a surface including the wiring. A step of forming an opening on the wiring by selectively etching, a step of forming a conductive resin film on the wiring in the opening by a printing method, and a step of welding solder on the conductive resin film. A method of manufacturing a semiconductor device, the method comprising: forming solder bumps using a method of manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1106209A JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1106209A JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02284426A true JPH02284426A (en) | 1990-11-21 |
JP2811741B2 JP2811741B2 (en) | 1998-10-15 |
Family
ID=14427767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1106209A Expired - Fee Related JP2811741B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2811741B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6028357A (en) * | 1996-03-28 | 2000-02-22 | Nec Corporation | Semiconductor device with a solder bump over a pillar form |
US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
WO2006112384A1 (en) * | 2005-04-15 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Protruding electrode for connecting electronic component, electronic component mounted body using such electrode and methods for manufacturing such electrode and electronic component mounted body |
JP2006302929A (en) * | 2005-04-15 | 2006-11-02 | Matsushita Electric Ind Co Ltd | Salient electrode for connecting electronic component, electronic component packaging body using the same, and manufacturing method of salient electrode and electronic component packaging body |
WO2008044537A1 (en) * | 2006-10-05 | 2008-04-17 | Nec Corporation | Semiconductor package and method for producing semiconductor package |
JP2008227359A (en) * | 2007-03-15 | 2008-09-25 | Fujitsu Ltd | Semiconductor device and method for manufacturing semiconductor device |
-
1989
- 1989-04-25 JP JP1106209A patent/JP2811741B2/en not_active Expired - Fee Related
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6028357A (en) * | 1996-03-28 | 2000-02-22 | Nec Corporation | Semiconductor device with a solder bump over a pillar form |
US6281107B1 (en) | 1996-03-28 | 2001-08-28 | Nec Corporation | Semiconductor device and method for manufacturing the same |
US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
WO2006112384A1 (en) * | 2005-04-15 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Protruding electrode for connecting electronic component, electronic component mounted body using such electrode and methods for manufacturing such electrode and electronic component mounted body |
JP2006302929A (en) * | 2005-04-15 | 2006-11-02 | Matsushita Electric Ind Co Ltd | Salient electrode for connecting electronic component, electronic component packaging body using the same, and manufacturing method of salient electrode and electronic component packaging body |
US8033016B2 (en) | 2005-04-15 | 2011-10-11 | Panasonic Corporation | Method for manufacturing an electrode and electrode component mounted body |
WO2008044537A1 (en) * | 2006-10-05 | 2008-04-17 | Nec Corporation | Semiconductor package and method for producing semiconductor package |
US7964963B2 (en) | 2006-10-05 | 2011-06-21 | Nec Corporation | Semiconductor package and method for manufacturing semiconductor package |
JP5272729B2 (en) * | 2006-10-05 | 2013-08-28 | 日本電気株式会社 | Semiconductor package and semiconductor package manufacturing method |
JP2008227359A (en) * | 2007-03-15 | 2008-09-25 | Fujitsu Ltd | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2811741B2 (en) | 1998-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |