JPH02251145A - Formation of bump electrode - Google Patents

Formation of bump electrode

Info

Publication number
JPH02251145A
JPH02251145A JP7331389A JP7331389A JPH02251145A JP H02251145 A JPH02251145 A JP H02251145A JP 7331389 A JP7331389 A JP 7331389A JP 7331389 A JP7331389 A JP 7331389A JP H02251145 A JPH02251145 A JP H02251145A
Authority
JP
Japan
Prior art keywords
protective film
terminal electrode
solder
electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7331389A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hirasawa
宏幸 平澤
Kazuo Inoue
和夫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP7331389A priority Critical patent/JPH02251145A/en
Publication of JPH02251145A publication Critical patent/JPH02251145A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/116Manufacturing methods by patterning a pre-deposited material

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To form bump electrodes of high density which only requires a simple technique and a low manufacturing cost by supplying solder collectively to a wide region including a plurality of terminal electrode parts that are formed at openings of a protective film and are quite densely in existence or to the whole surface of a substrate. CONSTITUTION:A protective film 16 is formed at the whole surface of terminal electrode parts 15 that are input/output terminals of a semiconductor integrated circuit and protective film opening 18 are formed on the protective film 16 by photoetching and then, the terminal electrode parts 15 are exposed. Then bump electrode materials are formed on the protective film 16 including the terminal electrode parts 15 and the bump electrode materials 19 are dissolved by treating with heat and then, bump electrodes 20 are formed at the terminal electrode parts 15. The bump electrodes are thus manufactured efficiently with a simple technique and a process is performed at a low cost. Moreover, as the bump electrodes of high density are formed, elements which are disposed with a number of terminals and the terminal electrode parts of high density are packaged.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子素子と回路基板とを接続する際に用いるボ
ンディング用の突起電極の形成方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a protruding electrode for bonding used when connecting an electronic element and a circuit board.

〔従来の技術〕[Conventional technology]

従来用いられているはんだ突起電極の形成方法は、フォ
トエツチング処理を用いたメツキ法に代表される。第4
図(a)、(b)、(C)、(d)、及び(e)は/I
’7キ法による突起電極の形成方法の工程とボンディン
グの状態を示す断面図である。
A conventional method of forming solder bump electrodes is typified by a plating method using photoetching. Fourth
Figures (a), (b), (C), (d), and (e) are /I
FIG. 7 is a cross-sectional view showing the steps and bonding state of a protruding electrode forming method using the '7-ki method.

まず第4図(a)に示すように、例えばシリコンからな
る基板41上に端子電極部42を、蒸着、スパッタ等に
よる成膜後、フォトエツチングによるバターニングによ
って形成する。この端子電極部42は、基板41上の同
図には示されていない半導体機能部と電気的に接続され
ていて、一般にアルミニウム系の材料が用いられる。次
に基板410表面の保護膜46として、絶縁材料を用い
て基板41全面を覆った後、フォトエツチング処理によ
って端子電極部42の中央部を露出する形状の保護膜4
6を形成する。
First, as shown in FIG. 4(a), a terminal electrode portion 42 is formed on a substrate 41 made of silicon, for example, by forming a film by vapor deposition, sputtering, etc., and then patterning by photoetching. This terminal electrode portion 42 is electrically connected to a semiconductor functional portion (not shown) on the substrate 41, and is generally made of an aluminum-based material. Next, as a protective film 46 on the surface of the substrate 410, an insulating material is used to cover the entire surface of the substrate 41, and then a protective film 4 in a shape that exposes the central part of the terminal electrode section 42 is formed by photo-etching.
form 6.

次に第4図(b)に示すように、基板41全面にメツキ
用共通電極層44を、例えばクロム、銅、金等の金属材
料を用いて、蒸着法によって順次成膜し積層形成する。
Next, as shown in FIG. 4(b), a common electrode layer 44 for plating is sequentially deposited and laminated on the entire surface of the substrate 41 using metal materials such as chromium, copper, and gold by vapor deposition.

これらの金属材料は端子電極部42と後工程で形成する
はんだ層との濡れ性・密着性の向上および両材料間の拡
散防止膜としての役目を持ち、一般に数種の金属材料の
積層構造となっている。更にメツキ用共通電極層44上
に、レジスト膜45を個々の突起電極を形成させる部分
を開口する形状にフォトエツチングによって形成する。
These metal materials have the role of improving the wettability and adhesion between the terminal electrode part 42 and the solder layer formed in a subsequent process, and acting as a diffusion prevention film between the two materials, and generally have a laminated structure of several types of metal materials. It has become. Furthermore, a resist film 45 is formed on the plating common electrode layer 44 by photoetching in a shape that opens the portions where the individual projecting electrodes are to be formed.

次に第4図(C)に示すように、メツキはんだ46を、
電解メツキ法によってメツキ用共通電極層44に電流を
供給しながら、レジスト膜45の開口された個々の端子
電極部42上に形成する。その後、基板41全面にフラ
ックス47を塗布する。
Next, as shown in FIG. 4(C), the plating solder 46 is
It is formed on each open terminal electrode portion 42 of the resist film 45 while supplying current to the plating common electrode layer 44 by an electrolytic plating method. After that, flux 47 is applied to the entire surface of the substrate 41.

次に第4図(d)に示すよりに、はんだ突起電極48と
して加熱によって前述のメツキはんだ46をフラックス
47と共に溶融し、溶融はんだの表面張力を利用して、
端子電極部42上にメツキ用共通電極層44を介して接
合された球状電極を形成する。これがいわゆる丸め処理
である。その後、余分なフラックスを洗浄除去し、レジ
スト膜45を剥離する。更にメツキ用共通電極層44の
金、銅、クロムを順次エツチングによって除去するが、
このとき端子電極部42上のメツキ用共通電極層44の
一部はエツチング除去されずに残留する。
Next, as shown in FIG. 4(d), the above-mentioned plating solder 46 is melted together with flux 47 by heating as the solder projection electrode 48, and the surface tension of the molten solder is utilized to
A spherical electrode is formed on the terminal electrode portion 42, which is bonded via the common electrode layer 44 for plating. This is the so-called rounding process. Thereafter, excess flux is removed by washing, and the resist film 45 is peeled off. Furthermore, the gold, copper, and chromium of the plating common electrode layer 44 are sequentially removed by etching.
At this time, a part of the plating common electrode layer 44 on the terminal electrode portion 42 remains without being etched away.

以上の工程によってはんだ突起電極48を完成する。The solder protrusion electrode 48 is completed through the above steps.

このはんだ突起電極48を形成した基板41は、第4図
(e)に示すように、例えばプリント基板などの相対し
て接合される基板49上の基板電極部50上にはんだ突
起電極48を位置合わせし、加熱によってはんだ突起電
極48を溶融して接合はんだ51として両基板がボンデ
ィングされる。
As shown in FIG. 4(e), the solder protruding electrodes 48 are positioned on the substrate electrode portion 50 of the substrate 49 to be bonded to each other, such as a printed circuit board. The solder protruding electrodes 48 are melted by heating, and the two substrates are bonded together as a joining solder 51.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したフォトレジストを用いたメツキ法による従来法
では、メツキ用共通電極層44としての金属層の形成か
らエツチング除去までの工程が長(工数がかかり生産上
コスト高であり、また所定のはんだ突起電極48高さを
得るためにメツキはんだ46厚を厚(する必要がありメ
ツキ時間が長くなるので、生産上の効率が良くない。し
かもこの場合、第4図(C)に示したよ5に、メツキ法
では等方的にメツキはんだ46が形成されるので基板4
1に対して水平な方向にメツキが進む。通常、メツキは
んだ46の高さと直径の比は、約1=3となるので、丸
め処理によって形成される球状のはんだ突起電極48が
十分な高さを有するには、隣接するメツキはんだ46と
の接触を避けるのに十分な端子電極部420間隙を設定
する必要がある。従って、高密度なはんだ突起電極48
の形成に限界があり半導体素子の多端子化、高密度化へ
の対応が困難である等の課題点がある。
In the conventional plating method using the photoresist described above, the process from forming the metal layer as the plating common electrode layer 44 to etching removal is long (man-hours are required and production costs are high; In order to obtain the height of the electrode 48, it is necessary to increase the thickness of the plating solder 46, which increases the plating time, which is not good in production efficiency.Moreover, in this case, as shown in FIG. 4(C), In the plating method, the plating solder 46 is formed isotropically, so the board 4
The plating progresses in a direction horizontal to 1. Normally, the ratio of the height and diameter of the solder plate 46 is approximately 1=3. Therefore, in order for the spherical solder protrusion electrode 48 formed by the rounding process to have a sufficient height, the ratio between the height and the diameter of the plated solder 46 must be It is necessary to set a sufficient gap between the terminal electrode parts 420 to avoid contact. Therefore, the high-density solder protrusion electrode 48
There are problems such as there is a limit to the formation of semiconductor devices, and it is difficult to respond to multi-terminal and high-density semiconductor devices.

本発明の目的は上記のような課題点に着目して、簡便な
手法で低コストであり、多端子で高密度な突起電極の形
成方法を提供することにある。
An object of the present invention is to provide a method for forming a multi-terminal, high-density protruding electrode using a simple method and at low cost, paying attention to the above-mentioned problems.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため本発明における突起電極は下記
記載の工程により製造する。
In order to achieve the above object, the protruding electrode according to the present invention is manufactured by the steps described below.

半導体集積回路の入出力端子である端子電極部上の全面
に保護膜を形成しフォトエツチングによりこの保護膜に
保護膜開口部を形成し端子電極部を露出する工程と、端
子電極部を含む保護膜上に突起電極材料を形成する工程
と、加熱処理を行なうことにより突起電極材料を溶融し
端子電極部に突起電極を形成する工程とを有する。
The process of forming a protective film over the entire surface of the terminal electrode part, which is the input/output terminal of a semiconductor integrated circuit, and forming a protective film opening in the protective film by photoetching to expose the terminal electrode part, and the process of protecting the terminal electrode part. The method includes a step of forming a protruding electrode material on the film, and a step of melting the protruding electrode material by performing heat treatment to form a protruding electrode on the terminal electrode portion.

〔実施例〕〔Example〕

以下本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)、(b)、(C)、(d)及び(e)は本
発明の一実施例を説明するだめの工程を示した断面図で
ある。また、第2図(a)、(b)及び(C)は同工程
を分かりやす(説明するために示した斜視図である。
FIGS. 1(a), (b), (C), (d), and (e) are cross-sectional views showing a final process for explaining an embodiment of the present invention. Further, FIGS. 2(a), 2(b), and 2(C) are perspective views shown for easy understanding (explanation) of the same process.

まず第1図(a)に示すように、例えばシリコンからな
る基板11上に導電層12、下地層16を順次成膜する
。具体的にはまず、導電層12としては、抵抗率が低(
、基板11との良好な接着性を有するアルミニウムある
いはその合金を、蒸着、スパッタリングなどの方法によ
って基板11上全面に約1μm厚に成膜する。ここでア
ルミニウム系の材料は、はんだとの濡れ性に欠(ので、
下地層16としてのはんだとの濡れ性が良好な導電材料
、例えば銅やニッケルなどを蒸着、スパッタリング等の
方法で200nm程の厚さに前述の導電層12上全面に
形成する。その後、下地層16上にレジスト膜14を形
成し、下地層16、導電層12を順次エツチングによる
パターニングを行い、第1図(b)に示す様に、端子電
極部15、電極下地部17を形成する。端子電極部15
は、基板11上の図には示されていない半導体機能部と
電気的に接続されている。次に保護膜16として基板1
1上の全面にリン珪酸ガラスあるいはポリイミドなどの
絶縁材料なCVD、スパッタリングあるいはスピンコー
ド法を用いて約3μm厚に成膜する。更に端子電極部1
5上の電極下地部17におけるはんだ突起電極形成予定
部分を露出させるよ5に、フォトエツチング処理によっ
て保護膜16のパターニングを行い、保護膜開口部18
を有する保護膜16を形成する。ここまでの工程を例え
ば前述ウェハ状の基板11におけるひとつの電子素子ベ
レットの斜視図として示したのが第2図(a)であり、
保護膜開口部18においては電極下地部17が露出して
いる。
First, as shown in FIG. 1(a), a conductive layer 12 and a base layer 16 are sequentially formed on a substrate 11 made of silicon, for example. Specifically, first, the conductive layer 12 has a low resistivity (
Aluminum or its alloy, which has good adhesion to the substrate 11, is formed into a film with a thickness of about 1 μm over the entire surface of the substrate 11 by a method such as vapor deposition or sputtering. Here, aluminum-based materials lack wettability with solder (so
As the base layer 16, a conductive material having good wettability with solder, such as copper or nickel, is formed on the entire surface of the conductive layer 12 to a thickness of about 200 nm by vapor deposition, sputtering, or the like. Thereafter, a resist film 14 is formed on the base layer 16, and the base layer 16 and the conductive layer 12 are sequentially patterned by etching to form the terminal electrode portion 15 and the electrode base portion 17, as shown in FIG. 1(b). Form. Terminal electrode part 15
is electrically connected to a semiconductor functional section on the substrate 11, which is not shown in the figure. Next, the substrate 1 is used as a protective film 16.
A film of insulating material such as phosphosilicate glass or polyimide is formed on the entire surface of the substrate 1 to a thickness of about 3 μm using CVD, sputtering, or spin-coding. Furthermore, the terminal electrode part 1
In step 5, the protective film 16 is patterned by photo-etching to expose the portion of the electrode base 17 on the electrode base 17 where the solder protrusion electrode is to be formed, and the protective film opening 18 is formed.
A protective film 16 is formed. FIG. 2(a) shows the steps up to this point, for example, as a perspective view of one electronic element pellet on the wafer-shaped substrate 11.
The electrode base portion 17 is exposed in the protective film opening 18 .

しかる後第1図(c) K示すように、はんだ層19と
して、はんだペーストを印刷法、転写法、あるいはディ
スペンス法等により保護膜開口部18を含む保護膜16
上に供給する。この供給形態を分かりやす(斜視図で示
したのが第2図(b)で、保護膜開口部18が高密度に
複数存在する領域、つまり端子電極部15が連続的に形
成されている領域においては、複数の保護膜開口部18
を含む領域に広域的にはんだの供給を行ない、ひとつの
電子素子ベレットに単数あるいは複数のはんだ供給領域
が存在する状態となる。同図においては2つのはんだ層
19領域が存在する例を示している。
Thereafter, as shown in FIG. 1(c) K, a solder paste is applied to the protective film 16 including the protective film openings 18 by a printing method, a transfer method, a dispensing method, etc. as a solder layer 19.
feed on top. This supply form is easy to understand (a perspective view is shown in FIG. 2(b), where a plurality of protective film openings 18 are present at high density, that is, an area where terminal electrode portions 15 are continuously formed. , a plurality of protective film openings 18
Solder is supplied over a wide area to the region including the solder, and one electronic element pellet has one or more solder supply regions. The figure shows an example in which two solder layer 19 regions exist.

次に第1図(d)に示す様に、突起電極20として、前
述のはんだ層19を200°C〜300℃の温度で加熱
溶融し、溶融はんだの表面張力を利用して保護膜開口部
18において電極下地部17を介して端子電極部15と
接合した球状のはんだを形成させ、放冷によって球状の
まま硬化させる丸め処理を行なう。第2図(C)は、突
起電極20の完成状態を示す斜視図である。
Next, as shown in FIG. 1(d), the solder layer 19 described above is heated and melted at a temperature of 200°C to 300°C to form the protruding electrode 20, and the surface tension of the molten solder is used to form the protective film opening. In step 18, a spherical solder is formed which is bonded to the terminal electrode part 15 via the electrode base part 17, and a rounding process is performed in which it is left to cool and harden while remaining in the spherical shape. FIG. 2(C) is a perspective view showing the completed state of the protruding electrode 20.

このとき複数の端子電極部15に対して広域的に供給さ
れていたはんだペーストは、溶融状態において保護膜1
6に対しては濡れることはなく、露出された端子電極部
15上の電極下地部17にのみ毛管現象によって凝集す
るので、個りの端子電極部15上に独立した突起電極2
0を形成することが可能である。
At this time, the solder paste that was widely supplied to the plurality of terminal electrode parts 15 is melted into the protective film 1.
6 does not get wet and aggregates only on the electrode base portion 17 on the exposed terminal electrode portion 15 by capillary phenomenon, so that the protruding electrode 2
It is possible to form a zero.

またこの場合はんだの組成とはんだの粘度、粘着性、だ
れ性は、はんだペースト中に含有されるフラックスによ
って左右されるが、通常突起電極の形成においては3w
t%〜15wt%のフラックスを含有するものが適当で
ある。更にはんだからなる突起電極20の高さは一般に
、端子電極ピンチ200μm〜300μmにおいて50
μm〜100μmが適当であるが、本発明知おいては、
突起電極のピッチに適応して、はんだの供給厚と供給面
積によって突起電極の高さを調節することが可能である
In addition, in this case, the composition of the solder and the viscosity, adhesion, and dripping properties of the solder are influenced by the flux contained in the solder paste.
One containing t% to 15wt% of flux is suitable. Furthermore, the height of the protruding electrode 20 made of solder is generally 50 μm at a terminal electrode pinch of 200 μm to 300 μm.
μm to 100 μm is suitable, but according to the present invention,
In accordance with the pitch of the protruding electrodes, the height of the protruding electrodes can be adjusted by adjusting the solder supply thickness and supply area.

丸め処理において溶融はんだの短絡現象によって、隣接
する突起電極20ど5しの短絡の発生が考えられるが、
一般にその原因は■端子電極位置の設計上の問題、■製
造条件、および■汚染されたはんだ等によるものであり
、それらの要素を配慮することで短絡を防止することが
可能である。
It is conceivable that a short circuit between adjacent protruding electrodes 20 and 5 may occur due to a short circuit phenomenon of molten solder during the rounding process.
Generally, the causes of this are: (1) design problems with the terminal electrode position, (2) manufacturing conditions, and (3) contaminated solder. By taking these factors into consideration, it is possible to prevent short circuits.

またはんだ層19の高さの管理による短絡現象の防止手
段として保護膜16を厚く成膜する方法、あるいはソル
ダレジストを端子電極部15間に塗る方法等も考えられ
る。
As a means of preventing short-circuiting by controlling the height of the solder layer 19, a method of forming a thick protective film 16 or a method of applying a solder resist between the terminal electrode portions 15 may be considered.

このはんだ突起電極20を形成した基板11は、第1図
(el)に示すように、例えばプリント基板のよ5に基
板11に相対して接合する基板21に形成されている基
板電極部22上に位置合わせを行い、加熱によって突起
電極20を溶融して形成される接合はんだ26によって
両差板をボンディングする。
As shown in FIG. 1 (el), the substrate 11 on which the solder protruding electrodes 20 are formed is placed on a substrate electrode portion 22 formed on a substrate 21 that is bonded opposite to the substrate 11, such as a printed circuit board 5, for example. After alignment, the two difference plates are bonded using a joining solder 26 formed by melting the protruding electrodes 20 by heating.

第3図(aL (b)及び(C)は本発明の別の実施例
による突起電極の形成をひとつの電子素子ベレットによ
って示した斜視図である。
FIGS. 3(b) and 3(c) are perspective views showing the formation of protruding electrodes using one electronic device pellet according to another embodiment of the present invention.

ここで前述における実施例と同様な部分には、同様な符
号を付してその詳細な説明を省略する。
Here, the same parts as in the embodiment described above are given the same reference numerals, and detailed explanation thereof will be omitted.

この実施例の特徴とするところは、前述例の第1図(a
)で示したはんだに濡れる下地層16の形成を、端子電
極部15を形成した後、ただちに突起電極形成予定領域
を開口した保護膜16を形成し、続いて第3図(a)に
示すよ5に、端子電極部15上の電極下地部17以外に
保護膜16上にも保護膜上の下地層61をパターンとし
て残留させたことである。
The feature of this embodiment is as shown in FIG.
) The formation of the base layer 16 that is wettable with solder is performed by immediately forming the protective film 16 with an opening in the region where the protruding electrode is to be formed after forming the terminal electrode portion 15, and then as shown in FIG. 3(a). 5. In addition to the electrode base portion 17 on the terminal electrode portion 15, the base layer 61 on the protective film is left as a pattern on the protective film 16.

この後、はんだペーストを印刷法、転写法、あるいはデ
ィスペンス法等てより基板11全面に供給し全面はんだ
層62を形成して、加熱溶融によるはんだの丸め処理を
行なう。その際、保護膜16上にも形成される素子機能
部と電気的に接続が無いはんだバンプは、エキストラバ
ンプ66と呼ぶこと、にする。このエキストラバンプ6
6は、素子ペレット実装時の機械的な安定を促す役目を
持ったバンプとして用いることができる。更に、素子ペ
レットが半導体メモリーである場合に、誤動作の原因と
なるα線の遮蔽効果を持つバリアメタルとして用いる等
の有効な活用法がある。
Thereafter, solder paste is supplied to the entire surface of the substrate 11 by a printing method, a transfer method, a dispensing method, etc. to form a solder layer 62 on the entire surface, and the solder is rounded by heating and melting. At this time, solder bumps that are also formed on the protective film 16 and are not electrically connected to the element functional parts are referred to as extra bumps 66. This extra bump 6
6 can be used as a bump that has the role of promoting mechanical stability during device pellet mounting. Furthermore, when the element pellet is a semiconductor memory, there are effective ways of using it, such as using it as a barrier metal that has the effect of shielding alpha rays that can cause malfunctions.

エキストラバンプ66の形状は、保護膜16上に形成す
る保護膜上の下地層61のパターン形状によって任意な
形状に形成することが可能であり、これは端子電極部1
5のレイアウトや第1図(e)に示した素子ペレフトを
ボンディングする側の基板電極部22の形状、あるいは
ボンディング時の機械的安定性、更に接合する基板の膨
張係数差から発生する応力や、両差板間隙を埋める封止
材から発生する応力等を考慮して、その形状を設計する
ことがで詫る。
The shape of the extra bump 66 can be formed into any shape depending on the pattern shape of the base layer 61 on the protective film formed on the protective film 16.
5 layout, the shape of the substrate electrode portion 22 on the side to which the element platen is bonded as shown in FIG. We apologize for the inconvenience that the shape should be designed taking into account the stress generated by the sealing material that fills the gap between the two differential plates.

以上、本発明による実施例の構成について述べてきたが
、本発明は、これらの構成に限定されるものではなく、
例えば端子電極部15がはんだとの濡れ性を有す材料、
例えば銅やニッケル等の導電材料で構成される場合ては
必ずしも下地層16を形成する必要がなく、工程の簡略
化を図ることが可能である。
Although the configurations of the embodiments according to the present invention have been described above, the present invention is not limited to these configurations.
For example, the terminal electrode portion 15 is made of a material that has wettability with solder;
For example, if it is made of a conductive material such as copper or nickel, it is not necessarily necessary to form the base layer 16, and the process can be simplified.

また第3図において保護膜16上の保護膜上の下地層6
1を形成させずに、エキストラバンプ66をまったく形
成しない構成にすることももちろん可能である。この場
合、第1図で示した一連の工程との違いは下地層16の
形成を保護膜16の形成前に行うか、保護膜16の形成
後に行うかである。このとき第1図(a)に示す様に、
フォトエツチング処理において同一のレジストで下地層
16と導電層12をパターニングすることが可能である
ので前者の方が後者よりも工程数が少な(、生産コスト
的には有利である。
In addition, in FIG. 3, the base layer 6 on the protective film 16 is
Of course, it is also possible to have a configuration in which no extra bump 66 is formed at all. In this case, the difference from the series of steps shown in FIG. 1 is whether the base layer 16 is formed before or after the formation of the protective film 16. At this time, as shown in Figure 1(a),
Since it is possible to pattern the base layer 16 and the conductive layer 12 using the same resist in the photoetching process, the former requires fewer steps than the latter (and is advantageous in terms of production cost).

更に下地層16あるいは保護膜上の下地層61の構成は
、はんだと濡れ性向上のほかに材料間の応力緩和、ある
いは材料間の反応防止などの目的からアルミニウム/ク
ロム/銅、チタン/銅/ニンケル、クロム/銅/ニッケ
ル、するいはクロム/銅/金といった複数の導電材料で
あってもよい。
Furthermore, the composition of the base layer 16 or the base layer 61 on the protective film is aluminum/chromium/copper, titanium/copper/ It may be multiple conductive materials such as nickel, chromium/copper/nickel, or chromium/copper/gold.

また突起電極20の材料は、はんだペーストに限らず、
例えば蒸着法等による金属はんだでもよく、供給を行っ
た後フラツクスを基板全面にスピンコードにより塗布し
てから丸め処理を行な5ことも可能である。
Further, the material of the protruding electrode 20 is not limited to solder paste.
For example, metal solder may be used by vapor deposition or the like, and after supplying flux, it is also possible to apply flux to the entire surface of the substrate using a spin cord and then perform rounding.

また突起電極20は端子電極部15上ではなく、第1図
(e)において端子電極部15に相対して接合する基板
21側の基板電極22上に形成するか、あるいは接合す
る両方の基板の両端子電極部上に形成してもいっこうに
構わない。
Further, the protruding electrode 20 is not formed on the terminal electrode section 15, but on the substrate electrode 22 on the side of the substrate 21 to be bonded facing the terminal electrode section 15 in FIG. It does not matter if it is formed on both terminal electrode parts.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように本発明におけるはんだ突起電極の形
成法では、はんだを高密度に存在する複数の端子電極部
を含む広域、あるいは基板全面に対して一括供給を行な
うようにすることで、突起電極を簡便な手法で能率的に
製造することができ、工程の低コスト化が可能であり、
しかも非常に高密度突起電極の形成が可能となるので多
端子、高密度端子電極部配置な素子の実装を提供するこ
とが可能になる。
As described in detail above, in the method of forming solder protruding electrodes according to the present invention, solder is supplied to a wide area including a plurality of terminal electrode parts present at a high density, or to the entire surface of the board, thereby forming protruding solder electrodes. Electrodes can be manufactured efficiently using a simple method, and the cost of the process can be reduced.
Moreover, since it becomes possible to form extremely high-density protruding electrodes, it becomes possible to provide element mounting with multiple terminals and a high-density terminal electrode arrangement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)、(C)、(d)および(e)は
いずれも本発明における第1の実施例の工程を示す断面
図、第2図(a)、(b)および(C)はいずれも本発
明の第1の実施例を説明するための斜視図、第3図(a
)、(b)およれも従来例の工程を示す断面図である。 11・・・・・・基板、 2・・・・・・導電層、 6・・・・・・下地層、 4・・・・・・レジスト膜、 5・・・・・・端子電極部、 6・・・・・・保護膜、 7・・・・・・電極下地部、 8・・・・・・保護膜開口部、 9・・・・・・はんだ層、 0・・・・・・突起電極、 1・・・・・・相対して接合する基板、2・・・・・・
基板電極部、 6・・・・・・接合はんだ、 1・・・・・・保護膜上の下地層、 2・・・・・・全面はんだ層、 6・・・・・・エキストラパンツ。
FIGS. 1(a), (b), (C), (d) and (e) are all sectional views showing the steps of the first embodiment of the present invention, and FIGS. 2(a), (b) and (C) are both perspective views for explaining the first embodiment of the present invention, and FIG.
) and (b) are also sectional views showing the steps of the conventional example. 11...Substrate, 2...Conductive layer, 6...Underlayer, 4...Resist film, 5...Terminal electrode part, 6... Protective film, 7... Electrode base portion, 8... Protective film opening, 9... Solder layer, 0... Protruding electrodes, 1... Substrates to be joined to each other, 2...
Substrate electrode portion, 6... Bonding solder, 1... Base layer on protective film, 2... Whole surface solder layer, 6... Extra pants.

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路の入出力端子である端子電極部上の全面
に保護膜を形成しフォトエッチングにより前記保護膜に
保護膜開口部を形成し前記端子電極部を露出する工程と
、前記端子電極部を含む前記保護膜上に突起電極材料を
形成する工程と、加熱処理を行なうことにより前記突起
電極材料を溶融し前記端子電極部に突起電極を形成する
工程とを有することを特徴とする突起電極形成方法。
forming a protective film over the entire surface of the terminal electrode portion, which is an input/output terminal of a semiconductor integrated circuit; and forming a protective film opening in the protective film by photoetching to expose the terminal electrode portion; and a step of exposing the terminal electrode portion. forming a protruding electrode material on the protective film containing the protruding electrode; and melting the protruding electrode material by performing heat treatment to form a protruding electrode on the terminal electrode portion. Method.
JP7331389A 1989-03-24 1989-03-24 Formation of bump electrode Pending JPH02251145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7331389A JPH02251145A (en) 1989-03-24 1989-03-24 Formation of bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7331389A JPH02251145A (en) 1989-03-24 1989-03-24 Formation of bump electrode

Publications (1)

Publication Number Publication Date
JPH02251145A true JPH02251145A (en) 1990-10-08

Family

ID=13514561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7331389A Pending JPH02251145A (en) 1989-03-24 1989-03-24 Formation of bump electrode

Country Status (1)

Country Link
JP (1) JPH02251145A (en)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
WO2006025387A1 (en) * 2004-09-03 2006-03-09 Matsushita Electric Industrial Co., Ltd. Bump forming method and solder bump
WO2006030674A1 (en) * 2004-09-15 2006-03-23 Matsushita Electric Industrial Co., Ltd. Flip chip mounting method and flip chip mounting element
JP2006147968A (en) * 2004-11-24 2006-06-08 Matsushita Electric Ind Co Ltd Method and device for flip chip packaging
JP2008198745A (en) * 2007-02-09 2008-08-28 Sumitomo Bakelite Co Ltd Solder bump forming method, solder bump, semiconductor device and manufacturing method of semiconductor device
JP2009135452A (en) * 2007-10-31 2009-06-18 Sanyo Electric Co Ltd Device mounting board, semiconductor module, and mobile device
US7726545B2 (en) 2005-03-16 2010-06-01 Panasonic Corporation Flip chip mounting process and bump-forming process using electrically-conductive particles as nuclei
US7910403B2 (en) 2005-03-09 2011-03-22 Panasonic Corporation Metal particles-dispersed composition and flip chip mounting process and bump-forming process using the same
US8283246B2 (en) 2005-04-06 2012-10-09 Panasonic Corporation Flip chip mounting method and bump forming method
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799607B2 (en) 2004-09-03 2010-09-21 Panasonic Corporation Process for forming bumps and solder bump
WO2006025387A1 (en) * 2004-09-03 2006-03-09 Matsushita Electric Industrial Co., Ltd. Bump forming method and solder bump
WO2006030674A1 (en) * 2004-09-15 2006-03-23 Matsushita Electric Industrial Co., Ltd. Flip chip mounting method and flip chip mounting element
US8012801B2 (en) 2004-09-15 2011-09-06 Panasonic Corporation Flip chip mounting process and flip chip assembly
US7759162B2 (en) 2004-09-15 2010-07-20 Panasonic Corporation Flip chip mounting process and flip chip assembly
JP2006147968A (en) * 2004-11-24 2006-06-08 Matsushita Electric Ind Co Ltd Method and device for flip chip packaging
JP4543899B2 (en) * 2004-11-24 2010-09-15 パナソニック株式会社 Flip chip mounting method and flip chip mounting apparatus
US8709293B2 (en) 2004-12-17 2014-04-29 Panasonic Corporation Flip-chip mounting resin composition and bump forming resin composition
US7910403B2 (en) 2005-03-09 2011-03-22 Panasonic Corporation Metal particles-dispersed composition and flip chip mounting process and bump-forming process using the same
US7726545B2 (en) 2005-03-16 2010-06-01 Panasonic Corporation Flip chip mounting process and bump-forming process using electrically-conductive particles as nuclei
US8283246B2 (en) 2005-04-06 2012-10-09 Panasonic Corporation Flip chip mounting method and bump forming method
JP2008198745A (en) * 2007-02-09 2008-08-28 Sumitomo Bakelite Co Ltd Solder bump forming method, solder bump, semiconductor device and manufacturing method of semiconductor device
JP2009135452A (en) * 2007-10-31 2009-06-18 Sanyo Electric Co Ltd Device mounting board, semiconductor module, and mobile device

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