WO1997018584A1 - Method for forming bump of semiconductor device - Google Patents

Method for forming bump of semiconductor device Download PDF

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Publication number
WO1997018584A1
WO1997018584A1 PCT/JP1996/002871 JP9602871W WO9718584A1 WO 1997018584 A1 WO1997018584 A1 WO 1997018584A1 JP 9602871 W JP9602871 W JP 9602871W WO 9718584 A1 WO9718584 A1 WO 9718584A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
solder
semiconductor device
forming
adhesive
Prior art date
Application number
PCT/JP1996/002871
Other languages
French (fr)
Japanese (ja)
Inventor
Tetsuo Satou
Yoshihiro Ishida
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Priority to US08/860,857 priority Critical patent/US6066551A/en
Publication of WO1997018584A1 publication Critical patent/WO1997018584A1/en

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns

Definitions

  • the present invention relates to a method for forming a bump formed on a pad electrode in a flip-chip type semiconductor device or the like.
  • solder bumps are formed on pad electrodes.
  • a method for forming the solder bumps a vapor deposition method, an electrolytic plating method, a stud bump method, and the like have been conventionally used.
  • the vapor deposition method has recently been used to increase the diameter of a wafer and to reduce the bump pitch and shape.
  • the stud bump method is used only on a trial basis because of its high cost.
  • the electrolytic plating method has become mainstream instead of the vapor deposition method.
  • FIG. 17 is a view showing a conventional bump formed by an electrolytic plating method.
  • 1 is a wafer
  • 2 is an aluminum pad electrode
  • 3 is a passivation film
  • 100 is an electrolytic plating bump
  • 101 is a base metal film
  • 102 is a copper core
  • 1 is a copper core.
  • 03 is a solder bump.
  • the wafer 11 aluminum, chromium, and copper are vapor-deposited on the wafer 11 by vacuum deposition to form an underlying metal film 101 in order to ensure reliability of the electrical connection between the pad electrode of the semiconductor element and the electrical connection. .
  • a plating resist is applied, a predetermined portion of the plating resist is opened, and the underlying metal film 101 on the aluminum pad electrode portion 2 is exposed, and copper is used as the underlying metal film 101 as a common electrode.
  • An electrolytic plating is performed to form a copper core 102, and then an electrolytic plating of the solder is performed.
  • the mask resist is peeled off, and the other underlying metal film is etched while the underlying metal film 101 of the bump portion is left.
  • a flux is applied, and the solder is melted in a reflow oven in a nitrogen atmosphere to complete the electrolytic plating bump 100.
  • a copper core of about 20 / zm is plated on the underlying metal film to prevent the solder bumps from crushing and shorting to the side of the semiconductor element. I have. For this reason, copper is a rigid body and firmly adheres to the underlying metal film.
  • the chip size increases, the temperature changes of heating and cooling increase, and the difference in the linear expansion coefficient between copper and the silicon substrate causes Stress was applied to the lower part of the copper core, causing interfacial delamination, disconnection, and cracking of silicon, leading to reliability problems.
  • the present invention has been made in view of the above circumstances, and requires only a simple process.
  • the purpose of the present invention is to provide a method for forming bumps of a semiconductor device that can obtain a highly reliable product.
  • the present invention provides a plating step of performing electroless plating on a pad electrode of a semiconductor element, an adhesive treatment step of applying an adhesive to an electroless plating portion, and a step of applying an adhesive to a portion provided with an adhesive.
  • the method includes a solder particle attaching step of attaching one or more solder particles, and a solder melting step of melting the solder particles to form a bump.
  • a metal core is interposed in the bump, and at least one of the gold core is previously mixed in some or all of the solder particles.
  • the metal core may be mixed with solder particles and adhered to a portion provided with an adhesive, so that the metal core is interposed in a bump during a solder melting step.
  • a method may be adopted in which the adhesive is applied to the electrode portion in a bonding agent treatment step and a metal core attachment step that are independent and independent of the solder particle attachment step, so as to be interposed in the bump during the solder melting step.
  • the present invention relates to a process for treating a bridging agent, a process for attaching solder particles, and a process for melting solder.
  • It consists of a high-temperature solder adhesive treatment step, a high-temperature solder paste adhesion step and a high-temperature solder melting step, and a low-temperature solder adhesive treatment step, a low-temperature solder particle adhesion step and a low-temperature solder fusion step.
  • the high-temperature solder functions as a metal core.
  • a highly reliable semiconductor device can be obtained by a simple process. It does not require expensive equipment and can easily respond to changes in wafer size.
  • FIG. 1 is a process chart showing a first embodiment of a bump forming method for a semiconductor device according to the present invention.
  • 2 (a) to 2 (f) are cross-sectional views of a main step of the first embodiment in the same manner.
  • FIG. 3 is a sectional view of a bump formed by a second embodiment of the method for forming a bump of a semiconductor device of the present invention.
  • FIGS. 4 (a) and 4 (b) are cross-sectional views of an electrode portion in main steps in a third embodiment of the bump forming method for a semiconductor device according to the present invention.
  • FIG. 5 is a cross-sectional view showing a state in which a semiconductor element having bumps formed by the method of the second embodiment is bonded to a circuit board.
  • FIG. 6 is a cross-sectional view showing a state in which three metal cores are interposed in a solder bump by the method of the third embodiment.
  • FIG. 7 is a process chart showing a fourth embodiment of the method for forming a bump of a semiconductor device of the present invention.
  • FIGS. 8 (a) to 8 (d) are cross-sectional views of an electrode part of a main process in the first stage of the fourth embodiment.
  • FIGS. 9 (a) to 9 (c) are cross-sectional views of an electrode part of a main process in the second stage of the fourth embodiment.
  • FIG. 10 is a process chart showing another embodiment using a metal core in the bump forming method for a semiconductor device of the present invention.
  • FIG. 11 is a process diagram showing a fifth embodiment of the bump forming method for a semiconductor device of the present invention.
  • FIGS. 12 (a) to 12 (e) are cross-sectional views of an electrode part in a main step in the same manner as in the fifth embodiment.
  • FIG. 13 is a plan view of a semiconductor device in which a metal core is interposed in at least three solder bumps by the bump forming method for a semiconductor device according to the present invention.
  • FIG. 14 is a plan view showing a use state of a semiconductor element manufactured by each embodiment of the method for forming a bump of a semiconductor element of the present invention.
  • FIG. 15 is a cross-sectional view for explaining an alignment state of a semiconductor element manufactured in each embodiment of the method for forming a bump of a semiconductor element of the present invention on a tray.
  • FIG. 16 is a cross-sectional view for explaining a state in which semiconductor elements manufactured in each embodiment of the method for forming bumps of a semiconductor element of the present invention are aligned on a tray.
  • FIG. 17 is a cross-sectional view of a conventional solder bump.
  • BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the accompanying drawings.
  • FIG. 1 is a process diagram
  • FIGS. 2 (a) to (f) are cross-sectional views of an electrode portion in a main process.
  • the oxide film of the aluminum pad electrode 2 of the semiconductor element completed on the wafer 11 is removed.
  • an activation process step S2 an activation process for selectively electrolessly plating nickel on the pad electrode 2 is performed.
  • the electroless nickel plating step S3 a nickel film 11 as a metal is electrolessly plated on the pad electrode 2 as shown in FIG. 2 (b).
  • Reference numeral 3 denotes a passivation film.
  • the wafer 1 is placed in a chemical tank in order to selectively apply the pressure-sensitive adhesive 4 to the metal portion exposed on the wafer 1 Soak and dry.
  • the solder particles 12 are sprinkled on the wafer 11, as shown in FIG. 2 (d).
  • the diameter of the solder particles 12 is about 100 / m.
  • a post-processing step S6 after performing a heat treatment for temporarily bonding the solder pieces to the electrode portions, as shown in FIG. 2 (e), the solder existing in a portion other than the portion where the adhesive 4 is applied is provided. Lightly brush and remove particles 12. As a result, only the solder paste 12 at the portion where the adhesive 4 is applied remains.
  • solder particles 12 are fixed to the metal part of the hearth 1 in a flux application step S 7, and then the reflow furnace S 8 is used in a solder reflow step S 8.
  • the molten solder 14 is rolled into a ball by surface tension as shown in Fig. 2 (f). Then, after cleaning and drying, inspection is performed in an inspection step S9 to complete solder bumps 10 on the wafer.
  • the process returns to the adhesive treatment step S4, and the subsequent steps are repeated.
  • one solder particle is adhered to one electrode by setting the diameter of the solder to about 100 / im.
  • the present invention is not limited to this. May be attached.
  • FIG. 3 is a sectional view of the solder bump formed in the second embodiment.
  • the method of the second embodiment of the present invention is formed by the same steps as those in FIG. 1 except that the activation step S 2 and the electroless nickel plating step S 3 in FIG. 1 are omitted. Ooo
  • solder particle attaching step S 5 post-processing Step S 6
  • flux application step S 7 solder riff opening one step S 8 are performed to form solder bumps 10 as shown in FIG. 3.
  • This embodiment can be applied when diffusion of tin or lead into a pad electrode metal such as aluminum or an intermetallic compound can be tolerated.
  • the electroless plating is not limited to nickel, but may be plating such as gold, copper, chromium, or the like, or may be a multilayer or mixed plating thereof.
  • FIG. 4 shows a cross-sectional view of an electrode part in a main step of the third embodiment.
  • bumps are formed based on the steps shown in FIG. 1.
  • the solder particles 1 2 a ball-shaped metal core 13 made of a metal such as copper is mixed.
  • the diameter of the metal core 13 is about 20 m, and the diameter of the solder particles 12 is about 100 m. As described above, when the diameter of the metal core 13 is smaller than the thickness of the solder particles 12 (the thickness of the present embodiment is about 30 ⁇ m), a sufficient amount of solder for the metal core 13 is secured. No need to refill the solder later It becomes.
  • solder particles 12 containing the metal core 13 are fixed to the metal part of the hearth 1 with the adhesive 14, and then the flux is applied on the surface of the hearth 1 in the flux application step S7.
  • Solder reflow process By passing through the reflow furnace in step S8, the molten solder with the metal core 13 interposed is rounded into a ball shape 14 by surface tension, and the solder is soldered as shown in Fig. 4 (b). The bump 10 is formed.
  • the adhesive treatment step S4 And repeat the subsequent steps. In this case, it is not necessary to use the solder particles 12 containing a metal core, and the diameter of the solder particles may be determined according to the required film thickness.
  • FIG. 5 shows an example in which a semiconductor element 1a on which a bump is formed by the method of the third embodiment is bonded to a gold-plated connection electrode 202 of a circuit board 200. It functions as a spacer between the element 1a and the substrate 200, and since the metal core 13 is wrapped in the solder 14a and does not directly adhere to the nickel film 11, the stress is reduced and the reliability is reduced. Excellent connection and easy bonding can be obtained.
  • a plurality of metal cores 13 can be mixed in the inside of the solder particles 12, and in this case, a solder bump 14 as shown in FIG. 6 can be obtained.
  • FIGS. 7, 8, and 9 show a fourth embodiment of the present invention.
  • FIG. 7 is a process chart of the method of this embodiment
  • FIGS. 8 (a) to (d) show cross-sectional views of the electrode part at the time of the main process in the first stage
  • FIGS. (C) shows a cross-sectional view of the electrode part of the main process in the second stage.
  • an adhesive treatment step S4 is performed as shown in FIG. 8 (a), and then, as shown in FIG. 8 (b), the solder particles 12 And the metal core 13 are mixed and adhered to the adhesive 4.
  • the proportion of the mixture of the solder particles 12 and the metal cores 13 depends on the number of bumps per chip, but should be such that the chips are substantially parallel when bonded.
  • a post-processing step S6 is performed, and then a flux coating step S7 is performed.
  • the solder reflow process S8 is performed as shown in FIG.
  • Each step of the second stage in the method of the present embodiment is performed when the thickness of the solder 14 is insufficient for the metal core 13, and as shown in FIG.
  • the adhesive is applied again to the solder bump formed in the step in the adhesive treatment step S9.
  • a post-treatment step S11 is performed after a solder particle attachment step S10, and solder particles 12 are attached only to the pad electrode portion as shown in FIG. 9 (b).
  • a solder reflow process S13 is performed through a flux application process S12 to form a solder bump 10 as shown in FIG. 9 (c).
  • the second step is repeated.
  • the solder bumps 10 are completed in the first steps S1 to S8, the second steps S9 to S13 can be omitted.
  • a method of interposing the metal core 13 in the solder bump 10 As described above, a method of mixing the metal core 13 inside the solder particles 12, and a method of mixing the solder particles 12 and the metal core 1
  • the method of mixing and supplying the method of performing both of the above methods simultaneously, the method of mixing and supplying the solder particles in which the metal core 13 is mixed and the solder particles in which the metal core 13 is not mixed are further provided. There are various methods such as a method of separately supplying the metal core 13 and the solder particles 12.
  • the method of separately supplying the metal core 13 and the solder particles 12 is shown in a process diagram as shown in FIG. 10, and in FIG.
  • the attaching step S5 becomes a metal core attaching step S5 for attaching only the metal core, and accordingly, the flux applying step S7 and the solder reflow step S8 are omitted.
  • FIG. 11 is a process chart of the method of this embodiment
  • FIGS. 12 (a) to 12 (e) are cross-sectional views of the electrode portion during a main process.
  • the upper layer of the solder bump is formed by high-temperature melting solder, and then the outer layer of the solder bump is formed by low-temperature melting solder.
  • an adhesive treatment step S14 for applying the adhesive 4 is performed.
  • a post-processing step S16 is performed after a high-temperature solder particle attaching step S15, and the high-temperature solder particles 12a are attached only to the adhesive 4 as shown in FIG. 12 (b).
  • an inner layer portion 14a of the solder bump is formed as shown in FIG. 12 (c) in a solder riff opening one step S18 through a flux applying step S17.
  • the adhesive treatment step 19 the adhesive 4 is applied to the outer periphery of the bump inner layer 14a made of the high-temperature molten solder, and the low-temperature solder paste adhesion step S20 and the post-treatment step S21 are performed again. .
  • the low-temperature melting solder 12b is attached only to the outer periphery of the bump inner layer 14a.
  • a solder riff opening one process S23 melts the outer layer portion 14b of the solder bump in a process S23 to complete the solder bump 14 as a whole.
  • solder bumps formed by the method of the fifth embodiment when the semiconductor element is mounted on the circuit board, only the outer layer portion 14 b made of low-temperature melting solder is melted, so that the inner layer portion 14 a Will function as a metal core.
  • the ratio of P bZS n is not limited to the above, and as a solder, not only P bZS n but also A gZS nZZ n, Z n / S n, S n / C u, S n / Various things such as Ag / B i and SnZIn can be applied.
  • the method according to this embodiment comprises a bump having a metal core 13 interposed between at least three pad electrodes or a high-temperature molten solder when the semiconductor element has three or more pad electrodes.
  • the inner layer portion 14a forms a solder bump interposed.
  • the semiconductor element 20 can be formed.
  • the semiconductor element and the circuit board can be kept parallel.
  • the metal core 13 is interposed between the solder bumps 14 located at the four corners as shown in FIG. In such a case, after the adhesive treatment steps S4 and S14, a metal core, solder particles containing a metal core, or high-temperature melting solder particles are attached to the four corner electrode pad portions. carry out.
  • the adhesive 21 decreases its adhesiveness due to light or heat. Things (e.g., as the adhesive the adhesiveness decreases by heat, Asahi Chemical Research Laboratory STRIPMASK # 4 4 8 T) With, Bruno, conveying from 0 Re' preparative 3 0 to Torei (not shown), Alignment can be automated.
  • the pallet 30 is made of a transparent material, and the pallet 30 is made of a transparent material. Light should be applied from below 30. If the adhesive 21 has a property of deteriorating the adhesiveness due to heat, a heater 40 is provided below the pallet 30 as shown in FIG. Let let 30 be heated.
  • the semiconductor element can be peeled off from the pallet 30 by a vacuum chuck 50 as shown in FIG. 16 and transported.
  • the present invention is not limited to the method of the embodiment described above, and various modifications can be made within the scope of the gist.
  • INDUSTRIAL APPLICABILITY The method for forming a bump of a semiconductor device of the present invention can be applied to the formation of a bump of a TAB type semiconductor device in addition to the flip chip method.

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  • Physics & Mathematics (AREA)
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  • Electrodes Of Semiconductors (AREA)

Abstract

A method for forming a bump of a semiconductor device including an adhesive applying step of applying an adhesive to a pad electrode of a semiconductor device, a solder grain attaching step of attaching one or more solder grains to the portion of the pad electrode where the adhesive is applied, and a solder melting step of forming a bump by melting the solder grains. In the solder melting step, a metallic core is put in the bump. Therefore, a semiconductor device where a highly reliable bump is formed is obtained through simple steps.

Description

¾g 糸田 半導体素子のバンプ形成方法 発明の背景  ¾g Itoda Method for forming bumps on semiconductor devices Background of the invention
[技術分野]  [Technical field]
この発明は、 フリ ップチップ方式等の半導体素子において、 パッ ド電極上に形 成されるバンプの形成方法に関する。  The present invention relates to a method for forming a bump formed on a pad electrode in a flip-chip type semiconductor device or the like.
[背景技術] [Background technology]
ボンディ ングをフリ ップチップ方式で行なう半導体素子にあってはパッ ド電極 上にはんだバンプが形成してある。 このはんだバンプの形成方法としては、 蒸着 法， 電解メツキ法， スタッ ドバンプ法等が従来より採用されているが、 蒸着法は 最近のウェハーの大口径化、 バンプピッチや形状の細密化に対して精度に問題が あり、 またスタツ ドバンプ法はコストが高いために試作的にのみ使われており、 量産的には近年、 電解メツキ法が蒸着法に変わって主流になりつつある。  In a semiconductor device that performs bonding by the flip chip method, solder bumps are formed on pad electrodes. As a method for forming the solder bumps, a vapor deposition method, an electrolytic plating method, a stud bump method, and the like have been conventionally used. However, the vapor deposition method has recently been used to increase the diameter of a wafer and to reduce the bump pitch and shape. There are problems with accuracy, and the stud bump method is used only on a trial basis because of its high cost. For mass production, in recent years, the electrolytic plating method has become mainstream instead of the vapor deposition method.
第 1 7図は電解メ ツキ法で形成した従来のバンプを示す図である。  FIG. 17 is a view showing a conventional bump formed by an electrolytic plating method.
同図において、 1はウェハ一、 2はアルミニウムのパッ ド電極、 3はパッシ ベ一シヨン膜、 1 0 0は電解メ ツキバンプで、 1 0 1は下地金属膜、 1 0 2は銅 コア、 1 0 3ははんだバンプである。  In the figure, 1 is a wafer, 2 is an aluminum pad electrode, 3 is a passivation film, 100 is an electrolytic plating bump, 101 is a base metal film, 102 is a copper core, and 1 is a copper core. 03 is a solder bump.
このバンプにおいては、 半導体素子のパッ ド電極と電気接続の信頼性を確保す るため、 ウェハ一 1上に真空蒸着法でアルミニウム、 クロム、 銅を蒸着して下地 金属膜 1 0 1を形成する。 その後、 メツキレジストを塗布し、 該メツキレジスト の所定部分を開口してアルミニウムのパッ ド電極部 2上の下地金属膜 1 0 1を露 出させ、 下地金属膜 1 0 1を共通電極として銅の電解メ ツキを行なって銅コア 1 0 2を形成し、 その後はんだの電解メツキを行なう。 次いで、 メ ツキレジスト を剥離し、 バンプ部の下地金属膜 1 0 1を残した状態で他の下地金属膜をエッチ ングし、 フラックスを塗布して窒素雰囲気のリフロ一炉ではんだを溶融して電解 メ ツキバンプ 1 0 0を完成させている。 In this bump, aluminum, chromium, and copper are vapor-deposited on the wafer 11 by vacuum deposition to form an underlying metal film 101 in order to ensure reliability of the electrical connection between the pad electrode of the semiconductor element and the electrical connection. . Thereafter, a plating resist is applied, a predetermined portion of the plating resist is opened, and the underlying metal film 101 on the aluminum pad electrode portion 2 is exposed, and copper is used as the underlying metal film 101 as a common electrode. An electrolytic plating is performed to form a copper core 102, and then an electrolytic plating of the solder is performed. Next, the mask resist is peeled off, and the other underlying metal film is etched while the underlying metal film 101 of the bump portion is left. Then, a flux is applied, and the solder is melted in a reflow oven in a nitrogen atmosphere to complete the electrolytic plating bump 100.
しかしながら、 この電解メツキ法によるはんだバンプの形成にも次のような問 題がある。  However, the formation of solder bumps by the electrolytic plating method has the following problems.
第 1に、 フォ 卜レジストの形成工程、 下地金属膜の形成工程で使用する装置が 高額でしかも取り扱うウェハーのサイズが限定されるため、 ウェハーサイズが違 うと切り替えに時間がかかったり、 仕様外のサイズを扱うことができなかった。 このため、 この方法ではコスト高になるとともに、 ゥヱハ一でないチップ単位の ンプ形成が不可能であつた。  First, since the equipment used in the photoresist formation process and the base metal film formation process is expensive and the size of the wafer to be handled is limited, if the wafer size is different, it takes a long time to switch or out of specification. Couldn't handle size. For this reason, this method not only increases the cost but also makes it impossible to form a non-pumped chip.
また第 2に、 はんだバンプを基板にボンディングする際、 はんだバンプが潰れ て半導体素子の側面とショートしてしまうことを防止するため、 約 2 0 /z mの銅 コアを下地金属膜にメツキしている。 このため、 銅が剛体でしかも下地金属膜と 強固に密着してしまうことから、 チップサイズが大型になるにつれて加熱、 冷却 の温度変化が加わると、 銅とシリコン基板の線膨張係数の違いにより、 銅コア下 部に応力を与え、 界面剥離して接続が切れたり、 シリコンにクラックが入ったり するなどして、 信頼性に問題があった。  Second, when bonding the solder bumps to the substrate, a copper core of about 20 / zm is plated on the underlying metal film to prevent the solder bumps from crushing and shorting to the side of the semiconductor element. I have. For this reason, copper is a rigid body and firmly adheres to the underlying metal film.When the chip size increases, the temperature changes of heating and cooling increase, and the difference in the linear expansion coefficient between copper and the silicon substrate causes Stress was applied to the lower part of the copper core, causing interfacial delamination, disconnection, and cracking of silicon, leading to reliability problems.
さらに第 3に、 下地金属膜のエッチング工程があり、 例えば下地金属膜として アルミニウム， クロム， 銅を使用した場合、 鉛と錫をエッチングせずに下地金属 膜をエッチングすることは困難であつたし、 エッチング量， 時間の管理も難し かった。  Third, there is an underlying metal film etching process. For example, when aluminum, chromium, or copper is used as the underlying metal film, it is difficult to etch the underlying metal film without etching lead and tin. Also, it was difficult to control the etching amount and time.
一方、 最近において、 メツキによらずに電子部品のリードや、 回路基板の露出 パターン上にはんだを塗布する技術が特開平 0 7 - 0 7 4 4 5 9号公報で提案さ れている。  On the other hand, recently, a technique of applying solder to the leads of an electronic component or an exposed pattern of a circuit board without depending on the plating has been proposed in Japanese Patent Application Laid-Open No. 07-074549.
し力、し、 この技術を半導体素子のパッ ド電極のバンプ形成に応用する具体的な 技術についてはまだ開発されていない。 さらに、 この技術によってバンプを形成 する際、 基板へのボンディング時にはんだバンプが潰れないようにする技術を付 加する点についても一切開示がなされていない。  No specific technology has yet been developed to apply this technology to the formation of bumps on semiconductor device pad electrodes. Furthermore, there is no disclosure of adding a technique for preventing solder bumps from being crushed during bonding to a substrate when forming bumps using this technique.
従って、 本発明は上記の諸事情に鑑みてなされたものであり、 簡単な工程で信 頼性の高い製品を得ることのできる半導体素子のバンプ形成方法の提供を目的と している。 Therefore, the present invention has been made in view of the above circumstances, and requires only a simple process. The purpose of the present invention is to provide a method for forming bumps of a semiconductor device that can obtain a highly reliable product.
[発明の開示] [Disclosure of the Invention]
上記目的を達成するため、 本発明は、 半導体素子のパッ ド電極上に無電解メッ キを行なうメツキ工程、 無電解メツキ部分に粘着剤を付与する粘着剤処理工程、 粘着剤を付与した部分に一又は二以上のはんだ粒子を付着させるはんだ粒子付着 工程、 及びはんだ粒子を溶融してバンプを形成するはんだ溶融工程とを有する方 法としてある。  In order to achieve the above object, the present invention provides a plating step of performing electroless plating on a pad electrode of a semiconductor element, an adhesive treatment step of applying an adhesive to an electroless plating portion, and a step of applying an adhesive to a portion provided with an adhesive. The method includes a solder particle attaching step of attaching one or more solder particles, and a solder melting step of melting the solder particles to form a bump.
ここで、 前記はんだ粒子を溶融してバンプを形成する工程において、 バンプ内 に金属コアを介在させ、 また、 この金厲コアを、 あらかじめ一部又は全部のはん だ粒子内に少なくとも一つ混入させておくことにより、 はんだ溶融工程時にバン プ内に介在させる方法としてある。  Here, in the step of melting the solder particles to form a bump, a metal core is interposed in the bump, and at least one of the gold core is previously mixed in some or all of the solder particles. By using this method, it is a method of interposing in the bump during the solder melting process.
また、 本発明では、 前記金属コアを、 はんだ粒子と混合させて粘着剤を付与し た部分に付着させることにより、 はんだ溶融工程時にバンプ内に介在させる方法 としてもよく、 さらに、 前記金属コアを、 はんだ粒子付着工程と別個独立した粘 着剤処理工程及び金属コア付着工程で電極部分に付着させることにより、 はんだ 溶融工程時にバンプ内に介在させる方法としてもよい。  Further, in the present invention, the metal core may be mixed with solder particles and adhered to a portion provided with an adhesive, so that the metal core is interposed in a bump during a solder melting step. Alternatively, a method may be adopted in which the adhesive is applied to the electrode portion in a bonding agent treatment step and a metal core attachment step that are independent and independent of the solder particle attachment step, so as to be interposed in the bump during the solder melting step.
また、 本発明は、 拈着剤処理工程とはんだ粒子付着工程及びはんだ溶融工程 力  In addition, the present invention relates to a process for treating a bridging agent, a process for attaching solder particles, and a process for melting solder.
高温はんだ粘着剤処理工程と高温はんだ拉子付着工程及び高温はんだ溶融工程、 並びに、 低温はんだ粘着剤処理工程と低温はんだ粒子付着工程及び低温はんだ溶 融工程からなる方法としてある。 It consists of a high-temperature solder adhesive treatment step, a high-temperature solder paste adhesion step and a high-temperature solder melting step, and a low-temperature solder adhesive treatment step, a low-temperature solder particle adhesion step and a low-temperature solder fusion step.
この場合において、 高温はんだ粘着剤処理工程と高温はんだ粒子付着工程及び 高温はんだ溶融工程を行なった後に、 低温はんだ粘着剤処理工程と低温はんだ粒 子付着工程及び低温はんだ溶融工程を行なうことが好ましく、 このようにすると 高温はんだが金属コアとして機能する。  In this case, it is preferable to perform the low-temperature solder adhesive treatment step, the low-temperature solder particle adhesion step, and the low-temperature solder melting step after performing the high-temperature solder adhesive treatment step, the high-temperature solder particle adhesion step, and the high-temperature solder melting step, In this case, the high-temperature solder functions as a metal core.
以上のように本発明によれば、 簡単な工程で信頼性の高い半導体素子を得るこ とができるとともに、 高価な装置を必要とすることもなく、 また、 ウェハ一サイ ズの変更にも容易に対応することができる。 As described above, according to the present invention, a highly reliable semiconductor device can be obtained by a simple process. It does not require expensive equipment and can easily respond to changes in wafer size.
また、 無電解メツキによってアルミニウム上に選択的にメツキを行なっている ので、 電解メツキのようにウェハ一上に共通電極を形成する必要がなくなり、 製 造工程を簡素化できるとともに、 低コスト化を図ることができる。 図面の簡単な説明 第 1図は、 本発明の半導体素子のバンプ形成方法の第 1実施形態を示す工程図 である。  In addition, since electroless plating is used to selectively perform plating on aluminum, there is no need to form a common electrode on the wafer as with electrolytic plating, which simplifies the manufacturing process and reduces costs. Can be planned. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process chart showing a first embodiment of a bump forming method for a semiconductor device according to the present invention.
第 2図 （ a ) 〜 （ f ) は、 同じく第 1実施形態における主要工程の電極部断面 図である。  2 (a) to 2 (f) are cross-sectional views of a main step of the first embodiment in the same manner.
第 3図は、 本発明の半導体素子のバンプ形成方法の第 2実施形態で形成したバ ンプの断面図である。  FIG. 3 is a sectional view of a bump formed by a second embodiment of the method for forming a bump of a semiconductor device of the present invention.
第 4図 （a ) , ( b ) は、 本発明の半導体素子のバンプ形成方法の第 3実施形 態における主要工程の電極部断面図である。  FIGS. 4 (a) and 4 (b) are cross-sectional views of an electrode portion in main steps in a third embodiment of the bump forming method for a semiconductor device according to the present invention.
第 5図は、 第 2実施形態の方法でバンプを形成した半導体素子を、 回路基板に ボンディングした状態の断面図である。  FIG. 5 is a cross-sectional view showing a state in which a semiconductor element having bumps formed by the method of the second embodiment is bonded to a circuit board.
第 6図は、 第 3実施形態の方法ではんだバンプ内に三個の金属コアを介在させ た状態の断面図である。  FIG. 6 is a cross-sectional view showing a state in which three metal cores are interposed in a solder bump by the method of the third embodiment.
第 7図は、 本発明の半導体素子のバンプ形成方法の第 4実施形態を示す工程図 である。  FIG. 7 is a process chart showing a fourth embodiment of the method for forming a bump of a semiconductor device of the present invention.
第 8図 （a ) 〜 （d ) は、 同じく第 4実施形態の第一段階における主要工程の 電極部断面図である。  FIGS. 8 (a) to 8 (d) are cross-sectional views of an electrode part of a main process in the first stage of the fourth embodiment.
第 9図 （a ) 〜 （c ) は、 同じく第 4実施形態の第二段階における主要工程の 電極部断面図である。  FIGS. 9 (a) to 9 (c) are cross-sectional views of an electrode part of a main process in the second stage of the fourth embodiment.
第 1 0図は、 本発明の半導体素子のバンプ形成方法の金属コアを用いた他の実 施形態を示す工程図である。 第 1 1図は、 本発明の半導体素子のバンプ形成方法の第 5実施形態を示す工程 図である。 FIG. 10 is a process chart showing another embodiment using a metal core in the bump forming method for a semiconductor device of the present invention. FIG. 11 is a process diagram showing a fifth embodiment of the bump forming method for a semiconductor device of the present invention.
第 1 2図 （a ) 〜 （e ) は、 同じく第 5実施形態における主要工程の電極部断 面図である。  FIGS. 12 (a) to 12 (e) are cross-sectional views of an electrode part in a main step in the same manner as in the fifth embodiment.
第 1 3図は、 本発明の半導体素子のバンプ形成方法によって、 少なくとも三個 のはんだバンプ内に金属コアを介在させた半導体素子の平面図である。  FIG. 13 is a plan view of a semiconductor device in which a metal core is interposed in at least three solder bumps by the bump forming method for a semiconductor device according to the present invention.
第 1 4図は、 本発明の半導体素子のバンプ形成方法の各実施形態で製造された 半導体素子の使用状態を示す平面図である。  FIG. 14 is a plan view showing a use state of a semiconductor element manufactured by each embodiment of the method for forming a bump of a semiconductor element of the present invention.
第 1 5図は、 本発明の半導体素子のバンプ形成方法の各実施形態で製造された 半導体素子の卜レイへの整列状態を説明するための断面図である。  FIG. 15 is a cross-sectional view for explaining an alignment state of a semiconductor element manufactured in each embodiment of the method for forming a bump of a semiconductor element of the present invention on a tray.
第 1 6図は、 本発明の半導体素子のバンプ形成方法の各実施形態で製造された 半導体素子のトレイへの整列状態を説明するための断面図である。  FIG. 16 is a cross-sectional view for explaining a state in which semiconductor elements manufactured in each embodiment of the method for forming bumps of a semiconductor element of the present invention are aligned on a tray.
第 1 7図は、 従来のはんだバンプの断面図である。 発明を実施するための最良の形態 本発明をより詳細に詳述するために、 添付の図面に従ってこれを説明する。 [第 1実施形態]  FIG. 17 is a cross-sectional view of a conventional solder bump. BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the accompanying drawings. [First Embodiment]
まず、 本発明の第 1実施形態を第 1図及び第 2図によって説明する。  First, a first embodiment of the present invention will be described with reference to FIGS.
第 1図は工程図、 第 2図 （a ) ~ ( f ) は主要工程における電極部の断面図を 示している。  FIG. 1 is a process diagram, and FIGS. 2 (a) to (f) are cross-sectional views of an electrode portion in a main process.
第 1図における前処理工程 S 1では、 第 2図 （a ) に示すようにウェハ一 1上 に完成された半導体素子のアルミニウムのパッ ド電極 2の酸化膜を除去する。 次いで、 活性化処理工程 S 2ではパッド電極 2上に選択的にニッケルを無電解 メツキするための活性化処理を行なう。 そして、 無電解ニッケルメツキ工程 S 3 では、 第 2図 （b ) に示すようにパッ ド電極 2上に金属としてのニッケル膜 1 1 を無電解メツキする。 なお、 3はパッシベーシヨン膜である。 In the pretreatment step S1 in FIG. 1, as shown in FIG. 2 (a), the oxide film of the aluminum pad electrode 2 of the semiconductor element completed on the wafer 11 is removed. Next, in an activation process step S2, an activation process for selectively electrolessly plating nickel on the pad electrode 2 is performed. Then, in the electroless nickel plating step S3, a nickel film 11 as a metal is electrolessly plated on the pad electrode 2 as shown in FIG. 2 (b). Reference numeral 3 denotes a passivation film.
次に、 粘着剤処理工程 S 4では、 第 2図 （ c ) に示すように、 ゥヱハ一1上に 露出している金属部分に選択的に粘着剤 4を付与するためウェハー 1を薬剤槽に 浸し、 かつ、 乾燥させる。  Next, in the pressure-sensitive adhesive treatment step S4, as shown in FIG. 2 (c), the wafer 1 is placed in a chemical tank in order to selectively apply the pressure-sensitive adhesive 4 to the metal portion exposed on the wafer 1 Soak and dry.
そして、 はんだ粒子付着工程 S 5では、 第 2図 （d ) に示すように、 はんだ粒 子 1 2をウェハ一 1上に振りかける。 本実施形態の場合、 はんだ粒子 1 2の直径 は約 1 0 0 / mである。  Then, in the solder particle attaching step S5, the solder particles 12 are sprinkled on the wafer 11, as shown in FIG. 2 (d). In the case of the present embodiment, the diameter of the solder particles 12 is about 100 / m.
その後、 後処理工程 S 6では、 はんだ拉子を電極部に仮接着させるための加熱 処理を行なった後、 第 2図 （e ) に示すように、 粘着剤 4を付与した部分以外に あるはんだ粒子 1 2を軽くブラッシングして除去する。 これにより、 粘着剤 4を 付与した部分にあるはんだ拉子 1 2のみが残る。  Then, in a post-processing step S6, after performing a heat treatment for temporarily bonding the solder pieces to the electrode portions, as shown in FIG. 2 (e), the solder existing in a portion other than the portion where the adhesive 4 is applied is provided. Lightly brush and remove particles 12. As a result, only the solder paste 12 at the portion where the adhesive 4 is applied remains.
このようにして、 ゥヱハー 1の金属部分にはんだ粒子 1 2を固定した後、 フ ラックス塗布工程 S 7でゥヱハー 1の表面上にフラックスを塗布し、 次いで、 は んだリフロー工程 S 8でリフロー炉の中を通すことにより、 第 2図 （ f ) に示す ように、 溶融したはんだ 1 4が表面張力でボール状に丸まる。 その後、 洗浄及び 乾燥を行なった後検査工程 S 9で検査を行ない、 ウェハ一上にはんだバンプ 1 0 を完成させる。  In this way, after the solder particles 12 are fixed to the metal part of the hearth 1, a flux is applied on the surface of the hearth 1 in a flux application step S 7, and then the reflow furnace S 8 is used in a solder reflow step S 8. As shown in Fig. 2 (f), the molten solder 14 is rolled into a ball by surface tension as shown in Fig. 2 (f). Then, after cleaning and drying, inspection is performed in an inspection step S9 to complete solder bumps 10 on the wafer.
なお、 はんだリフロー工程 S 8の後ではんだの膜厚が不足している場合は、 粘 着剤処理工程 S 4に戻り、 以降の工程を繰り返す。  If the thickness of the solder is insufficient after the solder reflow step S8, the process returns to the adhesive treatment step S4, and the subsequent steps are repeated.
本実施形態では、 はんだ拉子の直径を約 1 0 0 /i mとして一つの電極に一個の はんだ粒子を付着させるようにしたが、 これに限定されることなく、 例えば 5 0 / m以下の複数のはんだ拉子を付着させてもよい。  In the present embodiment, one solder particle is adhered to one electrode by setting the diameter of the solder to about 100 / im. However, the present invention is not limited to this. May be attached.
[第 2実施形態] [Second embodiment]
次に、 本発明の第 2実施形態について説明する。  Next, a second embodiment of the present invention will be described.
第 3図は第 2実施形態で形成したはんだバンプの断面図である。  FIG. 3 is a sectional view of the solder bump formed in the second embodiment.
本発明の第 2実施形態の方法は、 第 1図における活性化処理工程 S 2と無電解 二ッケルメッキエ程 S 3を省略した以外は第 1図における工程と同じ工程で形成 してあ O o The method of the second embodiment of the present invention is formed by the same steps as those in FIG. 1 except that the activation step S 2 and the electroless nickel plating step S 3 in FIG. 1 are omitted. Ooo
すなわち、 ウェハー 1の状態で前処理工程 S 1を行なった後、 直接粘着剤処理 工程 S 4を行なってパッ ド電極 2上に粘着層を形成し、 その後、 はんだ粒子付着 工程 S 5， 後処理工程 S 6 , フラックス塗布工程 S 7及びはんだリフ口一工程 S 8を行なって、 第 3図に示すような、 はんだバンプ 1 0を形成したものであ o  That is, after performing the pre-processing step S 1 in the state of the wafer 1, directly performing the adhesive processing step S 4 to form an adhesive layer on the pad electrode 2, and then performing the solder particle attaching step S 5, post-processing Step S 6, flux application step S 7 and solder riff opening one step S 8 are performed to form solder bumps 10 as shown in FIG. 3.
この実施形態のものはアルミニウム等のパッ ド電極金属に対する錫， 鉛の拡散 や金属間化合物等が許容できる場合に適用できる。  This embodiment can be applied when diffusion of tin or lead into a pad electrode metal such as aluminum or an intermetallic compound can be tolerated.
なお、 前記した活性化処理工程 S 2と無電解ニッケルメツキ工程 S 3を有する 第 1実施形態の方法と、 これら工程を有しない第 2実施形態の方法は、 以下で説 明する各実施形態に選択的に適用することができる。 したがって、 以下の各実施 形態の説明で、 第 1又は第 2の実施形態方法の一方を用いている場合であって も、 この実施形態の方法に限定されるものではない。  The method of the first embodiment having the above-described activation treatment step S2 and the electroless nickel plating step S3, and the method of the second embodiment not having these steps are described in each of the embodiments described below. Can be selectively applied. Therefore, even if one of the methods of the first and second embodiments is used in the following description of each embodiment, the present invention is not limited to the method of this embodiment.
また、 無電解メツキは、 ニッケルに限定されるものではなく、 例えば金， 銅， クロムなどのメツキでもよく、 さらには、 それらの多層あるいは混合メツキであ つてもよい。  Further, the electroless plating is not limited to nickel, but may be plating such as gold, copper, chromium, or the like, or may be a multilayer or mixed plating thereof.
[第 3実施形態] [Third embodiment]
次に、 本発明の第 3実施形態について説明する。  Next, a third embodiment of the present invention will be described.
第 4図は、 第 3実施形態の主要工程における電極部の断面図を示している。 この第 3実施形態の方法も、 第 1図に示す工程にもとづいてバンプを形成する が、 この実施形態においては、 第 4図 （a ) に示すように、 ゥヱハー 1上に振り かけるはんだ粒子 1 2の内部に銅等の金属からなるボール状の金属コア 1 3を混 入させてある。  FIG. 4 shows a cross-sectional view of an electrode part in a main step of the third embodiment. In the method of the third embodiment, bumps are formed based on the steps shown in FIG. 1. In this embodiment, as shown in FIG. 4 (a), the solder particles 1 2, a ball-shaped metal core 13 made of a metal such as copper is mixed.
この実施形態では、 金属コア 1 3の直径は約 2 0 m、 はんだ粒子 1 2の直径 を約 1 0 0 mとしてある。 このように、 金属コア 1 3の直径をはんだ粒子 1 2 の膜厚 （本実施形態の膜厚は約 3 0 ^ m ) よりも小さくすると、 金属コア 1 3に 対するはんだの量を十分確保することができ、 あとではんだを補充する必要がな くなる。 In this embodiment, the diameter of the metal core 13 is about 20 m, and the diameter of the solder particles 12 is about 100 m. As described above, when the diameter of the metal core 13 is smaller than the thickness of the solder particles 12 (the thickness of the present embodiment is about 30 ^ m), a sufficient amount of solder for the metal core 13 is secured. No need to refill the solder later It becomes.
このようにして、 ゥヱハー 1の金属部分に金属コア 1 3入りのはんだ粒子 1 2 を粘着剤 1 4で固定した後、 フラックス塗布工程 S 7でゥヱハー 1の表面上にフ ラックスを塗布して、 はんだリフロー工程 S 8でリフロー炉の中を通すことによ り、 金属コア 1 3を介在した状態で溶融したはんだが表面張力でボール状 1 4に 丸まり、 第 4図 （b ) に示すようはんだバンプ 1 0を形成する。  In this way, the solder particles 12 containing the metal core 13 are fixed to the metal part of the hearth 1 with the adhesive 14, and then the flux is applied on the surface of the hearth 1 in the flux application step S7. Solder reflow process By passing through the reflow furnace in step S8, the molten solder with the metal core 13 interposed is rounded into a ball shape 14 by surface tension, and the solder is soldered as shown in Fig. 4 (b). The bump 10 is formed.
なお、 はんだ粒子として金属コア 1 3の混入したものを用いた場合であって も、 はんだリフ口一工程 S 8の後ではんだの膜厚が不足しているときは、 粘着剤 処理工程 S 4に戻り、 以降の工程を繰り返す。 し力、し、 この場合、 はんだ粒子 1 2としては金属コア入りのものを用いる必要はないし、 またはんだ粒子の直径は 必要膜厚に応じて決めればよい。  Even when the solder particles mixed with the metal core 13 are used, if the film thickness of the solder is insufficient after the solder riff opening one step S8, the adhesive treatment step S4 And repeat the subsequent steps. In this case, it is not necessary to use the solder particles 12 containing a metal core, and the diameter of the solder particles may be determined according to the required film thickness.
第 5図は、 第 3実施形態の方法でバンプを形成した半導体素子 1 aを、 回路基 板 2 0 0の金メツキされた接続電極 2 0 2にボンディングした例で、 金属コア 1 3が半導体素子 1 aと基板 2 0 0のスぺ一ザとして機能し、 しかも金属コア 1 3 がはんだ 1 4 aに包まれており直接ニッケル膜 1 1に密着していないので、 応力 を緩和し信頼性の優れた、 しかもボンディングの容易な接続を得られる。  FIG. 5 shows an example in which a semiconductor element 1a on which a bump is formed by the method of the third embodiment is bonded to a gold-plated connection electrode 202 of a circuit board 200. It functions as a spacer between the element 1a and the substrate 200, and since the metal core 13 is wrapped in the solder 14a and does not directly adhere to the nickel film 11, the stress is reduced and the reliability is reduced. Excellent connection and easy bonding can be obtained.
なお、 はんだ粒子 1 2の内部に複数個の金属コア 1 3を混入させておくことも でき、 このようにすると、 第 6図に示すようなはんだバンプ 1 4を得ることがで きる。  In addition, a plurality of metal cores 13 can be mixed in the inside of the solder particles 12, and in this case, a solder bump 14 as shown in FIG. 6 can be obtained.
[第 4実施形態] [Fourth embodiment]
次に、 本発明の第 4実施形態について説明する。  Next, a fourth embodiment of the present invention will be described.
第 7図， 第 8図及び第 9図は、 本発明の第 4実施形態を示すものである。  FIGS. 7, 8, and 9 show a fourth embodiment of the present invention.
第 7図は、 この実施形態方法の工程図であり、 第 8図 （a ) 〜 （d ) は第一段 階における主要工程時の電極部の断面図を示し、 第 9図 （a ) 〜 （c ) は第二段 階における主要工程の電極部の断面図を示している。  FIG. 7 is a process chart of the method of this embodiment, and FIGS. 8 (a) to (d) show cross-sectional views of the electrode part at the time of the main process in the first stage, and FIGS. (C) shows a cross-sectional view of the electrode part of the main process in the second stage.
本実施形態の方法は、 はんだ粒子に金属コアを混合させて粘着剤に付着させは んだリフローする第一段階の工程 S 1 〜 S 8とはんだ粒子のみを粘着剤に付着さ せてはんだリフローする第二段階の工程 S 9〜S 1 4を有している。 In the method of the present embodiment, the first step S1 to S8 in which the metal core is mixed with the solder particles and attached to the adhesive and the solder is reflowed, and only the solder particles are attached to the adhesive. And the second step S9 to S14 for the solder reflow.
第一段階では、 第 8図 （a ) に示すように、 粘着剤処理工程 S 4を行ない、 そ の後、 第 8図 （b ) に示すように、 粒子付着工程 S 5においてはんだ粒子 1 2と 金属コア 1 3を混合して粘着剤 4に付着させる。 この場合におけるはんだ粒子 1 2と金属コア 1 3の混合の割合はチップ単位のバンプ数によるが、 ボンディング したときにチップがほぼ平行となるような割合とする。 その後、 第 8図 （c ) に 示すように、 パッ ド電極部以外からはんだ拉子 1 2と金属コア 1 3を除去した後 処理工程 S 6を行ない、 次いでフラックス塗布工程 S 7を経て第 8図 （d ) に示 すようにはんだリフロー工程 S 8を行なう。  In the first stage, an adhesive treatment step S4 is performed as shown in FIG. 8 (a), and then, as shown in FIG. 8 (b), the solder particles 12 And the metal core 13 are mixed and adhered to the adhesive 4. In this case, the proportion of the mixture of the solder particles 12 and the metal cores 13 depends on the number of bumps per chip, but should be such that the chips are substantially parallel when bonded. Thereafter, as shown in FIG. 8 (c), after removing the solder pieces 12 and the metal core 13 from portions other than the pad electrode portion, a post-processing step S6 is performed, and then a flux coating step S7 is performed. The solder reflow process S8 is performed as shown in FIG.
本実施形態方法における第二段階の各工程は、 金属コア 1 3に対してはんだ 1 4の膜厚が不足している場合に行なわれ、 第 9図 （a ) に示すように、 第一段階 の工程で形成されたはんだバンプに粘着剤処理工程 S 9で再度粘着剤を付与す る。 その後、 はんだ粒子付着工程 S 1 0を経て後処理工程 S 1 1を行ない、 第 9 図 （b ) に示すようにパッ ド電極部のみにはんだ粒子 1 2を付着させる。 その後 さらに、 フラックス塗布工程 S 1 2を経てはんだリフロー工程 S 1 3を行ない第 9図 （c ) に示すようなはんだバンプ 1 0を形成する。  Each step of the second stage in the method of the present embodiment is performed when the thickness of the solder 14 is insufficient for the metal core 13, and as shown in FIG. The adhesive is applied again to the solder bump formed in the step in the adhesive treatment step S9. Thereafter, a post-treatment step S11 is performed after a solder particle attachment step S10, and solder particles 12 are attached only to the pad electrode portion as shown in FIG. 9 (b). Thereafter, a solder reflow process S13 is performed through a flux application process S12 to form a solder bump 10 as shown in FIG. 9 (c).
この第 4実施形態の方法においても、 第二段階の工程一回だけでははんだが足 りないときは、 第二段階の工程を繰り返す。 また逆に、 第一段階の各工程 S l〜 S 8ではんだバンプ 1 0が完成するときは、 第二段階の各工程 S 9〜S 1 3を省 略することもできる。  Also in the method of the fourth embodiment, when the solder in the second step alone is not enough, the second step is repeated. Conversely, when the solder bumps 10 are completed in the first steps S1 to S8, the second steps S9 to S13 can be omitted.
はんだバンプ 1 0内に金属コア 1 3を介在させる方法としては、 前記したよう に、 はんだ粒子 1 2の内部に金属コア 1 3を混入させておく方法、 及びはんだ粒 子 1 2と金属コア 1 3を混合して供給する方法のほか、 前記両方法を同時に行な う方法、 金属コア 1 3を混入してあるはんだ粒子と混入していないはんだ粒子を 混合して供給する方法、 さらには、 金属コア 1 3とはんだ粒子 1 2を別個に供給 する方法など、 種々の方法がある。  As a method of interposing the metal core 13 in the solder bump 10, as described above, a method of mixing the metal core 13 inside the solder particles 12, and a method of mixing the solder particles 12 and the metal core 1 In addition to the method of mixing and supplying, the method of performing both of the above methods simultaneously, the method of mixing and supplying the solder particles in which the metal core 13 is mixed and the solder particles in which the metal core 13 is not mixed are further provided. There are various methods such as a method of separately supplying the metal core 13 and the solder particles 12.
このうち、 金属コア 1 3とはんだ粒子 1 2を別個に供給する方法を、 工程図で 表わすと第 1 0図に示すようになり、 第 7図における、 はんだ粒子， 金属コア付 着工程 S 5が、 金属コアのみを付着する金属コア付着工程 S 5となるとともに、 これにともなって、 フラックス塗布工程 S 7及びはんだリフロー工程 S 8が省略 される。 Of these, the method of separately supplying the metal core 13 and the solder particles 12 is shown in a process diagram as shown in FIG. 10, and in FIG. The attaching step S5 becomes a metal core attaching step S5 for attaching only the metal core, and accordingly, the flux applying step S7 and the solder reflow step S8 are omitted.
[第 5実施形態] [Fifth Embodiment]
次に、 本発明の第 5実施形態について説明する。  Next, a fifth embodiment of the present invention will be described.
第 1 1図はこの実施形態方法の工程図であり、 第 1 2図 （a ) 〜 （ e ) は主要 工程時における電極部の断面図である。  FIG. 11 is a process chart of the method of this embodiment, and FIGS. 12 (a) to 12 (e) are cross-sectional views of the electrode portion during a main process.
本実施形態の方法は、 高温溶融はんだによってはんだバンプの內層を形成し、 その後低温溶融はんだによってはんだバンプの外層を形成している。  According to the method of the present embodiment, the upper layer of the solder bump is formed by high-temperature melting solder, and then the outer layer of the solder bump is formed by low-temperature melting solder.
前記した第 1図あるいは第 7図に示す工程と同様の、 前処理工程 S I 1 , 活性 化処理工程 S 1 2 , 無電解ニッケル工程 S 1 3を行なった後、 第 1 2図 （a ) に 示すように粘着剤 4を付与する粘着剤処理工程 S 1 4を行なう。  After performing the pre-treatment step SI 1, the activation treatment step S 12, and the electroless nickel step S 13 in the same manner as the steps shown in FIG. 1 or FIG. 7 described above, FIG. As shown, an adhesive treatment step S14 for applying the adhesive 4 is performed.
その後、 高温はんだ粒子付着工程 S 1 5を経て後処理工程 S 1 6を行ない、 第 1 2図 （b ) に示すように粘着剤 4の部分にのみ高温はんだ粒子 1 2 aを付着さ せる。  Thereafter, a post-processing step S16 is performed after a high-temperature solder particle attaching step S15, and the high-temperature solder particles 12a are attached only to the adhesive 4 as shown in FIG. 12 (b).
次いで、 フラックス塗布工程 S 1 7を経てはんだリフ口一工程 S 1 8で第 1 2 図 （ c ) に示すようにはんだバンプの内層部分 1 4 aを形成する。  Next, an inner layer portion 14a of the solder bump is formed as shown in FIG. 12 (c) in a solder riff opening one step S18 through a flux applying step S17.
その後、 再び粘着剤処理工程 1 9で、 高温溶融はんだからなるバンプ内層 1 4 aの外周に粘着剤 4を付与するとともに、 低温はんだ拉子付着工程 S 2 0及び後 処理工程 S 2 1を行なう。 これにより、 第 1 2図 （d ) に示すようにバンプ内層 1 4 aの外周のみに低温溶融はんだ 1 2 bが付着される。  Then, in the adhesive treatment step 19, the adhesive 4 is applied to the outer periphery of the bump inner layer 14a made of the high-temperature molten solder, and the low-temperature solder paste adhesion step S20 and the post-treatment step S21 are performed again. . As a result, as shown in FIG. 12 (d), the low-temperature melting solder 12b is attached only to the outer periphery of the bump inner layer 14a.
次いで、 フラックス塗布工程 S 2 2を経てはんだリフ口一工程 S 2 3ではんだ バンプの外層部分 1 4 bを溶融形成し、 全体としてはんだバンプ 1 4を完成させ る  Then, through a flux application process S22, a solder riff opening one process S23 melts the outer layer portion 14b of the solder bump in a process S23 to complete the solder bump 14 as a whole.
この第 5実施形態の方法で形成したはんだバンプによれば、 半導体素子を回路 基板上に実装するときは、 低温溶融はんだからなる外層部分 1 4 bのみを溶かし て行なうので、 内層部分 1 4 aは金属コアとして機能することになる。 なお、 高温溶融はんだ粒子としては、 例えば、 P bZS n = 95Z5のものを 用い、 低温溶融はんだ粒子としては、 例えば、 PbZSn = 40Z60のものを 用いる。 P bZS nの比率は前記のものに限定されるものではなく、 また、 はん だとしては P bZS nだけでなく A gZS nZZ n, Z n/S n, S n/C u, S n/A g/B i , S nZ I n等種々のものを適用できる。 According to the solder bumps formed by the method of the fifth embodiment, when the semiconductor element is mounted on the circuit board, only the outer layer portion 14 b made of low-temperature melting solder is melted, so that the inner layer portion 14 a Will function as a metal core. As the high-temperature melting solder particles, for example, PbZSn = 95Z5 is used, and as the low-temperature melting solder particles, for example, PbZSn = 40Z60 is used. The ratio of P bZS n is not limited to the above, and as a solder, not only P bZS n but also A gZS nZZ n, Z n / S n, S n / C u, S n / Various things such as Ag / B i and SnZIn can be applied.
[第 6実施形態] [Sixth embodiment]
次に、 本発明の第 6実施形態について説明する。  Next, a sixth embodiment of the present invention will be described.
この実施形態の方法は、 半導体素子が三箇所以上にパッ ド電極を有する場合に おいて、 少なくとも三箇所のパッ ド電極に金属コア 13を介在させたバンプ、 あ るいは、 高温溶融はんだからなる内層部分 14 aが介在するはんだバンプを形成 するものである。  The method according to this embodiment comprises a bump having a metal core 13 interposed between at least three pad electrodes or a high-temperature molten solder when the semiconductor element has three or more pad electrodes. The inner layer portion 14a forms a solder bump interposed.
例えば、 第 13図に示すような、 外周部分に多数のはんだバンプ 14を有する 半導体素子 20において、 これらはんだバンプ 14のうちの少なくとも三つに金 属コアを介在させておくと、 半導体素子 20を回路基板に実装する際、 半導体素 子と回路基板を平行に保つことができる。  For example, as shown in FIG. 13, in a semiconductor element 20 having a large number of solder bumps 14 on the outer peripheral portion, if a metal core is interposed in at least three of these solder bumps 14, the semiconductor element 20 can be formed. When mounting on a circuit board, the semiconductor element and the circuit board can be kept parallel.
なお、 第 13図に示す半導体素子において、 第 13図に示すように、 四隅に位 置するはんだバンプ 14に金属コア 13を介在させておくことが最も好ましい。 このような場合は、 粘着剤処理工程 S 4, S 14の後、 四隅の電極パッ ド部分に 金属コア， 金属コア入りはんだ粒子あるいは高温溶融はんだ粒子を付着させ、 そ の後前記した各工程を実施する。  In the semiconductor device shown in FIG. 13, it is most preferable that the metal core 13 is interposed between the solder bumps 14 located at the four corners as shown in FIG. In such a case, after the adhesive treatment steps S4 and S14, a metal core, solder particles containing a metal core, or high-temperature melting solder particles are attached to the four corner electrode pad portions. carry out.
前記した各実施形態の方法は、 半導体素子がウェハー状の場合あるいはチップ 状の場合のいずれにも適用することができる。  The method of each of the above-described embodiments can be applied to either a case where the semiconductor element is a wafer or a case where the semiconductor element is a chip.
また、 前記した各実施形態の方法ではんだバンプを形成した半導体素子 20 カ 、 第 14図に示すように、 パレツト 30上に接着剤 21で保持されている場合 には、 実装等に際し、 半導体素子をパレット 30上から剥離して卜レイ上に整列 させることがある。  Further, in the case where 20 semiconductor elements having solder bumps formed by the method of each of the above-described embodiments are held on a pallet 30 with an adhesive 21 as shown in FIG. May be separated from the pallet 30 and aligned on the tray.
このような場合、 接着剤 21として、 光あるいは熱によって接着性が低下する もの （例えば、 熱によって接着性が低下する接着剤としては、 アサヒ化学研究所 製 S T R I P M A S K # 4 4 8 T ) を用いると、 ノ、0レッ ト 3 0からトレィ (図示せず） への搬送， 整列を自動化することができる。 In such a case, the adhesive 21 decreases its adhesiveness due to light or heat. Things (e.g., as the adhesive the adhesiveness decreases by heat, Asahi Chemical Research Laboratory STRIPMASK # 4 4 8 T) With, Bruno, conveying from 0 Re' preparative 3 0 to Torei (not shown), Alignment can be automated.
具体的には、 接着剤 2 1が光で接着性が低下する性質を有するものである場合 には、 第 1 5図に示すように、 パレツ ト 3 0を透明な材料で製作し、 パレツ ト 3 0の下方から光をあてるようにする。 また、 接着剤 2 1が熱で接着性が低下する 性質を有するものである場合には、 第 1 6図に示すように、 パレツ 卜 3 0の下部 にヒータ 4 0を設けて、 ハ。レツ ト 3 0を加熱するようにする。  Specifically, when the adhesive 21 has a property of deteriorating adhesiveness due to light, as shown in FIG. 15, the pallet 30 is made of a transparent material, and the pallet 30 is made of a transparent material. Light should be applied from below 30. If the adhesive 21 has a property of deteriorating the adhesiveness due to heat, a heater 40 is provided below the pallet 30 as shown in FIG. Let let 30 be heated.
このようにすると、 接着剤の接着性を低下させた後、 半導体素子を、 第 1 6図 に示すような真空チヤック 5 0でパレツ ト 3 0から剥離して搬送することが可能 となる。  In this way, after reducing the adhesiveness of the adhesive, the semiconductor element can be peeled off from the pallet 30 by a vacuum chuck 50 as shown in FIG. 16 and transported.
なお、 チップ状の半導体素子を回路基板に実装する際、 回路基板上のパターン のない部分に、 電気的接続と無関係なエキストラバンプを、 前記した各実施形態 方法によって形成することもできる。 このようにするとエキストラバンプがス ぺーサとして機能し、 半導体素子を回路基板に平行に実装することができる。 このとき、 回路基板のエキストラバンプと対応する部分にレジスト膜を形成し ておくと、 半導体素子の実装時にエキストラバンプが広がらず、 スぺ一サとして 確実に機能する。  When a chip-shaped semiconductor element is mounted on a circuit board, extra bumps irrelevant to electrical connection can be formed on portions of the circuit board where there is no pattern by the above-described embodiments. By doing so, the extra bump functions as a spacer, and the semiconductor element can be mounted in parallel with the circuit board. At this time, if a resist film is formed on a portion of the circuit board corresponding to the extra bump, the extra bump does not spread when the semiconductor element is mounted, and functions reliably as a spacer.
なお、 本発明は、 前記した実施形態の方法に限定されるものではなく、 要旨の 範囲内において、 種々変形実施が可能である。 産業上の利用可能性 本発明の半導体素子のバンプ形成方法は、 フリップチップ方式のほか、 T A B 方式の半導体素子のバンプ形成に適用することができる。  The present invention is not limited to the method of the embodiment described above, and various modifications can be made within the scope of the gist. INDUSTRIAL APPLICABILITY The method for forming a bump of a semiconductor device of the present invention can be applied to the formation of a bump of a TAB type semiconductor device in addition to the flip chip method.

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体素子のパッ ド電極上に粘着剤を付与する粘着剤処理工程、 粘着剤を 付与した部分に一又は二以上のはんだ粒子を付着させるはんだ粒子付着工程、 及 びはんだ粒子を溶融してバンプを形成するはんだ溶融工程とを有することを特徴 とした半導体素子のバンプ形成方法。 1. An adhesive treatment step of applying an adhesive on the pad electrode of the semiconductor element, a solder particle attachment step of attaching one or more solder particles to a portion to which the adhesive is applied, and melting of the solder particles. A method for forming a bump in a semiconductor device, comprising: a solder melting step of forming a bump.
2 . 半導体素子のパッ ド電極上に無電解メツキを行なうメツキ工程、 無電解 メツキ部分に粘着剤を付与する粘着剤処理工程、 粘着剤を付与した部分に一又は 二以上のはんだ粒子を付着させるはんだ拉子付着工程、 及びはんだ粒子を溶融し てバンプを形成するはんだ溶融工程とを有することを特徴とした半導体素子のバ ンプ形成方法。  2. An electroless plating process on the pad electrode of the semiconductor element, an adhesive treatment process of applying an adhesive to the electroless plating portion, and attaching one or more solder particles to the adhesive-applied portion. A method for forming a bump for a semiconductor device, comprising: a step of attaching a solder piece; and a step of melting a solder particle to form a bump.
3 . 前記はんだ粒子を溶融してバンプを形成する工程において、 バンプ内に金 属コアを介在させることを特徴とした請求の範囲第 1項又は第 2項記載の半導体 素子のバンプ形成方法。  3. The method for forming a bump of a semiconductor device according to claim 1, wherein a metal core is interposed in the bump in the step of melting the solder particles to form the bump.
4 . 金属コアを、 あらかじめ一部又は全部のはんだ粒子内に少なくとも一つ混 入させておくことにより、 はんだ溶融工程時にバンプ内に介在させることを特徴 とした請求の範囲第 3項記載の半導体素子のバンプ形成方法。  4. The semiconductor according to claim 3, wherein at least one metal core is previously mixed in some or all of the solder particles so that the metal core is interposed in the bump during the solder melting step. Device bump forming method.
5 . 金属コアを、 はんだ粒子と混合させて粘着剤を付与した部分に付着させる ことにより、 はんだ溶融工程時にバンプ内に介在させることを特徴とした請求の 範囲第 3項記載の半導体素子のノ ンプ形成方法。  5. The semiconductor device according to claim 3, wherein the metal core is mixed with the solder particles and adheres to the portion to which the adhesive is applied, so that the metal core is interposed in the bump during the solder melting step. Pump forming method.
6 . 金属コアを、 はんだ粒子付着工程と別個独立した粘着剤処理工程及び金属 コア付着工程で電極部分に付着させることにより、 はんだ溶融工程時にバンプ内 に介在させることを特徴とした請求の範囲第 3項記載の半導体素子のバンプ形成 方法。  6. The method according to claim 1, wherein the metal core is attached to the electrode portion in an adhesive treatment step and a metal core attachment step which are independent of the solder particle attachment step, so that the metal core is interposed in the bump during the solder melting step. 4. The method for forming a bump of a semiconductor device according to claim 3.
7 . 粘着剤処理工程とはんだ粒子のみの付着工程及びはんだ溶融工程を少なく とも一回付加したことを特徴とする請求の範囲第 1〜 6項のうちのいずれかの半 導体素子のバンプ形成方法。 7. The method for forming a bump of a semiconductor element according to any one of claims 1 to 6, wherein a pressure-sensitive adhesive treatment step, a solder particle attaching step, and a solder melting step are added at least once. .
8 . はんだ粒子内に混入された金属コアの直径が、 はんだ粒子の膜厚より小さ いことを特徴とした請求の範囲第 4項記載の半導体素子のバンプ形成方法。 8. The method according to claim 4, wherein the diameter of the metal core mixed into the solder particles is smaller than the thickness of the solder particles.
9 . 粘着剤処理工程とはんだ粒子付着工程及びはんだ溶融工程が、 高温はんだ 粘着剤処理工程と高温はんだ粒子付着工程及び高温はんだ溶融工程、 並びに、 低 温はんだ粘着剤処理工程と低温はんだ粒子付着工程及び低温はんだ溶融工程から なる請求の範囲第 1項又は第 2項記載の半導体素子の くンプ形成方法。  9. Adhesive treatment process, solder particle adhesion process and solder melting process are high temperature solder adhesive treatment process, high temperature solder particle adhesion process and high temperature solder fusion process, and low temperature solder adhesive treatment process and low temperature solder particle adhesion process 3. The method for forming a pump of a semiconductor device according to claim 1, comprising a low-temperature solder melting step.
1 0 . 高温はんだ粘着剤処理工程と高温はんだ粒子付着工程及び高温はんだ溶 融工程を行なった後に、 低温はんだ粘着剤処理工程と低温はんだ粒子付着工程及 び低温はんだ溶融工程を行ない、 高温はんだを金属コアとすることを特徴とした 請求の範囲第 9項記載の半導体素子のバンプ形成方法。  10. After performing the high-temperature solder adhesive treatment step, the high-temperature solder particle adhesion step, and the high-temperature solder melting step, the low-temperature solder adhesive treatment step, the low-temperature solder particle adhesion step, and the low-temperature solder fusion step are performed. 10. The method for forming a bump of a semiconductor device according to claim 9, wherein the bump is a metal core.
1 1 . 半導体素子が三箇所以上にパッ ド電極を有する場合において、 少なくと も三箇所のパッ ド電極に金属コアを介在させたバンプを形成することを特徴とし た請求の範囲第 3〜 1 0項のうちのいずれかの半導体素子のバンプ形成方法。  11. The semiconductor device according to claim 3, wherein when the semiconductor element has pad electrodes at three or more locations, a bump having a metal core interposed is formed on at least three of the pad electrodes. A method for forming a bump of a semiconductor device according to any one of the items 0.
1 2 . 少なくとも三箇所以上のパッ ド電極が、 予め定められた位置のパッ ド電 極であることを特徴とした請求の範囲第 1 1項記載の半導体素子のバンプ形成方 法。  12. The method for forming a bump of a semiconductor device according to claim 11, wherein at least three or more pad electrodes are pad electrodes at predetermined positions.
1 3 . 予め定められた三箇所又は四箇所のパッ ド電極が、 半導体素子の四隅の パッ ド電極であることを特徴とした請求の範囲第 1 2項記載の半導体素子のバン プ形成方法。  13. The bump forming method for a semiconductor device according to claim 12, wherein the predetermined three or four pad electrodes are pad electrodes at four corners of the semiconductor device.
1 4 . ウェハ一状態にある半導体素子に請求の範囲第 1 〜 1 3項のうちのいず れかの方法でバンプを形成することを特徴とした半導体素子のバンプ形成方法。  14. A bump forming method for a semiconductor device, comprising: forming a bump on a semiconductor device in a wafer state by any one of claims 1 to 13.
1 5 . チップ伏態にある半導体素子に請求の範囲第 1〜 1 3項のうちのいずれ かの方法でバンプを形成することを特徴とした半導体素子のバンプ形成方法。  15. A bump forming method for a semiconductor device, comprising: forming a bump on a semiconductor device in a chip-down state by the method according to any one of claims 1 to 13.
1 6 . チップ状態にある半導体素子が、 パレツ ト上に接着剤で保持されている ことを特徴とした請求の範囲第 1 5項記載の半導体素子のバンプ形成方法。  16. The method for forming a bump of a semiconductor device according to claim 15, wherein the semiconductor device in a chip state is held on a pallet with an adhesive.
1 7 . パレツ ト上に保持されているチップ状態にある半導体素子を、 パレツ ト から剥離してトレイ上に整列させることを特徴とした請求の範囲第〗 6項記載の 半導体素子のバンプ形成方法。 17. The method for forming a bump of a semiconductor element according to claim 6, wherein the semiconductor element in a chip state held on the pallet is peeled off from the pallet and aligned on a tray. .
1 8 . チップ状態にある半導体素子をパレツ 卜から剥雜する際、 接着剤の接着 性を熱によつて低下させることを特徴とした請求の範囲第 1 7項記載の半導体素 子のバンプ形成方法。 18. The bump formation of a semiconductor device according to claim 17, wherein when the semiconductor device in a chip state is peeled off from the pallet, the adhesiveness of the adhesive is reduced by heat. Method.
1 9 . チップ状態にある半導体素子をパレツ 卜から剥離する際、 接着剤の接着 性を光によって低下させることを特徵とした請求の範囲第 1 7項記載の半導体素 子のバンプ形成方法。  19. The method for forming a bump of a semiconductor device according to claim 17, wherein when the semiconductor device in a chip state is separated from the pallet, the adhesiveness of the adhesive is reduced by light.
PCT/JP1996/002871 1995-11-15 1996-10-03 Method for forming bump of semiconductor device WO1997018584A1 (en)

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