JPS60116157A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60116157A JPS60116157A JP22474483A JP22474483A JPS60116157A JP S60116157 A JPS60116157 A JP S60116157A JP 22474483 A JP22474483 A JP 22474483A JP 22474483 A JP22474483 A JP 22474483A JP S60116157 A JPS60116157 A JP S60116157A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- electrode
- powder
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
- H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体素子チップの電極パッド部の措造に係り
、回路基板」ニへ容易に、信頼性良く最少面積で実装で
きる半導体装置を提供するものである。[Detailed Description of the Invention] Industrial Application Field The present invention relates to the structure of an electrode pad portion of a semiconductor element chip, and provides a semiconductor device that can be easily and reliably mounted on a circuit board with a minimum area. It is.
従来例の構成とその問題点
近年、電子機器の小形、軽緻、薄形など、いわゆる軽薄
短小の動さが益々活発となってきた。半導体装置として
もこれらニーズに合せ高機能化、小形化への対応をはか
っている。半導体装置としては従来、デュアルインライ
ンパッケージ（ＤＩＬ）やフラットパッケージ（ＦＰ）
で代表されるように樹脂モールドを施したものがほとん
どである。Conventional configurations and their problems In recent years, electronic devices have become increasingly compact, light, compact, and thin, so-called light, thin, and short. In response to these needs, semiconductor devices are also becoming more sophisticated and smaller. Conventionally, semiconductor devices have been manufactured using dual in-line packages (DIL) and flat packages (FP).
Most of them are resin molded, as exemplified by.
したがって電子機器の軽薄短小化への対応がこれら半導
体装置の形状では困難となっている。Therefore, it is difficult to respond to the trend toward lighter, thinner, and shorter electronic devices due to the shape of these semiconductor devices.
半導体装置を最も小さく回路基板に実装する手段として
コ１′−導体素子をチップ状で取扱う方法が各種考案さ
れている。代表的な方法の一つとして、フリップチップ
がある。これは半導体素子チップの電極部、すなわちア
ルミパッド上に金属薄膜とノ・ンダメッキにより突起電
極を）投け、この半導体素子チップを回路基板上へフェ
イスダウンで実装するものである。この突起電極はバン
プと呼ばれ、半導体素子チップのアルミパッドを含む素
子全面にチタンやクロムのようなアルミと密着性の良好
な金属をエレクトロンビーム蒸着または抵抗加熱蒸着法
によって第一の薄膜を形成、さらに第二の薄膜として銅
、バラジューム、白金、金などの金属を先と同じ蒸着に
よって形成する。次にアルミパッド部以外をレジストコ
ートし、先の金属膜を電極としてスズと鉛の電気メッキ
を適当な高さく厚み）にメッキした後、レジストを剥９
１１する。次にスズと鉛の部分にレジストをかけて、第
一および第二の金属膜をエツチングで除去し、レジスト
を剥離した後、還元雰囲気中または空気中でスズと鉛の
メッキ層を溶融させハンダとする。このときハンダの表
面張力により半球状のいわゆるハンダバンプか形成され
る。このようにして作られた半導体装置は回路基板にフ
ェイスダウンによって載置、加熱することによって回路
基板上の電極へハンダ（＝Ｊけされ、電気的接続か成さ
れる。この方法によれば蒸着法による薄膜形成、電気メ
ッキによるハンダ形成、フォトリソによるエツチング等
の複雑な工程を必要とすることと、回路基板」二の電極
を十分なハンダ（＝Ｊけ強度を得るためハンダ里を多く
必要とし、パッド間隔も２００〜３００ミクロンが必要
となる。以上のような半導体装置の製造が複雑であるこ
とによるコストアップとパッド間隔か規制されることに
よる半導体素子チップ上のパッド数の限定など多くの問
題を有する。また、クリップチップは回路基板上へハン
ダ付けによって実装するもので回路基板、例えば液晶パ
ネルの如き金属酸化物透明電極（ＩＴＯ）上へ直接実装
する場合などは先にＩＴＯをハンダ付けできるようにメ
タライズしておかなければならず液晶パネルの製造にお
いても複雑となり、パネルコストのアンプとなる。Various methods of handling co-conductor elements in the form of chips have been devised as a means of packaging semiconductor devices on circuit boards in the smallest size possible. One of the typical methods is flip chip. In this method, a protruding electrode is placed on the electrode part of a semiconductor element chip (that is, an aluminum pad) using a metal thin film and solder plating, and the semiconductor element chip is mounted face down onto a circuit board. This protruding electrode is called a bump, and a first thin film of a metal such as titanium or chromium that has good adhesion to aluminum is formed on the entire surface of the semiconductor element chip, including the aluminum pad, by electron beam evaporation or resistance heating evaporation method. Then, as a second thin film, a metal such as copper, baladium, platinum, or gold is formed by the same vapor deposition as before. Next, apply a resist coat to the area other than the aluminum pad, and use the previous metal film as an electrode to electroplate tin and lead to an appropriate height and thickness, and then peel off the resist.
11. Next, resist is applied to the tin and lead parts, the first and second metal films are removed by etching, the resist is peeled off, and the tin and lead plating layers are melted in a reducing atmosphere or in the air and soldered. shall be. At this time, a hemispherical so-called solder bump is formed due to the surface tension of the solder. The semiconductor device made in this way is placed face down on a circuit board and heated to solder it to the electrodes on the circuit board to form an electrical connection. It requires complicated processes such as thin film formation by electroplating, solder formation by electroplating, and etching by photolithography, and it also requires a large amount of solder to obtain sufficient solder strength for the second electrode of the circuit board. In addition, the pad spacing is also required to be 200 to 300 microns.There are many problems such as increased costs due to the complexity of semiconductor device manufacturing as described above, and restrictions on the number of pads on the semiconductor element chip due to restrictions on pad spacing. Also, clip chips are mounted on a circuit board by soldering, so when mounting directly on a circuit board, such as a metal oxide transparent electrode (ITO) such as a liquid crystal panel, it is necessary to solder the ITO first. It is necessary to metalize the liquid crystal panel to make it possible, which complicates the manufacturing process of the liquid crystal panel and increases the panel cost.
発り−（の ［」自（Ｊ
本発明はチップ状で回路基板に最少面積で実装すること
、およびコストの低減を目的とする半導体装置に関する
ものである。The present invention relates to a semiconductor device which is in the form of a chip and is mounted on a circuit board with a minimum area, and whose purpose is to reduce costs.
発明の構成
」二記目的を達成するために本発明の半導体装置はアル
ミ電極パッド部に光硬化性樹脂と導電粉からなる第一の
等方導電層と、この第一の等方導電層」二もしくは半導
体素子チップの一生面に熱可塑性樹脂と導電粉からなる
第二の異方性導電層を形成したことを特徴とするもので
ある。In order to achieve the object described in item 2 of "Structure of the Invention", the semiconductor device of the present invention includes a first isotropically conductive layer made of a photocurable resin and conductive powder on an aluminum electrode pad portion, and this first isotropically conductive layer. The present invention is characterized in that a second anisotropic conductive layer made of a thermoplastic resin and conductive powder is formed on the entire surface of the semiconductor element chip.
実施例の説９ｊ 以下、本発明の半導体装置の実施例について説明する。Example theory 9j Examples of the semiconductor device of the present invention will be described below.
本発明は半導体素子チップのアルミ電極パッド部のバン
プの構造に係り、二層のそれぞれ異なる特性を持つ合成
樹脂系の導電４′Ａをバンプとするもので、第一の等方
専電層は感光性を有する樹脂、例えばエポキシアクリレ
ートオリゴマー、アクリレートモノマーやアクリレート
化されたポリイミド樹脂等が使用できる。この樹脂に導
電粉として透光性を有するイ広属酸化物粉、例えは酸化
スズ。The present invention relates to the structure of a bump on an aluminum electrode pad portion of a semiconductor element chip, in which the bump is made of two layers of conductive 4'A made of synthetic resin each having different characteristics, and the first isotropic exclusive layer is Photosensitive resins such as epoxy acrylate oligomers, acrylate monomers, and acrylated polyimide resins can be used. This resin is a conductive powder containing a translucent oxide powder, such as tin oxide.
酸化インジーラム等の微粉末を前記樹脂１００屯量部に
３０−７０屯量部加え均質に分散させた塗料・とする。A paint is prepared by adding 30 to 70 parts by volume of fine powder such as oxidized injeram to 100 parts by volume of the resin and homogeneously dispersing it.
この検相・を半導体素子チップの全曲にコーティングし
、ｆ（Ｊｉｉｉ乾燥した後、マスクを介しアルミパッド
部をｊ落光する。未露光部は現像して除去し、アルミパ
ッド−ＬＫ影形成れた第一の導電層はポストギュアし１
分硬化させる。この第一の等方導電層は半堺体素ｒテッ
プの電極と回路基板の電極との雷値α１結合ΔせＡ目的
のイ、のτす祖−誼は低くする必要がある。またこの第
一の等方導電層は通常のバンプと同様に半導体素子チッ
プ表面から必要な高さく５〜５０ミクロン）に形成し、
半導体素子チップをフェイスダウンで実装したとき半導
体素子にチップ表面が回路基板に当たらないようにする
目的もある。第二の異方性導電層は半導体素子チップの
能動素子面全面に形成し、回路基板上の電極との接着固
定と垂直方向の導電性を得る目的で使用される。この第
二の異方性導電層は熱用塑性樹脂、熱硬化性樹脂または
その併用でも本発明の目的は達成されるが、信頼性、半
導体素子チップ上に形成した二層のポットライフなとか
ら熱’＝ｆ塑性樹脂か有効である。導電粉は第一の層と
異なり光を透過させる必要がなく粒子径は大きくても良
い。この第二の異方性導電層の最も大きな４．Ｊ′徴は
異方性の導電性を付与することにある。垂直方向にノ９
電性を有し、水平方向、すなわち、半３Ｑ体素子チップ
の面方向は絶縁となるものである。第１図で本発明の作
用について説明する。After coating the entire surface of the semiconductor element chip with this phase detection solution and drying it, the aluminum pad part is exposed to light through a mask.The unexposed part is developed and removed, and the aluminum pad-LK shadow is formed. The first conductive layer is post-guarded 1
Let it harden for a minute. This first isotropic conductive layer must have a low value of α1 coupling Δ1 between the electrode of the semicircular element and the electrode of the circuit board. In addition, this first isotropic conductive layer is formed at the required height (5 to 50 microns) from the surface of the semiconductor element chip in the same way as a normal bump,
Another purpose is to prevent the chip surface of the semiconductor element from coming into contact with the circuit board when the semiconductor element chip is mounted face down. The second anisotropic conductive layer is formed over the entire surface of the active element of the semiconductor element chip, and is used for the purpose of adhesion and fixation with electrodes on the circuit board and to obtain vertical conductivity. Although the purpose of the present invention can be achieved by using thermoplastic resin, thermosetting resin, or a combination thereof for this second anisotropic conductive layer, reliability and pot life of the two layers formed on the semiconductor element chip may be affected. Since heat'=f plastic resin is valid. Unlike the first layer, the conductive powder does not need to transmit light and may have a large particle size. The largest 4. of this second anisotropic conductive layer. The J' feature is to provide anisotropic conductivity. No.9 vertically
It has electrical properties and is insulated in the horizontal direction, that is, in the plane direction of the half-3Q element chip. The operation of the present invention will be explained with reference to FIG.
第１図は半導体素子チップのアルミパッド部分の断面を
示し、シリコン基板からなる半導［本素子チップ１の上
面に形成したアルミパッド部３はパッシベーション膜２
で一部覆われていてアルミパッド部で形成され、さらに
全面に第二の異方性導電層５が形成される。この第二の
異方性導電層６の中に導電粉６か点在している。以」二
の構成において、この半導体素子チップ１を回路基板へ
実装したときの状態を第２図に示す。・回路基板７」二
に形成された電極８に゛）′−導体素子チツブ１を載置
し加圧加熱することによって第二の異方性導電層５の樹
脂かメルトし回路基板７の電極８に接着すると同時に第
二の異方性導電層５の中に点在する導電粉６が半導体素
子テップ１の第一の等方性専電層４と電極８の間に挟み
込まれ半導体素子チップ１と回路基板７０電極８とか電
気的１機械的に結合する。しかも加圧されない部分の導
電粉６は粒子間に樹脂が介在しており完全な絶縁膜とな
る。FIG. 1 shows a cross section of an aluminum pad portion of a semiconductor element chip.
A second anisotropic conductive layer 5 is formed on the entire surface. Conductive powder 6 is scattered within this second anisotropic conductive layer 6. FIG. 2 shows the state when this semiconductor element chip 1 is mounted on a circuit board in the second configuration.・By placing the conductive element chip 1 on the electrode 8 formed on the circuit board 7 and heating it under pressure, the resin of the second anisotropic conductive layer 5 melts and forms the electrode of the circuit board 7. At the same time, the conductive powder 6 dotted in the second anisotropic conductive layer 5 is sandwiched between the first isotropic exclusive layer 4 of the semiconductor element chip 1 and the electrode 8, thereby forming a semiconductor element chip. 1 and the circuit board 70 and the electrode 8 are electrically and mechanically coupled. Furthermore, the portions of the conductive powder 6 that are not pressurized have resin interposed between the particles, forming a complete insulating film.
次に不発り」の具体的な実施例について説明する。Next, a specific example of "non-explosion" will be explained.
第一の等方導電層４の伺料として以下の配合で塗料化し
た。A paint was prepared as a coating material for the first isotropic conductive layer 4 using the following formulation.
感光性樹脂〔東しく株）の商品名：フォトニース〕・・
・・・・・・・・・・・・１００重量部導電粉〔三菱金
属（株）酸化スズ粉〕
・・・・・・・・・・・・・ ３ｏ重量部溶剤〔Ｎ−メ
チル−２−ピロリドン関東化学〕・・・・・・・・・・
・・・・・ ５重量部第二の異方性導電層５の桐料とし
て以下の配合で塗料化した。Product name of photosensitive resin [Toshiku Co., Ltd.: Photonice]...
・・・・・・・・・・・・100 parts by weight Conductive powder [Mitsubishi Metals Co., Ltd. tin oxide powder] ・・・・・・・・・・・・・・・ 30 parts by weight Solvent [N-methyl-2 -Pyrrolidone Kanto Chemical]・・・・・・・・・・
... 5 parts by weight As a paulownia material for the second anisotropic conductive layer 5, a paint was prepared with the following formulation.
ポリエステル樹脂〔東洋紡（株）の商品名：バイロン〕
・・・・・・・・・・・・・・・１００重量部導電粉〔
三菱金属（株）酸化スズ粉〕
′・・・・・・・・・・・・・・・ ３重量部溶剤［Ｍ
ＥＫ 関東化学製〕
・・・・・・・・・・・・ ５０重量部それぞれの塗料
を０ＭＯ８が形成された４インチウェハー上にスピナー
でコーティングし、第一の等方導電層４は厚みが１０ミ
クロンになるよう形成し、８０℃６０分のポストキュア
後アルミパッド部のみ紫外線（１２ｏ’ｗ ／ ｃｍ
）で３０秒露光して、現像液にて未露光部を除去した。Polyester resin [Product name of Toyobo Co., Ltd.: Byron]
・・・・・・・・・・・・・・・100 parts by weight conductive powder [
Mitsubishi Metals Co., Ltd. tin oxide powder] '・・・・・・・・・・・・・・・ 3 parts by weight Solvent [M
EK manufactured by Kanto Kagaku] 50 parts by weight of each paint was coated with a spinner on a 4-inch wafer on which 0MO8 was formed, and the first isotropic conductive layer 4 was After post-curing at 80℃ for 60 minutes, only the aluminum pad part was exposed to ultraviolet light (12o'w/cm).
) for 30 seconds, and the unexposed areas were removed using a developer.
さらにポストキュアとして２００℃３０分、３００℃３
０分、４００℃３０分のステップでキー７し第一の持方
導電層４とした。さらに第二の異方性導電層５として同
様にスピナーで厚みが１０ミクロンになるよう全面に塗
布し、１１０℃６０分で乾燥させた。このウェハーを所
定のチップ寸法にダイシングし完成品を得た。この半導
体素子チップ１を回路基板（ガラス上に形成されたＩＴ
○回路基板）７に載置し半導体素子チップ１の裏面から
１５０℃加熱ツールと３０匁の圧力で押え接続させた。Furthermore, as a post cure, 200℃ 30 minutes, 300℃ 3
The first conductive layer 4 was formed by heating at 400° C. for 30 minutes. Further, a second anisotropic conductive layer 5 was similarly applied to the entire surface using a spinner to a thickness of 10 microns, and dried at 110° C. for 60 minutes. This wafer was diced into a predetermined chip size to obtain a finished product. This semiconductor element chip 1 is connected to a circuit board (IT formed on glass).
○Circuit board) 7, and the semiconductor element chip 1 was pressed from the back side with a 150° C. heating tool at a pressure of 30 momme.
その後、回路基板７の電気的特性をチェックしたところ
完全に所定の動作が得られることをｌｌ６ｉ認した。Thereafter, when the electrical characteristics of the circuit board 7 were checked, it was found that the circuit board 7 was able to perform perfectly as expected.
発明の効果
本発明はそれぞれ異なった二種類の導電層をバンプとし
て半導体素子に形成することによって従来の７リノプチ
ソプのような複雑な工程を必要とせず、しかもｆｉｌ単
な設備で製造がｒｉｆ能となった。Effects of the Invention By forming two different types of conductive layers as bumps on a semiconductor element, the present invention does not require a complicated process like the conventional 7Rinopti-Sop, and can be manufactured using a simple fil equipment. became.
これはチップコストの大巾な低減と従来半導体メーカー
しかできなかったバンプ技術を半導体ユーザー側でも作
成できるようになることなど大きな特徴を有するもので
ある。また、本発明の二種類の導電層はそれぞれの機能
を有し、特に第二の異方性導電層は、半導体素子チップ
全面に塗布されており、接着と半部方向の導通を得るは
かりでなく、従来この種半導体素子チップで回路基板に
実装した場合は十分な保護か必要で特に湿度に対する保
護は非常に困難とされていたが、この第二の異方性導電
層によってかなりの保護効果が達成される。以」二のよ
うに本発明はチップコストの犬「１」な低減と、軽薄短
小の市場ニーズにマツチングする最少の実装を可能とす
るものである。またユーザー…りで製造することもｉノ
能となり今後の半導体産業に寄与するものである。This has major features such as a drastic reduction in chip costs and the ability for semiconductor users to create bump technology that was previously only available to semiconductor manufacturers. In addition, the two types of conductive layers of the present invention have their respective functions, and in particular, the second anisotropic conductive layer is coated on the entire surface of the semiconductor element chip, and is used as a means to obtain adhesion and conduction in half directions. Conventionally, when this type of semiconductor element chip was mounted on a circuit board, sufficient protection was required, and protection against humidity was extremely difficult, but this second anisotropic conductive layer has a considerable protective effect. is achieved. As described above, the present invention enables a drastic reduction in chip cost and minimal packaging that meets the market needs for light, thin, short, and small devices. In addition, manufacturing by the user will also become an i-nobility and will contribute to the future semiconductor industry.
第１図は不発り−１の半導体装置の一実施例を示す断面
図、第２図は同半導体装置を実装した状態の断面図であ
る。
１・・・・・・半導体素子チップ、２・・・・・・パッ
シベーション膜、３・・・・・・アルミバッド、４・・
・・・・第一の等方性導電層、６・・・・・・第二の異
方性導電層、６・・・・・・導電粉、７・・・・・・回
路基板、８・・・・・・電極。FIG. 1 is a sectional view showing an embodiment of the non-explosion-1 semiconductor device, and FIG. 2 is a sectional view of the same semiconductor device in a mounted state. 1...Semiconductor element chip, 2...Passivation film, 3...Aluminum pad, 4...
...First isotropic conductive layer, 6... Second anisotropic conductive layer, 6... Conductive powder, 7... Circuit board, 8 ······electrode.
Claims (2)
脂と導電粉からなる第一の等方導電層と、該第−の導電
層上、もしくは半導体素子チップの一主面に熱可塑性樹
脂と導電粉からなる第二の異方性導電層を形成したこと
を特徴とする半導体装置。(1) A first isotropic conductive layer made of a photocurable resin and conductive powder is placed on the electrode pad portion of the semiconductor quick chip, and a thermoplastic resin is placed on the second conductive layer or on one main surface of the semiconductor element chip. and a second anisotropic conductive layer made of conductive powder.
請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the conductive powder is a metal oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474483A JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474483A JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60116157A true JPS60116157A (en) | 1985-06-22 |
| JPH031828B2 JPH031828B2 (en) | 1991-01-11 |
Family
ID=16818554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22474483A Granted JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60116157A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243138A (en) * | 1985-08-21 | 1987-02-25 | Seiko Instr & Electronics Ltd | Ic mounting structure of liquid crystal display apparatus |
| JPS6347942A (en) * | 1986-08-18 | 1988-02-29 | Fuji Xerox Co Ltd | Semiconductor device |
| EP0265077A2 (en) * | 1986-09-25 | 1988-04-27 | Sheldahl, Inc. | An anisotropic adhesive for bonding electrical components |
| FR2618254A1 (en) * | 1987-07-16 | 1989-01-20 | Thomson Semiconducteurs | METHOD AND STRUCTURE FOR TAKING CONTACT ON INTEGRATED CIRCUIT PLOTS. |
| JPH0195553A (en) * | 1987-10-08 | 1989-04-13 | Sony Corp | Solid-state image sensing device |
| JPH01132138A (en) * | 1987-08-13 | 1989-05-24 | Shin Etsu Polymer Co Ltd | Electrical connection method of ic chip, material for resin bump formation and liquid crystal display |
| JPH0234951A (en) * | 1988-04-20 | 1990-02-05 | Seiko Epson Corp | Mounting structure for semiconductor device |
| JPH02199847A (en) * | 1989-01-27 | 1990-08-08 | Shin Etsu Polymer Co Ltd | Mounting of ic chip |
| JPH04262890A (en) * | 1990-09-27 | 1992-09-18 | Motorola Inc | Flux agent and adhesive containing metal particle |
| EP0734065A2 (en) * | 1995-03-24 | 1996-09-25 | Shinko Electric Industries Co. Ltd. | Chip sized semiconductor device |
| WO1997018584A1 (en) * | 1995-11-15 | 1997-05-22 | Citizen Watch Co., Ltd. | Method for forming bump of semiconductor device |
| US6204164B1 (en) * | 1995-08-21 | 2001-03-20 | Mitel Corporation | Method of making electrical connections to integrated circuit |
| US6396712B1 (en) * | 1998-02-12 | 2002-05-28 | Rose Research, L.L.C. | Method and apparatus for coupling circuit components |
| JP2007294916A (en) * | 2006-03-31 | 2007-11-08 | Brother Ind Ltd | Connecting structure, method of forming bump and the like |
-
1983
- 1983-11-29 JP JP22474483A patent/JPS60116157A/en active Granted
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243138A (en) * | 1985-08-21 | 1987-02-25 | Seiko Instr & Electronics Ltd | Ic mounting structure of liquid crystal display apparatus |
| JPS6347942A (en) * | 1986-08-18 | 1988-02-29 | Fuji Xerox Co Ltd | Semiconductor device |
| EP0265077A2 (en) * | 1986-09-25 | 1988-04-27 | Sheldahl, Inc. | An anisotropic adhesive for bonding electrical components |
| EP0265077A3 (en) * | 1986-09-25 | 1989-03-08 | Sheldahl, Inc. | An anisotropic adhesive for bonding electrical components |
| FR2618254A1 (en) * | 1987-07-16 | 1989-01-20 | Thomson Semiconducteurs | METHOD AND STRUCTURE FOR TAKING CONTACT ON INTEGRATED CIRCUIT PLOTS. |
| JPH01132138A (en) * | 1987-08-13 | 1989-05-24 | Shin Etsu Polymer Co Ltd | Electrical connection method of ic chip, material for resin bump formation and liquid crystal display |
| JPH0195553A (en) * | 1987-10-08 | 1989-04-13 | Sony Corp | Solid-state image sensing device |
| JPH0234951A (en) * | 1988-04-20 | 1990-02-05 | Seiko Epson Corp | Mounting structure for semiconductor device |
| JPH02199847A (en) * | 1989-01-27 | 1990-08-08 | Shin Etsu Polymer Co Ltd | Mounting of ic chip |
| JPH04262890A (en) * | 1990-09-27 | 1992-09-18 | Motorola Inc | Flux agent and adhesive containing metal particle |
| EP0734065A2 (en) * | 1995-03-24 | 1996-09-25 | Shinko Electric Industries Co. Ltd. | Chip sized semiconductor device |
| EP0734065A3 (en) * | 1995-03-24 | 1997-03-05 | Shinko Electric Ind Co | Chip sized semiconductor device |
| US6204164B1 (en) * | 1995-08-21 | 2001-03-20 | Mitel Corporation | Method of making electrical connections to integrated circuit |
| WO1997018584A1 (en) * | 1995-11-15 | 1997-05-22 | Citizen Watch Co., Ltd. | Method for forming bump of semiconductor device |
| US6066551A (en) * | 1995-11-15 | 2000-05-23 | Citizen Watch Co., Ltd. | Method for forming bump of semiconductor device |
| US6396712B1 (en) * | 1998-02-12 | 2002-05-28 | Rose Research, L.L.C. | Method and apparatus for coupling circuit components |
| JP2007294916A (en) * | 2006-03-31 | 2007-11-08 | Brother Ind Ltd | Connecting structure, method of forming bump and the like |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH031828B2 (en) | 1991-01-11 |
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